CS5505/6/7/8
CS5505/6/7/8
CS5505/6/7/8
CDB5505/6/7/8
Evaluation
Very
Low-power,
Board16-Bit
for
16-bit
CS5505/6/7/8
& 20-bit
Series
Converters
of ADCs
Very
Low
Power,
and
20-BitA/D
A/D
Converters
Features
Description
l Very
The CS5505/6/7/8 are a family of low power CMOS A/D
converters which are ideal for measuring low-frequency
signals representing physical, chemical, and biological
processes.
Low Power Consumption
- Single supply +5 V operation: 1.7 mW
- Dual supply ±5 V operation: 3.2 mW
l Offers
superior performance to VFCs and
multi-slope integrating ADCs
l Differential Inputs
- Single Channel (CS5507/8) and Four-Channel
(CS5505/6) pseudo-differential versions
l Either
5 V or 3.3 V Digital Interface
l Linearity Error:
The CS5507/8 have single-channel differential analog
and reference inputs while the CS5505/6 have four
pseudo-differential analog input channels. The
CS5505/7 have a 16-bit output word. The CS5506/8
have a 20-bit output word.The CS5505/6/7/8 sample
upon command up to 100 Sps.
The on-chip digital filter offers superior line rejection at
50 and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
- ±0.0015% FS (16-bit CS5505/7)
- ±0.0007% FS (20-bit CS5506/8)
The CS5505/6/7/8 include on-chip self-calibration circuitry which can be initiated at any time or temperature
to ensure minimum offset and full-scale errors.
l Output
update rates up to 100 Sps
l Flexible Serial Port
l Pin-Selectable Unipolar/Bipolar Ranges
The CS5505/6/7/8 serial port offers two general-purpose
modes for the direct interface to shift registers or synchronous
serial
ports
of
industry-standard
microcontrollers.
ORDERING INFORMATION
See page 30.
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Cirrus Logic, Inc.
Crystal
Semiconductor Products Division
http://www.cirrus.com
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright
© Cirrus
Copyright © Cirrus
Logic, Inc.
2005Logic, Inc. 1997
(All Rights Reserved)
(All Rights Reserved)
MAR
AUG ‘95
‘05
DS59F4
DS59DB3
DS59F5
1
CS5505/6/7/8
CS5505/6/7/8
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V(external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF
to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
CS5505/7-A
Parameter*
Min
Specified Temperature Range
Typ
CS5507-S
Max
Min
-40 to +85
Typ
Max
Units
°C
-55 to +125
Accuracy
Linearity Error
-
0.0015
0.003
-
0.0015
0.003
±%FS
Differential Nonlinearity
-
±0.25
±0.5
-
±0.25
±0.5
LSB16
Full Scale Error
(Note 3)
-
±0.25
±2
-
±0.5
±2
LSB16
Full Scale Drift
(Note 4)
-
±0.5
-
-
±2
-
LSB16
Unipolar Offset
(Note 3)
-
±0.5
±2
-
±1
±4
LSB16
Unipolar Offset Drift
(Note 4)
-
±0.5
-
-
±1
-
LSB16
Bipolar Offset
(Note 3)
-
±0.25
±1
-
±0.5
±2
LSB16
Bipolar Offset Drift
(Note 4)
-
±0.25
-
-
±0.5
-
LSB16
-
0.16
-
-
0.16
-
LSBrms16
Noise (Referred to Output)
Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the
master clock frequency. Both source resistance and shunt capacitance are therefore critical in
determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the
text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25°C.
Recalibration at any temperature will remove these errors.
mV
10
19
38
76
152
LSB’s
0.26
0.50
1.00
2.00
4.00
Unipolar Mode
% FS
0.0004
0.0008
0.0015
0.0030
0.0061
ppm FS
LSB’s
4
0.13
8
0.26
15
0.50
30
1.00
61
2.00
VREF = 2.5V
Bipolar Mode
% FS
0.0002
0.0004
0.0008
0.0015
0.0030
ppm FS
2
4
8
15
30
CS5505/7; 16-Bit Unit Conversion Factors
* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.
2
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
CS5506/8-B
Parameter*
Min
Specified Temperature Range
Typ
CS5508-S
Max
Min
-40 to +85
Typ
Max
Units
°C
-55 to +125
Accuracy
Linearity Error
Differential Nonlinearity
(No Missing Codes)
-
0.0007
0.0015
-
0.0015
0.003
20
-
-
20
-
-
±%FS
Bits
Full Scale Error
(Note 3)
-
±4
±32
-
±8
±32
LSB20
Full Scale Drift
(Note 4)
-
±8
-
-
±32
-
LSB20
Unipolar Offset
(Note 3)
-
±8
±32
-
±16
±64
LSB20
Unipolar Offset Drift
(Note 4)
-
±8
-
-
±16
-
LSB20
Bipolar Offset
(Note 3)
-
±4
±16
-
±8
±32
LSB20
Bipolar Offset Drift
(Note 4)
-
±4
-
-
±8
-
LSB20
-
2.6
-
-
2.6
-
LSBrms20
Noise (Referred to Output)
mV
0.596
1.192
2.384
4.768
9.537
LSB’s
0.25
0.50
1.00
2.00
4.00
Unipolar Mode
% FS
0.0000238
0.0000477
0.0000954
0.0001907
0.0003814
ppm FS
LSB’s
0.24
0.13
0.47
0.26
0.95
0.50
1.91
1.00
3.81
2.00
VREF = 2.5V
Bipolar Mode
% FS
0.0000119
0.0000238
0.0000477
0.0000954
0.0001907
ppm FS
0.12
0.24
0.47
0.95
1.91
CS5506/8; 20-Bit Unit Conversion Factors
DYNAMIC CHARACTERISTICS
Parameter
Modulator Sampling Frequency
Output Update Rate (CONV = 1)
Filter Corner Frequency
Settling Time to 1⁄2 LSB (FS Step)
DS59F4
DS59F5
Symbol
fs
fout
f-3dB
ts
Ratio
fclk/2
fclk/1622
fclk/1928
1/fout
Units
Hz
Sps
Hz
s
3
CS5505/6/7/8
CS5505/6/7/8
ANALOG CHARACTERISTICS (TA = TMIN to TMAX;
VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
CS5505/7
CS5506/8
Parameter*
Min
Specified Temperature Range
Typ
CS5507/8-S
Max
Min
Typ
Max
Units
-40 to +85
-55 to +125
°C
0 to +2.5
±2.5
0 to +2.5
±2.5
Volts
Volts
Analog Input
Analog Input Range:
(VAIN+)-(VAIN-)
Unipolar
Bipolar
(Note 5)
Common Mode Rejection:
dc
50, 60 Hz (Note 6)
120
105
-
-
120
105
-
-
dB
dB
Off Channel Isolation
-
120
-
-
120
-
dB
Input Capacitance
-
15
-
-
15
-
pF
-
5
-
-
5
-
nA
VREFOUT Voltage
-
(VA+)-2.5
-
-
(VA+)-2.5
-
Volts
VREFOUT Voltage Tolerance
-
-
4.0
-
-
4.0
%
VREFOUT Voltage Temperature Coefficient
-
60
-
-
60
-
ppm/°C
VREFOUT Line Regulation
-
1.5
-
-
1.5
-
mV/Volt
VREFOUT Output Voltage Noise
0.1 to 10 Hz
-
50
-
-
50
-
µVp-p
-
-
3
50
-
-
3
50
µA
µA
ITotal
IAnalog
IDigital
-
340
300
40
450
-
-
340
300
40
450
-
µA
µA
µA
(Note 7)
SLEEP inactive
SLEEP active
-
3.2
5
4.5
10
-
3.2
10
4.5
25
mW
µW
Power Supply Rejection: Positive Supplies
Negative Supplies
-
80
80
-
-
80
80
-
dB
dB
DC Bias Current
(Note 1)
Voltage Reference (Output)
VREFOUT:
Source Current
Sink Current
Power Supplies
DC Power Supply Currents:
Power Dissipation:
Notes: 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. XIN = 32.768 kHz. Guaranteed by design and / or characterization.
7. All outputs unloaded. All inputs CMOS levels. SLEEP mode controlled by M/SLP pin.
SLEEP active = M/SLP pin at (VD+)/2 input level.
4
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX;
VA+VD+ = 5V ± 10%; VA-= -5V ± 10%;
DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage:
XIN
M/SLP
All Pins Except XIN and M/SLP
VIH
VIH
VIH
3.5
0.9VD+
2.0
-
-
V
V
V
Low-Level Input Voltage:
XIN
M/SLP
All Pins Except XIN and M/SLP
VIL
VIL
VIL
-
-
1.5
0.1VD+
0.8
V
V
V
M/SLP SLEEP Active Threshold
(Note 8)
VSLP
0.45VD+
0.5VD+
0.55VD+
V
High-Level Output Voltage
(Note 9)
VOH
(VD+)-1.0
-
-
V
VOL
-
-
0.4
V
Input Leakage Current
Iin
-
1
10
µA
3-State Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
9
-
pF
Low Level Output Voltage
Iout = 1.6 mA
Notes: 8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP
pin enters the SLEEP active threshold range the device will enter the power down condition. Returning
to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse
of the wake-up period.
9. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 µA).
3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX;
VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter
High-Level Input Voltage:
Low-Level Input Voltage:
Symbol
Min
Typ
Max
Units
XIN
M/SLP
All Pins Except XIN and M/SLP
VIH
0.7VD+
0.9VD+
0.6VD+
-
-
V
V
V
XIN
M/SLP
All Pins Except XIN and M/SLP
VIL
-
-
0.3VD+
0.1VD+
0.16VD+
V
V
V
VSLP
0.43VD+ 0.45VD+ 0.47VD+
V
M/SLP SLEEP Active Threshold
(Note 8)
VIH
VIH
VIL
VIL
High-Level Output Voltage
Iout = -400 µA
VOH
(VD+)-0.3
-
-
V
Low Level Output Voltage
Iout = 400 µA
VOL
-
-
0.3
V
Input Leakage Current
Iin
-
1
10
µA
3-State Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
9
-
pF
DS59F4
DS59F5
5
CS5505/6/7/8
CS5505/6/7/8
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Master Clock Frequency:
Internal Oscillator:
-A,B
-S
External Clock:
Symbol
Min
Typ
Max
Units
XIN
or
fclk
30.0
30.0
30
32.768
32.768
-
53.0
34.0
163
kHz
kHz
kHz
40
-
60
%
Master Clock Duty Cycle
Rise Times:
Any Digital Input
Any Digital Output
(Note 10)
trise
-
50
1.0
-
µs
ns
Fall Times:
Any Digital Input
Any Digital Output
(Note 10)
tfall
-
20
1.0
-
µs
ns
(Note 11)
tres
-
10
-
ms
(Note 12)
tosu
-
500
-
ms
(Note 13)
twup
-
1800/fclk
-
s
(Note 14)
tccw
100
-
-
ns
CONV and CAL High to Start of Calibration
tscl
-
-
2/fclk+200
ns
Start of Calibration to End of Calibration
tcal
-
3246/fclk
-
s
Start-Up
Power-On Reset Period
Oscillator Start-up Time
XTAL=32.768 kHz
Wake-up Period
Calibration
CONV Pulse Width (CAL = 1)
Conversion
Set Up Time
A0, A1 to CONV High
tsac
50
-
-
ns
Hold Time
A0, A1 after CONV High
thca
100
-
-
ns
CONV Pulse Width
tcpw
100
-
-
ns
CONV High to Start of Conversion
tscn
-
-
2/fclk+200
ns
Set Up Time
BP/UP stable prior to DRDY falling
tbus
82/fclk
-
-
s
BP/UP stable after DRDY falls
tbuh
0
-
-
ns
tcon
-
1624/fclk
-
s
Hold Time
Start of Conversion to End of Conversion
(Note 15)
Notes: 10. Specified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out
of a SLEEP state.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
13. The wake-up period begins once the oscillator starts;
or when using an external fclk, after the power-on reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/fclk if CONV remains high continuously.
6
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX
VA+ = 5V ± 10%;
VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Master Clock Frequency:
Internal Oscillator:
-A,B
-S
External Clock:
Symbol
Min
Typ
Max
Units
XIN
or
fclk
30.0
30.0
30
32.768
32.768
-
53.0
34.0
163
kHz
kHz
kHz
40
-
60
%
Master Clock Duty Cycle
Rise Times:
Any Digital Input
Any Digital Output
(Note 10)
trise
-
50
1.0
-
µs
ns
Fall Times:
Any Digital Input
Any Digital Output
(Note 10)
tfall
-
20
1.0
-
µs
ns
(Note 11)
tres
-
10
-
ms
(Note 12)
tosu
-
500
-
ms
(Note 13)
twup
-
1800/fclk
-
s
(Note 14)
tccw
100
-
-
ns
CONV and CAL High to Start of Calibration
tscl
-
-
2/fclk+200
ns
Start of Calibration to End of Calibration
tcal
-
3246/fclk
-
s
Start-Up
Power-On Reset Period
Oscillator Start-up Time
XTAL=32.768 kHz
Wake-up Period
Calibration
CONV Pulse Width (CAL = 1)
Conversion
Set Up Time
A0, A1 to CONV High
tsac
50
-
-
ns
Hold Time
A0, A1 after CONV High
thca
100
-
-
ns
CONV Pulse Width
tcpw
100
-
-
ns
CONV High to Start of Conversion
tscn
-
-
2/fclk+200
ns
Set Up Time
BP/UP stable prior to DRDY falling
tbus
82/fclk
-
-
s
BP/UP stable after DRDY falls
tbuh
0
-
-
ns
tcon
-
1624/fclk
-
s
Hold Time
Start of Conversion to End of Conversion
DS59F4
DS59F5
(Note 15)
7
CS5505/6/7/8
CS5505/6/7/8
XIN
XIN/2
CAL
t ccw
CONV
t scl
STATE
t cal
Standby
Calibration
Standby
Figure 1. Calibration Timing (Not to Scale)
XIN
XIN/2
A0, A1
t hca
t sac
CONV
t cpw
DRDY
BP/UP
t scn
STATE
Standby
t con
t bus
Conversion
t buh
Standby
Figure 2. Conversion Timing (Not to Scale)
8
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol
Min
Typ
Max
Units
CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low)
tcsd1
tdfd
-
2/fclk
2/fclk
3/fclk
ns
ns
SDATA Delay Time:
SCLK falling to next SDATA bit
tdd1
-
80
250
ns
SCLK Delay Time
SDATA MSB bit to SCLK rising
tcd1
-
1/fclk
-
ns
Serial Clock (Out)
Pulse Width High
Pulse Width Low
tph1
tpl1
-
1/fclk
1/fclk
-
ns
ns
CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z
tfd1
tfd2
-
1/fclk
2/fclk
-
ns
ns
fsclk
0
-
2.5
MHz
Pulse Width High
Pulse Width Low
tph2
tpl2
200
200
-
-
ns
ns
CS Low to data valid (Note 17)
tcsd2
-
60
200
ns
(Note 18)
SCLK falling to new SDATA bit
tdd2
-
150
310
ns
CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z
tfd3
tfd4
-
60
160
150
300
ns
ns
SSC Mode (M/SLP = VD+)
Access Time:
Output Float Delay:
SEC Mode (M/SLP = DGND)
Serial Clock (In)
Serial Clock (In)
Access Time:
Maximum Delay time:
Output Float Delay:
Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the
current data bit and then go to high impedance.
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 fclk + 200 ns after CS goes low.
18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
DS59F4
DS59F5
9
CS5505/6/7/8
CS5505/6/7/8
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX
VA+ = 5V ± 10%; VD+ = 3.3V ±
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol
Min
Typ
Max
Units
CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low)
tcsd1
tdfd
-
2/fclk
2/fclk
3/fclk
ns
ns
SDATA Delay Time:
SCLK falling to next SDATA bit
tdd1
-
265
400
ns
SCLK Delay Time
SDATA MSB bit to SCLK rising
tcd1
-
1/fclk
-
ns
Serial Clock (Out)
Pulse Width High
Pulse Width Low
tph1
tpl1
-
1/fclk
1/fclk
-
ns
ns
CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z
tfd1
tfd2
-
1/fclk
2/fclk
-
ns
ns
fsclk
0
-
1.25
MHz
Pulse Width High
Pulse Width Low
tph2
tpl2
200
200
-
-
ns
ns
CS Low to data valid (Note 17)
tcsd2
-
100
200
ns
(Note 18)
SCLK falling to new SDATA bit
tdd2
-
400
600
ns
CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z
tfd3
tfd4
-
70
320
150
500
ns
ns
SSC Mode (M/SLP = VD+)
Access Time:
Output Float Delay:
SEC Mode (M/SLP = DGND)
Serial Clock (In)
Serial Clock (In)
Access Time:
Maximum Delay time:
Output Float Delay:
10
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
XIN
XIN/2
CONV
tcsd1
CS
STATE
Standby
Conversion
Standby
Conversion
DRDY
tph1
SCLK(o) Hi-Z
Hi-Z
tdd1
tcd1
SDATA(o) Hi-Z
MSB
STATE (CONV held high)
Conversion1
tpl1
tfd2
MSB-1
LSB+1
Hi-Z
LSB
Conversion2
Figure 3. Timing Relationships; SSC Mode (Not to Scale)
DRDY
CS
SDATA(o) Hi-Z
t csd2
t fd3
MSB
MSB-1
MSB-2
MSB-1
LSB+2
t dd2
SCLK(i)
DRDY
CS
t csd2
SDATA(o) Hi-Z
MSB
t dd2
LSB+1
LSB
t fd4
t ph2
SCLK(i)
t pl2
Figure 4. Timing Relationships; SEC Mode (Not to Scale)
DS59F4
DS59F5
11
CS5505/6/7/8
CS5505/6/7/8
RECOMMENDED OPERATING CONDITIONS (DGND = 0V)
(Note 19)
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supplies: Positive Digital
(VA+)-(VA-)
Positive Analog
Negative Analog
VD+
Vdiff
VA+
VA-
3.15
4.5
4.5
0
5.0
10
5.0
-5.0
5.5
11
11
-5.5
V
V
V
V
1.0
2.5
3.6
V
0
-((VREF+)-(VREF-))
-
(VREF+)-(VREF-)
+((VREF+)-(VREF-))
V
V
Analog Reference Voltage (Note 20) (VREF+)-(VREF-)
Analog Input Voltage:
(Note 21)
Unipolar
Bipolar
VAIN
VAIN
Notes: 19. All voltages with respect to ground.
20. The CS5505/6/7/8 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
21. The CS5505/6/7/8 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar
mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds
((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative than 0 Volts.
In bipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds
((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative in magnitude than
-((VREF+)-(VREF-)).
ABSOLUTE MAXIMUM RATINGS*
Parameter
DC Power Supplies:
Digital Ground
Positive Digital
Positive Analog
Negative Analog
(VA+)-(VA-)
(VA+)-(VD+)
Input Current, Any Pin Except Supplies
Analog Input Voltage
Ambient Operating Temperature
Min
Typ
Max
Units
DGND
VD+
VA+
VAVdiff1
Vdiff2
-0.3
-0.3
-0.3
+0.3
-0.3
-0.3
-
(VD+)-0.3
6.0 or VA+
12.0
-6.0
12.0
12.0
V
V
V
V
V
V
Iin
-
-
±10
mA
VINA
(VA-)-0.3
-
(VA+)+0.3
V
VIND
-0.3
-
(VD+)+0.3
V
TA
-55
-
125
°C
°C
No pin should go more positive than (VA+)+0.3V.
VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V.
Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.
Storage Temperature
Notes: 22.
23.
24.
25.
(Notes 24, 25)
AIN and VREF pins
Digital Input Voltage
(Note 22)
(Note 23)
Symbol
T stg
-65
-
150
* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
12
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
GENERAL DESCRIPTION
The CS5505/6/7/8 are very low power monolith ic CM OS A/D co nverters designed
specifically for measurement of dc signals. The
CS5505/7 are 16-bit converters (a four channel
and a single channel version). The CS5506/8 are
20-bit converters (a four channel and a single
channel version). Each of the devices includes a
delta-sigma charge-balance converter, a voltage
reference, a calibration microcontroller with
SRAM, a digital filter and a serial interface. The
CS5505 and CS5506 include a four channel
pseudo-differential (all four channels have the
same reference measurement node) multiplexer.
The CS5505/6/7/8 include an on-chip reference
but can also utilize an off-chip reference for precision applications. The CS5505/6/7/8 can be
used to measure either unipolar or bipolar signals. The devices use self-calibration to insure
excellent offset and gain accuracy.
The CS5505/6/7/8 are optimized to operate from
a 32.768 kHz crystal but can be driven by an
external clock whose frequency is between
30 kHz and 163 kHz. When the digital filter is
operated with a 32.768 kHz clock, the filter has
zeros precisely at 50 and 60 Hz line frequencies
and multiples thereof.
The CS5505/6/7/8 use a "start convert" command to latch the input channel selection and to
start a convolution cycle on the digital filter.
Once the filter cycle is completed, the output
port is updated. When operated with a
32.768 kHz clock the ADC converts and updates
its output port at 20 samples/sec. The throughput
rate per channel is the output update rate divided
by th e number of channels being multiplexed. The output port includes a serial
interface with two modes of operation.
The CS5505/6/7/8 can operate from dual polarity power supplies (+5 and -5), from a single +5
volt supply, or with +10 volts on the analog and
DS59F4
DS59F5
+5 on the digital. They can also operate with
dual polarity (+5 and -5), or from a single +5
volt supply on the analog and + 3.3 on the digital.
THEORY OF OPERATION FOR THE
CS5505/6/7/8
The front page of this data sheet illustrates the
block diagram of the CS5505/6.
Basic Converter Operation
The CS5505/6/7/8 A/D converters have four operating states. These are start-up, calibration,
conversion and sleep. When power is first applied, the device enters the start-up state. The
first step is a power-on reset delay of about
10 ms which resets all of the logic in the device.
To proceed with start-up, the oscillator must
then begin oscillating. After the power-on reset
the device enters the wake-up period for 1800
clock cycles after clock is present. This allows
the delta-sigma modulator and other circuitry
(which are operating with very low currents) to
reach a stable bias condition prior to entering
into either the calibration or conversion states.
During the 1800 cycle wake-up period, the device can accept an input command. Execution of
this command will not occur until the complete
wake-up period elapses. If no command is given,
the device enters the standby mode.
Calibration
After the initial application of power, the
CS5505/6/7/8 must enter the calibration state
prior to performing accurate conversions. During
calibration, the chip executes a two-step process.
The device first performs an offset calibration
and then follows this with a gain calibration.
The two calibration steps determine the zero reference point and the full scale reference point of
the converter’s transfer function. From these
points it calibrates the zero point and a gain
13
CS5505/6/7/8
CS5505/6/7/8
slope to be used to properly scale the output
digital codes when doing conversions.
The calibration state is entered whenever the
CAL and CONV pins are high at the same time.
The state of the CAL and CONV pins at poweron and when coming out of sleep are recognized
as commands, but will not be executed until the
end of the 1800 clock cycle wake-up period.
Note that any time CONV transitions from low
to high, the multiplexer inputs A0 and A1 are
latched internal to the CS5505 and CS5506 devices. These latched inputs select the analog
input channel which will be used once conversion commences.
If CAL and CONV become active (high) during
the 1800 clock cycle wake-up time, the converter will wait until the wake-up period elapses
before executing the calibration. If the wake-up
time has elapsed, the converter will be in the
standby mode waiting for instruction and will
enter the calibration cycle immediately. The calibration lasts for 3246 clock cycles. Calibration
coefficients are then retained in the SRAM
(static RAM) for use during conversion.
At the end of the calibration cycle, the on-chip
microcontroller checks the logic state of the
CONV signal. If the CONV input is low the device will enter the standby mode where it waits
for further instruction. If the CONV signal is
high at the end of the calibration cycle, the converter will enter the conversion state and
perform a conversion on the input channel which
was selected when CONV transitioned from low
to high. The CAL signal can be returned low
any time after calibration is initiated. CONV can
also be returned low, but it should never be
taken low and then taken back high until the
calibration period has ended and the converter is
in the standby state. If CONV is taken low and
then high again with CAL high while the converter is calibrating, the device will interrupt the
current calibration cycle and start a new one. If
CAL is taken low and CONV is taken low and
14
then high during calibration, the calibration cycle will continue as the conversion command is
disregarded. The states of A0, A1 and BP/UP
are not important during calibrations.
If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONV
signal high continuously. Once the calibration is
completed, a conversion will be performed. At
the end of the conversion, DRDY will fall to indicate the first valid conversion after the
calibration has been completed.
See Understanding Converter Calibration for details on how the converter calibrates its transfer
function.
Conversion
The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONV is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cycle is completed (CAL is taken low after CONV
transitions high), the converter will begin a conversion upon completion of the calibration
period. The device will perform a conversion on
the input channel selected by the A0 and A1 inputs when CONV transitioned high. Table 1
indicates the multiplexer channel selection truth
table for A0 and A1.
A1
A0
Channel addressed
0
0
AIN1
0
1
AIN2
1
0
AIN3
1
1
AIN4
Table 1. Multiplexer Truth Table
The A0 and A1 inputs are latched internal to the
4-channel devices (CS5505/6) when CONV
rises. A0 and A1 have internal pull-down circuits which default the multiplexer to channel
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
AIN1. The BP/UP pin is not a latched input. The
BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is
offset by 8000H in the 16-bit CS5505/7 or
80000H in 20-bit CS5506/8 (see Understanding
Converter Calibration). BP/UP can be changed
after a conversion is started as long as it is stable
for 82 clock cycles of the conversion period
prior to DRDY falling. If one wishes to intermix
measurement of bipolar and unipolar signals on
various input channels, it is best to switch the
BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again. If
the converter is beginning a conversion starting
from the standby state, BP/UP can be changed at
the same time as A0 and A1.
The digital filter in the CS5505/6/7/8 has a Finite Impulse Response and is designed to settle
to full accuracy in one conversion time. Therefore, the multiplexer can be changed at the
conversion rate.
If CONV is left high, the CS5505/6/7/8 will perform continuous conversions on one channel.
The conversion time will be 1622 clock cycles.
If conversion is initiated from the standby state,
there may be up to two XIN clock cycles of uncertainty as to when conversion actually begins.
This is because the internal logic operates at one
half the external clock rate and the exact phase
of the internal clock may be 180° out of phase
relative to the XIN clock. When a new conversion is initiated from the standby state, it will
take up to two XIN clock cycles to begin. Actual
conversion will use 1624 clock cycles before
DRDY goes low to indicate that the serial port
has been updated. See the Serial Interface Logic
section of the data sheet for information on reading data from the serial port.
terminated and a new conversion will be initiated.
Voltage Reference
The CS5505/6/7/8 uses a differential voltage reference input. The positive input is VREF+ and
the negative input is VREF-. The voltage between VREF+ and VREF- can range from 1 volt
minimum to 3.6 volts maximum. The gain slope
will track changes in the reference without recalibration, accommodating ratiometric
applications.
The CS5505/6/7/8 include an on-chip voltage
reference which outputs 2.5 volts on the VREFOUT pin. This voltage is referenced to the
VA+ pin and will track changes relative to VA+.
The VREFOUT output requires a 0.1 µF capacitor connected between VREFOUT and VA+ for
stability. When using the internal reference, the
VREFOUT signal should be connected to the
VREF- input and the VREF+ pin should be connected to the VA+ supply. The internal voltage
reference is capable of sourcing 3 µA maximum
and sinking 50 µA maximum. If a more precise
reference voltage is required, an external voltage
reference should be used. If an external voltage
reference is used, the VREFOUT pin of the internal reference should be connected directly to
VA-. It cannot be left open unless the 0.1 µF capacitor is in place for stability.
CS5505/6/7/8
LT1019,
REF43
or
LM368
-VA
In the event the A/D conversion command
(CONV going positive) is issued during the conversion state, the current conversion will be
DS59F4
DS59F5
VA+
+VA
2.5V
VREF+
VREFVREFOUT
VA-
Figure 5. External Reference Connections
15
CS5505/6/7/8
CS5505/6/7/8
ages for the A/D. The differential input voltage
can also have any common mode value as long
as the maximum signal magnitude stays within
the supply voltages.
CS5505/6/7/8
+VA
VA+
VREF+
0.1 µF
VREFVREFOUT
-VA
VA-
Figure 6. Internal Reference Connections
External reference voltages can range from 1.0
volt minimum to 3.6 volts maximum. The common mode voltage range of the external
reference can allow the reference to lie at any
voltage between the VA+ and VA- supply rails.
Figures 5 and 6 illustrate how the CS5505/6/7/8
converters are connected for external and for internal voltage reference use, respectively.
Analog Input Range
The analog input range is set by the magnitude
of the voltage between the VREF+ and VREFpins. In unipolar mode the input range will equal
the magnitude of the voltage reference. In bipolar mode the input voltage range will equate to
plus and minus the magnitude of the voltage reference. While the voltage reference can be as
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply volt-
The A/D converter is intended to measure dc or
low frequency inputs. It is designed to yield accurate conversions even with noise exceeding
the input voltage range as long as the spectral
components of this noise will be filtered out by
the digital filter. For example, with a 3.0 volt
reference in unipolar mode, the converter will
accurately convert an input dc signal up to
3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz
component which is 0.5 volts above the maximum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise amplitude stays within the supply voltages.
The CS5505/6/7/8 converters output data in binary format when converting unipolar signals
and in offset binary format when converting bipolar signals. Table 2 outlines the output coding
for the 16-bit CS5505/7 and the 20-bit CS5506/8
in both unipolar and bipolar measurement
modes.
CS5505 and CS5507 (16 Bit)
CS5506 and CS5508 (20 Bit)
Unipolar Input
Voltage
Output
Codes
Bipolar Input
Voltage
Unipolar Input
Voltage
Output
Codes
Bipolar Input
Voltage
>(VREF - 1.5 LSB)
FFFF
>(VREF - 1.5 LSB)
>(VREF - 1.5 LSB)
FFFFF
>(VREF - 1.5 LSB)
VREF - 1.5 LSB
FFFF
FFFE
VREF - 1.5 LSB
VREF - 1.5 LSB
FFFFF
FFFFE
VREF - 1.5 LSB
VREF/2 - 0.5 LSB
8000
7FFF
-0.5 LSB
VREF/2 - 0.5 LSB
80000
7FFFF
-0.5 LSB
+0.5 LSB
0001
0000
-VREF + 0.5 LSB
+0.5 LSB
00001
00000
-VREF + 0.5 LSB
<(+0.5 LSB)
0000
<(-VREF + 0.5 LSB)
<(+0.5 LSB)
00000
<(-VREF + 0.5 LSB)
Note: VREF = (VREF+) - (VREF-); Table excludes common mode voltage on the signal and reference inputs.
Table 2. Output Coding
16
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
Understanding Converter Calibration
Calibration can be performed at any time. A
calibration sequence will minimize offset errors
and set the gain slope scale factor. The deltasigma modulator in the converter is a differential
modulator. To calibrate out offset error, the
converter internally connects the modulator differential inputs to an internal VREF- voltage and
measures the 1’s density output from the modulator. It stores the digital code representation for
this 1’s density in SRAM and remembers this
code as being the zero scale point for the A/D
conversion. The converter then connects the
negative modulator differential input to the
VREF- input and the positive modulator differential input to the VREF+ voltage. The 1’s
density output from the modulator is then reco rded. The converter uses the digital
representation of this 1’s density along with the
digital code for the zero scale point and calculates a gain scale factor. The gain scale factor is
stored in SRAM and used for calculating the
proper output codes during conversions.
The states of A0, A1 and BP/UP are ignored
during calibration but should remain stable
throughout the calibration period to minimize
noise.
When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital
output code. The only difference is that in bipolar mode the on-chip microcontroller offsets the
computed output word by a code value of
8000H (16-bit) or 80000H (20-bit) and multiplies the LSB size by two. This means that the
bipolar measurement range is not calibrated from
full scale positive to full scale negative. Instead
it is calibrated from the bipolar zero scale point
to full scale positive. The slope factor is then
extended below bipolar zero to accommodate the
negative input signals. The converter can be
used to convert both unipolar and bipolar signals
by changing the BP/UP pin. Recalibration is not
required when switching between unipolar and
bipolar modes.
Converter Performance
The CS5505/6/7/8 A/D converters have excellent
linearity performance. Calibration minimizes the
errors in offset and gain. The CS5505/7 devices
have no missing code performance to 16-bits.
The CS5506/8 devices have no missing code
performance to 20-bits. Figure 7 illustrates the
DNL of the 16-bit CS5505. The converters
achieve Common Mode Rejection (CMR) at dc
of 105 dB typical, and CMR at 50 and 60 Hz of
120 dB typical.
The CS5505/6/7/8 can experience some drift as
temperature changes. The CS5505/6/7/8 use
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.
+1
DNL (LSB)
+1/2
0
-1/2
-1
0
32,768
65,535
Codes
Figure 7. CS5505 Differential Nonlinearity plot.
DS59F4
DS59F5
17
CS5505/6/7/8
CS5505/6/7/8
Analog Input Impedance Considerations
The analog input of the CS5505/6/7/8 can be
modeled as illustrated in Figure 8 (the model ignores the multiplexer switch resistance).
Capacitors (15 pF each) are used to dynamically
sample each of the inputs (AIN+ and AIN-).
Every half XIN cycle the switch alternately connects the capacitor to the output of the buffer
and then directly to the AIN pin. Whenever the
sample capacitor is switched from the output of
the buffer to the AIN pin, a small packet of
charge (a dynamic demand of current) is required from the input source to settle the voltage
of the sample capacitor to its final value. The
voltage on the output of the buffer may differ up
to 100 mV from the actual input voltage due to
the offset voltage of the buffer. Timing allows
one half of a XIN clock cycle for the voltage on
the sample capacitor to settle to its final value.
The equation which defines the settling time is:
Vmax occurs the instant the sample capacitor is
switched from the buffer output to the AIN pin.
Prior to switching, AIN has an error estimated as
being less than or equal to Ve. Vmax is equal to
the prior error (Ve) plus the additional error
from the buffer offset. The estimate for Vmax is:
Vmax = Ve + 100mV
15pF
(15pF + CEXT )
Where CEXT is the combination of any external
or stray capacitance.
From the settling time equation, an equation for
the maximum acceptable source resistance is derived.
Rsmax =
−1
Ve
2XIN (15pF + CEXT ) ln
Ve + 15pF(100mv)
(15pF + CEXT )
−t
Ve = Vmax e ⁄RC
Where Ve is the final settled value, Vmax is the
maximum error voltage value of the input signal,
R is the value of the input source resistance, C is
the 15 pF sample capacitor plus the value of any
stray or additional capacitance at the input pin.
The value of t is equal to 1/(2XIN).
CS5505/6/7/8
AIN+
Vos < 100 mV +
AIN-
15 pF
Internal
Bias
Voltage
15 pF
Vos < 100 mV +
-
This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable.
For a maximum error voltage (Ve) of 10 µV in
the CS5505 (1/4LSB at 16-bits) and 600 nV in
the CS5506 (1/4LSB at 20-bits), the above equation indicates that when operating from a
32.768 kHz XIN, source resistances up to
110 kΩ in the CS5505 or 84 kΩ in the CS5506
are acceptable in the absence of external capacitance (CEXT = 0). If higher input source
resistances are desired the master clock rate can
be reduced to yield a longer settling time.
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input impedance applies to the voltage reference inputs as
well.
Figure 8. Analog Input Model
18
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
Digital Filter Characteristics
The digital filter in the CS5505/6/7/8 is the combination of a comb filter and a low pass filter.
The comb filter has zeros in its transfer function
which are optimally placed to reject line interference frequencies (50 and 60 Hz and their
multiples) when the CS5505/6/7/8 is clocked at
32.768 kHz. Figures 9, 10 and 11 illustrate the
magnitude and phase characteristics of the filter.
0
X1 = 32.768kHz
X2 = 163.00kHz
-20
Figure 9 illustrates the filter attenuation from dc
to 260 Hz. At exactly 50, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Table 3 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation
of these interference frequencies even if the fundamental line frequency should vary ±1% from
its specified frequency. The -3 dB corner frequency of the filter when operating from a
32.768 kHz clock is 17 Hz. Figure 11 illustrates
that the phase characteristics of the filter are precisely linear phase.
Attenuation (dB)
-40
Frequency
(Hz)
-60
-80
50
60
100
120
150
180
200
240
-100
-120
-140
XIN = 32.768 kHz
-160
X1
0
X2
0
40
80
120
160
200
240
198.97 397.95 596.92 795.10 993.87 1193.85
Frequency (Hz)
Figure 9. Filter Magnitude Plot to 260 Hz
Frequency Minimum
(Hz)
Attenuation
(dB)
55.5
50±1%
58.4
60±1%
62.2
100±1%
68.4
120±1%
74.9
150±1%
87.9
180±1%
94.0
200±1%
104.4
240±1%
Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)
180
0
135
Flatness
Frequency dB
-0.010
1
-40
-60
-80
-100
2
-0.041
3
-0.093
4
-0.166
5
-0.259
6
-0.374
7
-0.510
8
-0.667
9
-0.846
10
-1.047
17
-3.093
90
Phase (Degrees)
-20
Attenuation (dB)
Notch
Depth
(dB)
125.6
126.7
145.7
136.0
118.4
132.9
102.5
108.4
45
0
-45
-90
XIN = 32.768 kHz
XIN = 32.768 kHz
-120
-135
-140
-180
0
5
10
15
20
25
30
35
40
Frequency (Hz)
Figure 10. Filter Magnitude Plot to 50 Hz
DS59F4
DS59F5
45
50
0
5
10
15
20
25
30
35
40
45
50
Frequency (Hz)
Figure 11. Filter Phase Plot to 50 Hz
19
CS5505/6/7/8
CS5505/6/7/8
If the CS5505/6/7/8 is operated at a clock rate
other than 32.768 kHz, the filter characteristics,
including the comb filter zeros, will scale with
the operating clock frequency. Therefore, optimum rejection of line frequency interference will
occur with the CS5505/6/7/8 running at
32.768 kHz. The CS5505/6/7/8 can be used with
external clock rates from 30 kHz to 163 kHz.
ponents should be removed by means of lowpass filtering prior to the A/D input to prevent
aliasing. Spectral components greater than one
half the output word rate on the VREF inputs
(VREF+ and VREF-) may also be aliased. Filtering of the reference voltage to remove these
spectral components from the reference voltage
is desirable.
Anti-Alias Considerations for Spectral
Measurement Applications
Crystal Oscillator
The CS5505/6/7/8 is designed to be operated using a 32.768 kHz "tuning fork" type crystal. One
end of the crystal should be connected to the
XIN input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance. Figure 12 illustrates
the gate oscillator, and a simplified version of
the control logic used on the chip.
Input frequencies greater than one half the output word rate (CONV = 1) may be aliased by
the converter. To prevent this, input signals
should be limited in frequency to no greater than
one half the output word rate of the converter
(when CONV =1). Frequencies close to the
modulator sample rate (XIN/2) and multiples
thereof may also be aliased. If the signal source
includes spectral components above one half the
output word rate (when CONV = 1) these com-
Over the industrial temperature range (-40 to
+85 °C) the on-chip gate oscillator will oscillate
CS5505/6
Channel A0 A1
D Q
A0
CLK
Input
Mux
Decoder
D Q
A1
1
0
0
2
0
1
3
1
0
4
1
1
CLK
CONV
S Q
R
D Q
CLK
10 MΩ
15 pF
Start
Calibration
R
Q
22.5 pF
Start
Conversion
CLK
R
S Q
CAL
D Q
T
Modulator
Sample
Clock
gm ~
~ 19 umho
XOUT
XIN
XTL=32.768 kHz
Figure 12. Gate Oscillator and Control Logic
20
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
with other crystals in the range of 30 kHz to
53 kHz. Over the military temperature range (55 to +125 °C) the on-chip gate oscillator is
designed to work only with a 32.768 kHz crystal. The chip will operate with external clock
frequencies from 30 kHz to 163 kHz.over all
temperature ranges. The 32.768 kHz crystal is
normally specified as a time-keeping crystal with
tight specifications for both initial frequency and
for drift over temperature. To maintain excellent
frequency stability, these crystals are specified
only over limited operating temperature ranges
(i.e. -10 to +60 °C) by the manufacturers. Applications of these crystals with the CS5505/6/7/8
do not require tight initial tolerance or low
tempco drift. Therefore, a lower cost crystal with
looser initial tolerance and tempco will generally
be adequate for use with the CS5505/6/7/8 converters. Also check with the manufacturer about
wide temperature range application of their
standard crystals. Generally, even those crystals
specified for limited temperature range will operate over much larger ranges if frequency
stability over temperature is not a requirement.
The frequency stability can be as bad as ±3000
ppm over the operating temperature range and
still be typically better than the line frequency
(50 or 60 Hz) stability over cycle to cycle during
the course of a day. There are crystals available
for operation over the military temperature range
(-55 to +125 °C). See the Appendix for suppliers
of 32.768 kHz crystals.
Serial Interface Logic
The digital filter in the CS5505/6/7/8 takes 1624
clock cycles to compute an output word once a
conversion begins. At the end of the conversion
cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update
DRDY will go high. When DRDY goes high
just prior to a port update it checks to see if the
port is either empty or unselected (CS = 1). If
the port is empty or unselected, the digital filter
will update the port with a new output word.
DS59F4
DS59F5
When new data is put into the port DRDY will
go low.
Data can be read from the serial port in either of
two modes. The M/SLP pin determines which
serial mode is selected. Serial port mode selection is as follows:
SSC (Synchronous Self-Clocking) mode;
M/SLP = VD+, or SEC (Synchronous External
Clocking) mode; M/SLP = DGND. Timing diagrams which illustrate the SSC and SEC timing
are in the tables section of this data sheet.
Synchronous Self-Clocking Mode
The serial port operates in the SSC mode when
the M/SLP pin is connected to the VD+ pin on
the part. In SSC mode the CS5505/6/7/8 furnishes both the serial output data (SDATA) and
the serial clock (SCLK). When the serial port is
updated at the end of a conversion, DRDY falls.
If CS is low, the SDATA and SCLK pins will
come out of the high impedance state two XIN
clock cycles after DRDY falls. The MSB data
bit will be presented for two cycles of XIN
clock. The SCLK signal will rise in the middle
of the MSB data bit. When SCLK then returns
low the (MSB - 1) bit will appear. Subsequent
data bits will be output on each falling edge of
SCLK until the LSB data bit is output. After the
LSB data bit is output, the SCLK will fall at
which time both the SDATA and SCLK outputs
will return to the high impedance output state.
DRDY will return high at this time.
If CS is taken low after DRDY falls, the MSB
data bit will appear within two XIN clock cycles
after CS is taken low. CS need not be held low
for the entire data output. If CS is returned high
during a data bit the port will complete the output of that bit and then go into the Hi-Z state.
The port can be reselected any time prior to the
completion of the next conversion (DRDY falling) to allow the remaining data bits to be
output.
21
CS5505/6/7/8
CS5505/6/7/8
Synchronous External-Clocking Mode
The serial port operates in the SEC mode when
the M/SLP pin is connected to the DGND pin.
SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit present. SCLK is the input pin for the serial clock
in the SEC mode. If the MSB data bit is on the
SDATA pin, the first rising edge of SCLK enables the shifting mechanism. This allows the
falling edges of SCLK to shift subsequent data
bits out of the port. Note that if the MSB data
bit is output and the SCLK signal is high, the
first falling edge of SCLK will be ignored because the shifting mechanism has not become
activated. After the first rising edge of SCLK,
each subsequent falling edge will shift out the
serial data. Once the LSB is present, the falling
edge of SCLK will cause the SDATA output to
go to Hi-Z and DRDY to return high. The serial
port register will be updated with a new data
word upon the completion of another conversion
if the serial port has been emptied, or if the CS
is inactive (high).
CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.
Sleep Mode
The CS5505/6/7/8 devices offer two methods of
putting the device into a SLEEP condition to
conserve power. Calibration words will be retained in SRAM during either sleep condition.
The M/SLP pin can be put into the SLEEP
threshold to lower the operating power used by
the device to about 1% of nominal. Alternately,
the clock into the XIN pin can be stopped. This
will lower the power consumed by the converter
to about 30% of nominal. In both cases, the
22
converter must go through a wake-up sequence
prior to conversions being initiated. This wakeup sequence includes the 10 msec. (typ.)
power-on-reset delay, the start-up of the oscillator (unless an external clock is used), and the
1800 clock cycle wake-up delay after the clock
begins. When coming out of the sleep condition, the converter will latch the A0 and A1
inputs.
Figure 13 illustrates how to use a gate and resistors to bias the M/SLP pin into the SLEEP
threshold region when using the converter in the
SSC mode. To use the SEC mode return resistor
R1 to DGND instead of the supply. When in
the SEC mode configuration the CS5505/6/7/8
will enter the SLEEP threshold when the logic
control input is a logic 1 (VD+). Note that large
resistors can be used to conserve power while in
sleep. The input leakage of the pin is typically
less than 1 µA even at 125 °C, although the
worst case specification tables indicate a leakage
VD+ *
1%
Control
Input
’1’ = SSC Mode
’0’ = SLEEP
R1**
CS5505/6/7/8
R2
M/SLP
499k
1%
0.01µF
* Tie R to DGND for SEC mode; control input
1
logic inverts.
** R = 499k, V + = 5V; R = 590k, V + = 3.3V
1
D
1
D
Figure 13. Sleep Threshold Control
of 10 µA maximum.
Power Supplies and Grounding
The analog and digital supply pins to the
CS5505/6/7/8 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. Note that there is no
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
analog ground pin. No analog ground pin is required because the inputs for measurement and
for the voltage reference are differential and require no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CS5505/6/7/8 requires that the supply voltage on the VA+ pin always be more positive
than the voltage on any other pin of the device.
If this requirement is not met, the device can
latch-up or be damaged. In all circumstances the
VA+ voltage must remain more positive than the
VD+ or DGND pins; VD+ must remain more
positive than the DGND pin.
The following power supply options are possible:
VA+ = +5V to +10V, VA- = 0V,
VA+ = +5V,
VA- = -5V,
VA+ = +5V,
VA- = 0V to -5V,
VD+ = +5V
VD+ = +5V
VD+ = +3.3V
The CS5505/6/7/8 cannot be operated with a
3.3V digital supply if VA+ is greater than
+5.5V.
10Ω
+5V
Analog
Supply
0.1 µF
0.1 µF
17
20
VA+
VD+
5
XIN
Calibration
Control
Bipolar/
Unipolar
Input Select
4
8
6
CAL
XOUT
BP/UP
M/SLP
32.768 kHz
7
CS5505/6
9
10
12
13
Analog*
Signal
Sources
Signal
Ground
11
*Unused analog inputs
should be tied to AIN14
+
Voltage
Reference
-
15
16
AIN1+
AIN2+
AIN3+
AIN4+
SCLK
SDATA
AIN-
DRDY
CS
VREF+
A0
A1
VREF-
CONV
VREFOUT
DGND
VA18
Optional
Clock
Source
21
22
23
2
1
24
Sleep Mode
Control
and
Output Mode
Select
Serial
Data
Interface
Control
Logic
3
19
Unused Logic
inputs must be
connected to
VD+ or DGND.
Note: To use the internal 2.5 volt reference see Figure 6.
Figure 14. CS5505/6 System Connection Diagram Using External Reference, Single Supply
DS59F4
DS59F5
23
CS5505/6/7/8
CS5505/6/7/8
Figure 14 illustrates the System Connection Diagram for the CS5505/6 using a single +5V
supply. Note that all supply pins are bypassed
with 0.1 µF capacitors and that the VD+ digital
supply is derived from the VA+ supply.
Figure 16 illustrates the CS5505/6 using dual
supplies of +10V analog and +5V digital.
When using separate supplies for VA+ and
VD+, VA+ must be established first. VD+
should never become more positive than VA+
under any operating condition. Remember to investigate transient power-up conditions, when
one power supply may have a faster rise time.
Figure 15 illustrates the CS5505/6 using dual
supplies of +5 and -5V.
10Ω
+5V
Analog
Supply
0.1 µF
0.1 µF
17
20
VA+
VD+
5
XIN
Calibration
Control
Bipolar/
Unipolar
Input Select
4
8
6
CAL
XOUT
BP/UP
M/SLP
32.768 kHz
7
CS5505/6
9
10
12
13
Analog*
Signal
Sources
Signal
Ground
11
*Unused analog inputs
should be tied to AIN14
+
Voltage
Reference
15
-
16
-5V
Analog
Supply
0.1 µF
AIN1+
AIN2+
AIN3+
AIN4+
SCLK
SDATA
AIN-
DRDY
CS
VREF+
A0
A1
VREF-
CONV
VREFOUT
DGND
VA18
Optional
Clock
Source
21
22
23
2
1
24
Sleep Mode
Control
and
Output Mode
Select
Serial
Data
Interface
Control
Logic
3
19
Unused Logic
inputs must be
connected to
VD+ or DGND.
Note: To use the internal 2.5 volt reference see Figure 6.
Figure 15. CS5505/6 System Connection Diagram Using External Reference, Dual Supplies
24
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
+10V
Analog
Supply
0.1 µF
17 (2)
VA+
20
VD+
5
XIN
Calibration
Control
Bipolar/
Unipolar
Input Select
4
8
6
CAL
XOUT
BP/UP
M/SLP
9
10
12
13
11
*Unused analog inputs
should be tied to AIN14
+
Voltage
(1)
Reference
15
16
Signal
Ground
AIN1+
AIN2+
AIN3+
AIN4+
SCLK
SDATA
AIN-
DRDY
CS
VREF+
A0
A1
VREF-
CONV
VREFOUT
DGND
VA-
Optional
Clock
Source
32.768 kHz
7
CS5505/6
Analog*
Signal
Sources
+5V
Analog
Supply
0.1 µF
21
22
Sleep Mode
Control
and
Output Mode
Select
Serial
Data
Interface
23
2
1
24
Control
Logic
3
19
18
Unused Logic
inputs must be
connected to
VD+ or DGND.
Note: (1) To use the internal 2.5 volt reference see Figure 6.
(2) VD+ must never exceed VA+. Examine power-up conditions.
Figure 16. CS5505/6 System Connection Diagram Using External Reference,
Dual Supply, +10V Analog, +5V Digital
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
DS59F4
DS59F5
25
CS5505/6/7/8
CS5505/6/7/8
PIN CONNECTIONS*
CS5505/6
MULTIPLEXER SELECTION INPUT
A0
1
24
A1
MULTIPLEXER SELECTION INPUT
CHIP SELECT
CS
2
23
DRDY
DATA READY
CONVERT
CONV
3
22
SDATA
SERIAL DATA OUTPUT
CALIBRATE
CAL
4
21
SCLK
SERIAL CLOCK INPUT/OUTPUT
CRYSTAL IN
XIN
5
20
VD+
POSITIVE DIGITAL POWER
CRYSTAL OUT
XOUT
6
19
DGND
DIGITAL GROUND
SERIAL MODE/ SLEEP
M/SLP
7
18
VA-
NEGATIVE ANALOG POWER
BIPOLAR/UNIPOLAR
BP/UP
8
17
VA+
POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT
AIN1+
9
16
VREFOUT VOLTAGE REFERENCE OUTPUT
DIFFERENTIAL ANALOG INPUT
AIN2+
10
15
VREF-
VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG RETURN
AIN-
11
14
VREF+
VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT
AIN3+
12
13
AIN4+
DIFFERENTIAL ANALOG INPUT
CS5507/8
CS
1
20
DRDY
DATA READY
CONV
2
19
SDATA
SERIAL DATA OUTPUT
CALIBRATE
CAL
3
18
SCLK
SERIAL CLOCK INPUT/OUTPUT
CRYSTAL IN
XIN
4
17
VD+
POSITIVE DIGITAL POWER
CRYSTAL OUT
XOUT
5
16
DGND
DIGITAL GROUND
SERIAL MODE/ SLEEP
M/SLP
6
15
VA-
NEGATIVE ANALOG POWER
BIPOLAR/UNIPOLAR
BP/UP
7
14
VA+
POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT
AIN+
8
13
VREFOUT VOLTAGE REFERENCE OUTPUT
NO CONNECTION
NC
9
12
VREF-
VOLTAGE REFERENCE INPUT
10
11
VREF+
VOLTAGE REFERENCE INPUT
CHIP SELECT
CONVERT
DIFFERENTIAL ANALOG INPUT
AIN-
*Pinout applies to both DIP and SOIC
26
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
PIN DESCRIPTIONS
Pin numbers for four channel devices are in parentheses.
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6).
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output I/O
M/SLP - Serial Interface Mode Select/ Sleep, Pin 6 (7).
Dual function pin which selects the operating mode of the serial port and provides a very low
power sleep function. When M/SLP is tied to the VD+ pin the serial port will operate in the
Synchronous Self-Clocking (SSC) mode. When M/SLP is tied to the DGND pin the serial port
will operate in the Synchronous External Clocking (SEC) mode. When the M/SLP pin is tied
half way between VD+ and DGND the chip will enter into a very low powered sleep mode in
which its calibration data will be maintained.
CS - Chip Select, Pin 1 (2).
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 20 (23)
Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 19 (22).
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK and in a format determined by the M/SLP pin. Data is output MSB first
and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high
impedance state when not transmitting data.
SCLK - Serial Clock Input/Output, Pin 18 (21).
A clock signal on this pin determines the output rate of the data from the SDATA pin. The
M/SLP pin determines whether SCLK is an input or and output. When used as an input, it must
not be allowed to float.
DS59F4
DS59F5
27
CS5505/6/7/8
CS5505/6/7/8
Control Input Pins
CAL - Calibrate, Pin 3 (4).
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.
CONV - Convert, Pin 2 (3).
The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. CONV
latches the multiplexer selection when it transitions from low to high on the multiple channel
devices. If CONV is held high (CAL low) the converter will do continuous conversions.
A0, A1 - Multiplexer Selection Inputs, Pins (1, 24).
A0 and A1 select the input channel for conversion on the multi-channel input devices. A0 and
A1 are latched when CONV transitions from low to high. These two inputs have pull-down
resistors internal to the chip.
BP/UP - Bipolar/Unipolar, Pin 7 (8).
The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.
Measurement and Reference Inputs
AIN+, AIN-, (AIN1+, AIN2+, AIN3+, AIN4+, AIN-) - Differential Analog Inputs, Pins 8, 10 (9,
10, 12, 13, 11).
AIN- in the CS5505/6 is a common measurement node for AIN1+, AIN2+, AIN3+ and AIN4+.
VREF+, VREF- - Differential Voltage Reference Inputs, Pins 11, 12 (14, 15).
A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.
Voltage Reference
VREFOUT - Voltage Reference Output, Pin 13 (16).
The on-chip voltage reference is output from this pin. The voltage reference has a nominal
magnitude of 2.5 volts and is referenced to the VA+ pin on the converter.
Power Supply Connections
VA+ - Positive Analog Power, Pin 14 (17).
Positive analog supply voltage. Nominally +5 volts.
VA- - Negative Analog Power, Pin 15 (18).
Negative analog supply voltage. Nominally -5 volts when using dual polarity supplies; or 0
volts (tied to system analog ground) when using single supply operation.
28
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
VD+ - Positive Digital Power, Pin 17 (20).
Positive digital supply voltage. Nominally +5 volts or 3.3 volts.
DGND - Digital Ground, Pin 16 (19).
Digital Ground.
Other
NC - No Connection, Pin 9.
Pin should be left floating.
SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Nonlinearity
The deviation of a code’s width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB].
Units are in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AINpin.) when in unipolar mode (BP/UP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs
DS59F4
DS59F5
29
CS5505/6/7/8
CS5505/6/7/8
ORDERING INFORMATION
Ordering Guide
Liearity
Model Model
# of
Number
Channels
CS5505-AP
Resolution
Error
Channels
Temperature
Linearity
Temperature
Package Type
Range (°C)
24-pin Plastic DIPError
CS5505-AS
CS5505-AP
4
CS5505-AS
4
CS5505-ASZ (lead free)
16 Bits -400.0030%
16-Bits
0.0030%
to +85
24-pin SOIC
16-Bits
0.0030%
-40 to +85
CS5506-BP
CS5506-BP
CS5506-BS
CS5506-BS
24-pin
20-BitsPlastic DIP
0.0015%
20-Bits
0.0015%
20 Bits
24-pin SOIC
16-Bits
0.0030%
16-Bits
0.0030%
20-pin Plastic DIP
16-Bits
0.0030%
16 Bits
20-pin
SOIC
20-Bits
0.0015%
20-Bits
0.0015%
20-pin
20-BitsPlastic DIP
0.0030%
-40 to +85
-40 to +85
-55 to +125
0.0030%
-40 to +85
-40 to +85
-55 to +125
20 Bits
0.0015%
4
4
CS5506-BSZ
(lead free)
CS5507-AP
1
CS5507-AS
1
CS5507-AP
CS5507-SD
1
CS5507-AS
CS5508-BP
1
CS5507-ASZ (lead free)
CS5508-BS
1
CS5508-BP
CS5508-SD
1
CS5508-BS
CS5508-BSZ (lead free)
Package
Resolution
20-pin SOIC
-40 to +85
-400.0015%
to +85
24-pin
24-pin
4
24-pin
24-pin
0.3" Plastic DIP
0.3" SOIC
0.3" Plastic DIP
0.3" SOIC
20-pin 0.3" Plastic DIP
-40 to +85 °C
20-pin 0.3" SOIC
20-pin 0.3" CerDIP
20-pin 0.3" Plastic DIP
20-pin
0.3" SOIC
1
20-pin 0.3" CerDIP
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS5505-AP
260 °C
1
No Limit
CS5505-AS
240 °C
2
365 Days
CS5505-ASZ (lead free)
260 °C
3
7 Days
CS5506-BP
260 °C
1
No Limit
CS5506-BS
240 °C
2
365 Days
CS5506-BSZ (lead free)
260 °C
3
7 Days
CS5507-AP
260 °C
1
No Limit
CS5507-AS
240 °C
2
365 Days
CS5507-ASZ (lead free)
260 °C
3
7 Days
CS5508-BP
260 °C
1
No Limit
CS5508-BS
240 °C
2
365 Days
CS5508-BSZ (lead free)
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
30
DS59F4
DS59F5
CS5505/6/7/8
CS5505/6/7/8
REVISION HISTORY
APPENDIX
Revision
Date
Changes
The following
companies
kHz crystals in many package varieties and temperature
F4
MAR 1995 provide
First 32.768
Final Release
ranges.
F5
AUG 2005
Updated device ordering info. Updated legal notice. Added MSL data..
Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905
(813) 693-0099
Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005
(708) 806-1485
SaRonix
4010 Transport Street
Palo Alto, California 94303
(415) 856-6900
Statek
512 North Main
Orange, California 92668
(714) 639-7810
Taiwan X’tal Corp.
5F. No. 16, Sec 2, Chung Yang S. RD.
Reitou, Taipei, Taiwan R. O. C.
Tel: 02-894-1202
Fax: 02-895-6207
Interquip Limited
24/F Million Fortune Industrial Centre
34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
Fax: 4137053
S& T Enterprises, Ltd.
Rm 404 Blk B
Sea View Estate
North Point, Hong Kong
Tel: 5784921
Fax: 8073126
Mr. Darren Mcleod
Hy-Q International Pty. Ltd.
IQD Ltd.
North Street
12 Rosella Road,
Contacting CirrusCrewkerne
Logic Support
FRANKSON, 3199
For all product questions
andTA18
inquiries
contact a Cirrus Logic Sales Representative.Victoria, Australia
Somerset
7AK
To find the one nearest to
you go to www.cirrus.com
England
Tel: 61-3-783 9611
01460
77155
Fax:
61-3-783 9703
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
Mr. Pierre Hersberger
Microcrystal/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
CERTAIN APPLICATIONS USING
SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
065
53
05 57
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS,
PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-
VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
DS59F4
DS59F5
31
CS5505/6/7/8
• Notes •
- NOTES -
32
DS59F5
CDB5505/6/7/8
CDB5505/6/7/8
EvaluationBoard
Boardfor
forCS5505/6/7/8
CS5505/6/7/8Series
Seriesof
ofADC’s
ADCs
Evaluation
Features
Description
l Operation with on-board 32.768 kHz crystal
or off-board clock source
l Jumper selectable:
- SSC mode; SEC mode; Sleep
l DIP Switch Selectable:
- BP/UP mode; A0, & A1 channel selection
l On-board precision voltage reference
l Access to all digital control pins
l On-board patch area
The CDB5505/5506/5507/5508 is a circuit board designed to provide quick evaluation of the CS5505/6/7/8
series of A/D converters. The board can be configured to
evaluate the CS5505/6/7/8 in either SSC (Synchronous
Self-Clocking) or SEC (Synchronous External-Clocking)
serial port mode.
The board allows access to all of the digital interface pins
of the CS5505/6/7/8 chip.
ORDERING INFORMATION
CDB5505
CDB5506
CDB5507
CDB5508
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
I
AIN4+
CS5505/6/7/8
AIN3+
AIN2+
B
U
F
F
E
R
S
H
E
A
D
E
R
AIN1+
AIN-
CLKIN
VREF
+5V GND -5V
Cirrus Logic, Inc.
Crystal
Semiconductor Products Division
http://www.cirrus.com
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright
© Cirrus
Copyright © Cirrus
Logic, Inc.
2005Logic, Inc. 1998
(All Rights Reserved)
(All Rights Reserved)
AUG ‘95
‘05
MAR
DS59DB3
DS59DB2
33
CDB5505/6/7/8
CS5505/6/7/8
Introduction
The CDB5505/6/7/8 evaluation board provides a
quick means of testing the CS5505/6/7/8 series
A/D converters. The CS5505/6/7/8 converters
require a minimal amount of external circuitry.
The evaluation board comes configured with the
A/D converter chip operating from a 32.768 kHz
crystal and with an off-chip precision 2.5 volt
reference. The board provides access to all of
the digital interface pins of the CS5505/6/7/8
chip.
The board is configured for operation from +5
and -5 volt power supplies, but can be operated
from a single +5 volt supply if the -5V binding
post is shorted to the GND binding post.
Evaluation Board Overview
The board provides a complete means of making
the CS5505/6/7/8 A/D converter chip function.
The user must provide a means of taking the
output data from the board in serial format and
using it in his system.
Figure 1 illustrates the schematic for the board.
The board comes configured for the A/D converter chip to operate from the 32.768 kHz
watch crystal. A BNC connector for an external
clock is provided on the board. To connect the
external BNC source to the converter chip, a circuit trace must be cut. Then a jumper must be
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the
BNC. The BNC input is terminated with a 50Ω
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure 1.
The board comes with the A/D converter
VREF+ and VREF- pins hard-wired to the
2.5 volt bandgap voltage reference IC on the
board. The VREF+ and VREF- pins can be connected to either the on chip reference or an
off-board reference if the connections (2A and
2B) to the bandgap IC are cut.
Note that the pin-out of the CS5505/6/7/8 series
chips allows the 20-pin single channel devices to
be plugged into the 24-pin, four channel footprint. See Figure 2 which illustrates the footprint
compatibility.
Prior to powering up the board, select the serial
port operating mode with the appropriate jumper
on the M/SLP header. The device can be operated in either the SSC (Synchronous
Self-Clocking) or the SEC (Synchronous External Clocking) mode. See the device data sheet
for an explanation of these modes.
All of the control pins of the CS5505/6/7/8 are
available at the J1 header connector. Buffer ICs
U2 and U3 are used to buffer the converter for
interface to off-board circuits. The buffers are
used on the evaluation board only because the
exact loading and off-board circuitry is unknown. Most applications will not require the
buffer ICs for proper operation.
To put the board in operation, select either bipolar or unipolar mode with DIP switch S2. Then
press the CAL pushbutton after the board is
powered up. This initiates calibration of the converter which is required before measurements
can be taken.
To select an input channel on the four channel
devices, use DIP switch S2 to select the inputs
A1
A0
Channel addressed
0
0
AIN1
0
1
AIN2
1
0
AIN3
1
1
AIN4
Table 1. Multiplexer Truth Table
34
DS59DB2
DS59DB3
DS59DB2
DS59DB3
-5V
GND
+5V
AIN-
AIN1+
AIN2+
AIN3+
AIN4+
+
External
VREF _
R12
R31
100k
R30
100k
R29
100k
2
100k
402
402
402
402
R7
402
4
R13
R4
R5
R6
6
0.1 µF
C4
0.1 µF
C5
LT1019
-2.5 V 5
10 µF
R28
100k
0.1 µF
+5
C9
D2
6.8V
+ C3
C2
D1 +
10 µF
6.8V
+5
CLKIN
3B
3A
2B
2A
1B
1A
C15
R26
1K
R27
1K
0.1 µF
C6
R2
200
R3
50
17
9
10
AIN4+
VREF-
VREF+
AIN-
AIN1+
AIN2+
U1
CS5508
OR
CS5507
CS5506
CS5505
20
TP13
TP12
TP11
TP7
TP8
TP9
TP10
R24
100k
R23
100k
2
1
U2B
U2A
5
3
VD+
47k
R18
R17
R11
100k
14
11
U2F
8
U2E
15
12
R19
6
100k 47k
7
U2C
VD+
R20
10
100k
9
U2D
4
20k
VD+
R10
0.1 µF
C17
C11
0.01 µF
VD+
10
R22
M/SLP
Figure 1. ADC Connections
Y1
32.768
kHz
R14
100k
7
R15
VD+
SLEEP
SSC
SEC
100k
47k
R21
8
10
7
U3C
9
VD+
5 U3B 6
0.1 µF
VD+
R25
4
100k VD+
14
2 C18
U3A
R1
3
R16
100k
TP14
1
100k
11
12
BP/UP 8
U3D
13
SCLK 21
SDATA 22
DRDY 23
A1 24
A0 1
CS 2
CONV 3
CAL 4
VD+
0.1 µF
C10
VD+
VA- XIN XOUT DGND
19
18 5
6
-5
C1
0.1 µF
10
VREFOUT
VA+
12 AIN3+
13
15
14
16
TP15
11
TP6
TP5
TP4
TP3
C20
10nF
C19
10nF
C7
0.1 µF
0.01 µF 0.01 µF
C14
0.1 µF
0.01 µF
C13
0.01 µF
C12
R8 C8
25k
-5
DGND
AGND
+5
R9
CAL
+5
+
C16
10 µF
S2
BP/UP
SCLKI
SCLKO
SDATA
DRDY
A1
A0
CS
CONV
CAL
BP/UP
CONV
A0
A1
U2 74HC4050
U3 74HC125
J1
J2
SDATA
SCLK
DRDY
+5
+5
CDB5505/6/7/8
CS5505/6/7/8
35
CDB5505/6/7/8
CS5505/6/7/8
A0
1
CS
2/1
CONV
CS5505/6 24
A1
20/23
CS5507/8
19/22
3/2
DRDY
SDATA
CAL
4/3
18/21
SCLK
XIN
5/4
17/20
VD+
XOUT
6/5
16/19
DGND
M/SLP
7/6
15/18
VA-
BU/UP
8/7
14/17
VA+
AIN1+
9/8
13/16
VREFOUT
10/9
12/15
VREF-
11/10
11/14
VREF+
AIN2+/NC
AINAIN3+
12
13
AIN4+
Figure 2. CS5505/6 and CS5507/8 Pin Layouts
for A0 and A1 (see Table 1). Once A0 and A1
are selected, the CONV switch (S2-3) must be
switched on (closed) and then open to cause the
CONV signal to transition low to high. This
latches the A0 and A1 channel selection into the
converter. With CONV high (S2-3 open) the
converter will convert continuously.
Figures 3 and 4 illustrate the evaluation board
layout while Figure 5 illustrates the component
placement (silkscreen) of the evaluation board.
36
DS59DB2
DS59DB3
CDB5505/6/7/8
CS5505/6/7/8
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
DS59DB2
DS59DB3
37
CDB5505/6/7/8
CS5505/6/7/8
Figure 4. Bottom Trace Layer (NOT TO SCALE)
38
DS59DB2
DS59DB3
CDB5505/6/7/8
CS5505/6/7/8
Figure 5. Silk Screen Layer (NOT TO SCALE)
DS59DB2
DS59DB3
39
CDB5505/6/7/8
REVISION HISTORY
Revision
Date
Changes
DB2
MAR 1995
First Release
F5
AUG 2005
Updated legal notice.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
40
DS59DB3