Cypress CY7C194-35 64k x 4 static ram Datasheet

96
CY7C194
CY7C195
CY7C196
64K x 4 Static RAM
Features
able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) and three-state drivers. They have an automatic
power-down feature, reducing the power consumption by 75%
when deselected.
• High speed
— 12 ns
• Output enable (OE) feature (7C195 and 7C196)
• CMOS for optimum speed/power
• Low active power
— 880 mW
• Low standby power
— 220 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Writing to the device is accomplished when the Chip Enable(s)
(CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) and Write Enable (WE) inputs are both LOW. Data
on the four input pins (I/O0 through I/O3) is written into the
memory location, specified on the address pins (A0 through
A15).
Reading the device is accomplished by taking the Chip Enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) LOW, while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location
specified on the address pins will appear on the four data I/O
pins.
Functional Description
The CY7C194, CY7C195, and CY7C196 are high-performance CMOS static RAMs organized as 65,536 by 4 bits.
Easy memory expansion is provided by active LOW Chip En-
A die coat is used to ensure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
DIP/SOJ
Top View
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
I/O3
SENSE AMPS
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
ROW DECODER
INPUT BUFFER
1024 x 64 x 4
ARRAY
1
2
3
4
5
6 7C194
7
8
9
10
11
12
CE
GND
I/O2
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A5
A4
A3
A2
A1
A0
I/O3
I/O2
I/O1
I/O0
WE
NC
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
CE1
OE
GND
1
2
3
4
5
6 7C195
7 7C196
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A5
A4
A3
A2
A1
A0
NC
I/O3
I/O2
I/O1
I/O0
WE
CE2
(7C196)
NC
(7C195)
C194-2
C194-3
I/O1
I/O0
POWER
DOWN
CE2 (7C196 only)
CE1
WE
(OE)
(7C195 and
7C196 ONLY)
A15
A0
A11
A12
A13
A14
COLUMN
DECODER
C194-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05162 Rev. **
7C194-12
7C195-12
7C196-12
12
155
30
•
7C194-15
7C195-15
7C196-15
15
145
30
3901 North First Street
7C194-20
7C195-20
7C196-20
20
135
30
•
7C194-25
7C195-25
7C196-25
25
115
30
San Jose
•
7C194-35
7C195-35
7C196-35
35
115
30
7C194-45
7C196-45
45
30
CA 95134 • 408-943-2600
Revised September 18, 2001
CY7C194
CY7C195
CY7C196
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Commercial
Ambient
Temperature[2]
VCC
0°C to +70°C
5V ± 10%
]
Electrical Characteristics Over the Operating Range
7C194-12
7C195-12
7C196-12
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL[1]
Input LOW Voltage
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VO < VCC,
Output Disabled
IOS
Output Short
Circuit Current[3]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
Min.
Max.
2.4
7C194-15
7C195-15
7C196-15
Min.
Max.
2.4
0.4
Unit
V
0.4
V
2.2
VCC
+ 0.3V
2.2
VCC
+ 0.3V
V
−0.5
0.8
−0.5
0.8
V
−5
+5
−5
+5
µA
−5
+5
−5
+5
µA
−300
−300
mA
VCC =Max., IOUT =0 mA,
f=fMAX =1/tRC
155
145
mA
Automatic CE
Power-Down Current
—TTL Inputs[4]
Max. VCC, CE1,2 > VIH,
VIN > VIH or VIN < VIL, f = fMAX
30
30
mA
Automatic CE
Power-Down Current
—CMOS Inputs[4]
Max. VCC, CE1,2 > VCC - 0.3V,
VIN > VCC - 0.3V or
VIN < 0.3V, f = 0
10
10
mA
Notes:
1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
Document #: 38-05162 Rev. **
Page 2 of 12
CY7C194
CY7C195
CY7C196
)
Electrical Characteristics Over the Operating Range (continued)
7C194-20
7C195-20
7C196-20
Parameter
Description
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
+ 0.3V
VIL
Input LOW Voltage
–0.5
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VO < VCC,
Output Disabled
IOS
Output Short
Circuit Current[3]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
7C194-25, 35, 45
7C195-25, 35
7C196-25, 35, 45
Min.
2.4
Max.
Unit
2.4
0.4
V
0.4
V
2.2
VCC
+0.3V
V
0.8
–0.5
0.8
V
–5
+5
–5
+5
µA
–5
+5
–5
+5
µA
–300
–300
mA
VCC=Max., IOUT=0 mA,
f=fMAX=1/tRC
135
115
mA
Automatic CE
Power-Down Current
—TTL Inputs[4]
Max. VCC, CE1,2 > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
30
30
mA
Automatic CE
Power-Down Current
—CMOS Inputs[4]
Max. VCC, CE1,2 > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V, f = 0
15
15
mA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
10
pF
AC Test Loads and Waveforms[6]
R1 481Ω
5V
OUTPUT
R1 481Ω
5V
ALL INPUT PULSES
OUTPUT
R2
255Ω
30 pF
INCLUDING
JIG AND
SCOPE (a)
3.0V
5 pF
INCLUDING
JIG AND
SCOPE (b)
R2
255Ω
GND
90%
10%
< tr
C194-4
90%
10%
< tr
C194-5
Equivalent to:
THÉ
EVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. tr = < 3 ns for the -12 and -15 speeds. T.r = < 5 ns for the -20 and slower speeds.
Document #: 38-05162 Rev. **
Page 3 of 12
CY7C194
CY7C195
CY7C196
:
Switching Characteristics Over the Operating Range[7]
7C194-12
7C195-12
7C196-12
Parameter
Description
Min.
Max.
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7C194-45
7C196-45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data
Valid
tOHA
Output Hold from
Address Change
tACE1,
tACE2
CE LOW to
Data Valid
tDOE
OE LOW to
Data Valid
7C195,
7C196
tLZOE
OE LOW to
Low Z
7C195,
7C196
tHZOE
OE HIGH to
High Z[8]
7C195,
7C196
tLZCE1,
tLZCE2
CE LOW to
Low Z[8]
tHZCE1,
tHZCE2
CE HIGH to
High Z[8,8]
tPU
CE LOW to
Power-Up
tPD
CE HIGH to
Power-Down
12
15
12
3
20
15
3
25
20
3
35
25
3
45
35
3
ns
45
3
ns
ns
12
15
20
25
35
45
ns
5
7
9
10
16
16
ns
0
0
5
3
0
7
3
5
0
9
3
7
0
12
3
11
3
9
0
15
3
15
3
11
0
20
3
15
3
15
0
25
ns
ns
15
0
35
ns
ns
ns
45
ns
WRITE CYCLE[10]
tWC
Write Cycle Time
12
15
20
25
35
45
ns
tSCE
CE LOW to Write End
9
10
15
18
22
22
ns
tAW
Address Set-Up to
Write End
9
10
15
20
25
35
ns
tHA
Address Hold from
Write End
0
0
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
tPWE
WE Pulse Width
8
9
15
18
22
22
ns
tSD
Data Set-Up to
Write End
8
9
10
10
15
15
ns
tHD
Data Hold from
Write End
0
0
0
0
0
0
ns
tLZWE
WE HIGH to
Low Z[8]
3
3
3
3
3
3
ns
tHZWE
WE LOW to
High Z[8, 9]
7
7
10
0
13
0
15
0
20
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, and WE LOW. All signals must be LOW to initiate a write and any signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05162 Rev. **
Page 4 of 12
CY7C194
CY7C195
CY7C196
Switching Waveforms
Read Cycle No. 1 [11, 12]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
C194-8
Read Cycle No. 2
[11, 13]
t RC
CE1, CE2
tACE
OE
(7C195 and
7C196)
DATA OUT
t HZOE
t HZCE
tDOE
t LZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
t LZCE
VCC
SUPPLY
CURRENT
tPD
t PU
ICC
50%
50%
ISB
C194-6
Write Cycle No. 1 (CE Controlled) [10, 14, 15]
tWC
ADDRESS
CE1
CE2
(7C196)
tSCE
tSA
tHA
tAW
WE
tSD
DATA I/O
tHD
DATA VALID
C194-7
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected: CE1 = VIL, CE2 = VIL (7C196), and OE = VIL (7C195 and 7C196).
13. Address valid prior to or coincident with CE1 and CE2 transition LOW.
14. Data I/O will be high impedance if OE = VIH (7C195 and 7C196).
15. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05162 Rev. **
Page 5 of 12
CY7C194
CY7C195
CY7C196
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write for 7C195 and 7C196only)
[10, 14, 15]
tWC
ADDRESS
CE1
CE2 (7C196)
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
tHD
DATA VALID
C194-8
tHZOE
Write Cycle No. 3 (WE Controlled, OE LOW)
[15, 16]
tWC
ADDRESS
CE1
CE2 (7C196)
tAW
WE
tHA
tSA
tSD
DATA I/O
tHD
DATA VALID
tHZWE
tLZWE
C194-9
Note:
16. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05162 Rev. **
Page 6 of 12
CY7C194
CY7C195
CY7C196
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SB
1.4
1.2
ICC
0.8
VIN =5.0V
TA =25°C
0.4
0.2
1.0
0.8
0.6
VCC =5.0V
VIN =5.0V
0.4
0.2
ISB
0.0
4.0
1.2
4.5
5.0
5.5
ISB
0.0
−55
6.0
25
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
1.3
NORMALIZED tAA
NORMALIZED tAA
1.4
1.2
1.1
TA =25°C
1.0
1.4
1.2
1.0
VCC =5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
0.6
−55
6.0
25
120
100
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
DELTA tAA (ns)
3.0
2.0
1.5
1.0
0.5
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE(V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
VCC =5.0V
TA =25°C
40
20
0
0.0
125
AMBIENT TEMPERATURE (°C)
0.0
0.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE(°C)
SUPPLY VOLTAGE(V)
NORMALIZED I PO
125
OUTPUT SINK CURRENT (mA)
0.6
ICC
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED I CC vs.CYCLE TIME
1.25
20.0
15.0
VCC =4.5V
TA =25°C
10.0
NORMALIZED I CC
1.0
NORMALIZED I,CCI
NORMALIZED I,CC
I
SB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
1.00
VCC =5.0V
TA =25°C
VIN =0.5V
0.75
5.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-05162 Rev. **
5.0
0.0
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 7 of 12
CY7C194
CY7C195
CY7C196
7C194 Truth Table
CE
WE
Data I/O
Mode
Power
H
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
Data Out
Read
Active (ICC)
L
L
Data In
Write
Active (ICC)
7C195 Truth Table
CE1
WE
OE
Data I/O
Mode
Power
H
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect
Active (ICC)
7C196 Truth Table
CE1
CE2
WE
OE
H
X
X
X
X
H
X
X
L
L
H
L
L
L
L
Data I/O
Mode
Power
High Z
Deselect/Power-Down
Standby (ISB)
L
Data Out
Read
Active (ICC)
L
X
Data In
Write
Active (ICC)
H
H
High Z
Deselect
Active (ICC)
Document #: 38-05162 Rev. **
Page 8 of 12
CY7C194
CY7C195
CY7C196
Ordering Information
Speed (ns)
12
15
20
25
35
45
Speed (ns)
Ordering Code
CY7C194-12PC
Package Name
P13
Package Type
24-Lead (300-Mil) Molded DIP
CY7C194-12VC
V13
24-Lead Molded SOJ
CY7C194-15PC
P13
24-Lead (300-Mil) Molded DIP
CY7C194-15VC
V13
24-Lead Molded SOJ
CY7C194-20PC
P13
24-Lead (300-Mil) Molded DIP
CY7C194-20VC
V13
24-Lead Molded SOJ
CY7C194-25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C194-25VC
V13
24-Lead Molded SOJ
CY7C194-35PC
P13
24-Lead (300-Mil) Molded DIP
CY7C194-35VC
V13
24-Lead Molded SOJ
CY7C194-45PC
P13
24-Lead (300-Mil) Molded DIP
CY7C194-45VC
V13
24-Lead Molded SOJ
Ordering Code
Package Name
P21
Package Type
12
CY7C195-12PC
28-Lead (300-Mil) Molded DIP
CY7C195-12VC
V21
28-Lead Molded SOJ
15
CY7C195-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C195-15VC
V21
28-Lead Molded SOJ
20
CY7C195-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C195-20VC
V21
28-Lead Molded SOJ
25
CY7C195-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C195-25VC
V21
28-Lead Molded SOJ
35
CY7C195-35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C195-35VC
V21
28-Lead Molded SOJ
45
CY7C195-45PC
P21
28-Lead (300-Mil) Molded DIP
CY7C195-45VC
V21
28-Lead Molded SOJ
Operating Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Operating Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
)
Speed (ns)
12
15
20
25
35
Ordering Code
Package Name
Package Type
CY7C196-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7C196-12VC
V21
28-Lead Molded SOJ
CY7C196-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C196-15VC
V21
28-Lead Molded SOJ
CY7C196-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C196-20VC
V21
28-Lead Molded SOJ
CY7C196-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C196-25VC
V21
28-Lead Molded SOJ
CY7C196-35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C196-35VC
V21
28-Lead Molded SOJ
Document #: 38-05162 Rev. **
Operating Range
Commercial
Commercial
Commercial
Commercial
Commercial
Page 9 of 12
CY7C194
CY7C195
CY7C196
Package Diagrams
24-Lead (300-Mil) Molded DIP P13/P13A
51-85013-A
28-Lead (300-Mil) Molded DIP P21
51-85014-B
Document #: 38-05162 Rev. **
Page 10 of 12
CY7C194
CY7C195
CY7C196
Package Diagrams (continued)
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
Document #: 38-05162 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C194
CY7C195
CY7C196
Document Title: CY7C194/CY7C195/CY7C196 64K x 4 Static RAM
Document Number: 38-05162
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110172
09/29/01
SZV
Change from Spec number: 38-00081 to 38-05162
Document #: 38-05162 Rev. **
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