PRELIMINARY Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters n 10-bit resolution n 20/40/65/80MSPS maximum sampling rate n Ultra-low power dissipation: 24/43/65/78mW n 61.6dB SNR at 8MHz FIN n Internal reference circuitry n 1.8V core supply voltage n 1.7V – 3.6V I/O supply voltage n Parallel CMOS output n 64-pin TQFP package n Dual channel n Pin compatible with CDK2307 Several idle modes with fast startup times exist. Each channel can independently be powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs. A ppli c a t i o n s n Portable Test Equipment n Digital Oscilloscopes n IF Communication Functional Block Diagram CLKN Medical Imaging CLKP n The CDK2308 is a high performance, low power dual Analog-to-Digital Converters (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. CLK_EXT Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK2308AITQ64 20MSPS TQFP-64 Yes Yes -40°C to +85°C Tray CDK2308AITQ64X 20MSPS TQFP-64 Yes Yes -40°C to +85°C Tape & Reel CDK2308BITQ64 40MSPS TQFP-64 Yes Yes -40°C to +85°C Tray CDK2308BITQ64X 40MSPS TQFP-64 Yes Yes -40°C to +85°C Tape & Reel CDK2308CITQ64 65MSPS TQFP-64 Yes Yes -40°C to +85°C Tray CDK2308CITQ64X 65MSPS TQFP-64 Yes Yes -40°C to +85°C Tape & Reel CDK2308DITQ64 80MSPS TQFP-64 Yes Yes -40°C to +85°C Tray CDK2308DITQ64X 80MSPS TQFP-64 Yes Yes -40°C to +85°C Tape & Reel Moisture sensitivity level for all parts is MSL-3. ©2008 CADEKA Microcircuits LLC www.cadeka.com Rev 0.1.1 Ordering Information CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters General Description f ea t u re s PRELIMINARY Data Sheet Pin Configuration D0_5 D0_4 D0_3 51 50 49 52 53 54 55 56 57 58 59 60 61 62 63 1 48 2 47 3 46 4 45 N/C 5 44 N/C 6 43 N/C 42 CLK_EXT CDK2308 7 TQFP-64 8 41 32 31 30 29 28 CLK_EXT_EN N/C 33 27 16 26 34 CLKN N/C 15 N/C 35 CLKP 25 14 24 36 DVDDCLK 23 13 22 37 DVSSCLK 21 38 12 20 39 11 19 40 18 9 10 17 CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters 64 TQFP-64 Pin Assignments Pin No. Pin Name 1, 18, 23 DVDD Description Digital and I/O-ring pre driver supply voltage, 1.8V CM_EXT AVDD Common Mode voltage output Analog supply voltage, 1.8V 4, 5, 8 AVSS Analog ground 6, 7 IP0, IN0 Analog input Channel 0 (non-inverting, inverting) 10, 11 IP1, IN1 Analog input Channel 1 (non-inverting, inverting) 13 DVSSCLK Clock circuitry ground 14 DVDDCLK Clock circuitry supply voltage, 1.8V 15 CLKP Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave) 16 CLKN Clock input, inverting. For CMOS input on CLKP, bypass CLKN to ground with a 10nF capacitor 17, 64 DVSS Digital circuitry ground 19 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high. 20 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement 21 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. 22 OE_N_1 24, 41, 58 OVDD I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. 25, 40, 57 OVSS Ground for I/O ring 26 NC ©2008 CADEKA Microcircuits LLC Rev 0.1.1 2 3, 9, 12 Output Enable Channel 0. Tristate when high No Connect www.cadeka.com 2 PRELIMINARY Data Sheet Pin Assignments (Continued) Pin Name Description 27 NC No Connect 28 NC No Connect 29 D1_0 Output Data Channel 1 (LSB) 30 D1_1 Output Data Channel 1 31 D1_2 Output Data Channel 1 32 D1_3 Output Data Channel 1 33 D1_4 Output Data Channel 1 34 D1_5 Output Data Channel 1 35 D1_6 Output Data Channel 1 36 D1_7 Output Data Channel 1 37 D1_8 Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section) 38 D1_9 Output Data Channel 1 (MSB for 2Vpp full scale range) 39 ORNG_1 Out of Range flag Channel 1. High when input signal is out of range 42 CLK_EXT Output clock signal for data synchronization. CMOS levels. 43 NC No Connect 44 NC No Connect 45 NC No Connect 46 D0_0 Output Data Channel 0 47 D0_1 Output Data Channel 0 48 D0_2 Output Data Channel 0 49 D0_3 Output Data Channel 0 50 D0_4 Output Data Channel 0 51 D0_5 Output Data Channel 0 52 D0_6 Output Data Channel 0 53 D0_7 Output Data Channel 0 54 D0_8 Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section) 55 D0_9 Output Data Channel 0 (MSB for 2Vpp full scale range) 56 ORNG_0 Out of Range flag Channel 0. High when input signal is out of range. 59 OE_N_0 Output Enable Channel 0. Tristate when low. 60, 61 CM_EXTBC_1, CM_EXTBC_0 62, 63 SLP_N_1, SLP_N_0 Bias control bits for the buffer driving pin CM_EXT 00: Off 10: 50uA@50MSPS 10: 500uA@50MSPS 11: 1mA@50MSPS Sleep Mode 00: Sleep Mode 10: Channel 1 active Rev 0.1.1 ©2008 CADEKA Microcircuits LLC CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Pin No. 01: Channel 0 active 11: Both channels active www.cadeka.com 3 PRELIMINARY Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Min Max Unit AVDD, AVSS DVDD, DVSS AVSS, DVSSCK, DVSS, OVSS OVDD, OVSS CKP, CKN, DVSSCK Analog inputs and outpts (IPx, INx, AVSS) Digital inputs Digital outputs -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9 V V V V V V V V CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Parameter Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 64-Lead TQFP Min Typ Max Unit TBD +150 TBD °C °C °C TBD °C/W -60 Notes: Package thermal resistance (θJA), JDEC standard, multi-layer test boards, still air. ESD Protection Product TQFP-64 Human Body Model (HBM) Charged Device Model (CDM) TBD TBD Recommended Operating Conditions Parameter Min Operating Temperature Range -40 Typ Max Unit +85 °C Rev 0.1.1 ©2008 CADEKA Microcircuits LLC www.cadeka.com 4 PRELIMINARY Data Sheet Electrical Characteristics (AVDD=1.8V, DVDD=1.8V, DVDDCLK=1.8V, OVDD=2.5V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DC Accuracy Guaranteed Offset Error Midscale offset TBD Gain Error Full scale range deviation from typical Gain Matching Gain matching between channels DLE Differential Non-Linearity 12-bit level -1 ILE Integral Non-Linearity 12-bit level -1 VCMO Common Mode Voltage Output -6 mV 6 ±0.05 %FS %FS 1 LSB 1 LSB VAVDD/2 V Analog Input VCMI Input Common Mode Analog input common mode voltage Full Scale Range, Normal Differential input voltage range, 2.0 Vpp Full Scale Range, Option Differential input voltage range, 1V (see section Reference Voltages) 1.0 Vpp Input Capacitance Differential input capacitance Bandwidth Input bandwidth, full power 500 AVDD, DVDD Core Supply Voltage Supply voltage to all 1.8V domain pins. See Pin Configuration and Description 1.7 1.8 1.9 V 2.5 3.6 V I/O Supply Voltage Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VOCVDD) 1.7 OVDD VFSR VCM -0.1 VCM +0.1 V 1.8 pF MHz Power Supply CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters No Missing Codes Rev 0.1.1 ©2008 CADEKA Microcircuits LLC www.cadeka.com 5 PRELIMINARY Data Sheet Electrical Characteristics - CDK2308A (AVDD=1.8V, DVDD=1.8V, DVDDCLK=1.8V, OVDD=2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNDR SFDR HD2 HD3 ENOB XTALK Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Crosstalk 61.7 dBFS FIN = 8MHz 61.6 dBFS FIN = FS / 2 61.6 dBFS FIN = 20MHz 61.6 dBFS FIN = 2MHz 61.7 dBFS FIN = 8MHz 61.6 dBFS FIN = FS / 2 60.5 dBFS FIN = 20MHz 61.6 dBFS FIN = 2MHz 84.1 dBc FIN = 8MHz 85.5 dBc FIN = FS / 2 70.3 dBc FIN = 20MHz 87.5 dBc FIN = 2MHz -88.8 dBc FIN = 8MHz -89.5 dBc FIN = FS / 2 -95.9 dBc FIN = 20MHz -91.4 dBc FIN = 2MHz -89.5 dBc FIN = 8MHz -90.5 dBc FIN = FS / 2 -70.3 dBc FIN = 20MHz -89.7 dBc FIN = 2MHz 10.0 bits FIN = 8MHz 9.9 bits FIN = FS / 2 9.8 bits FIN = 20MHz 9.9 bits -105 dBc Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD Output Driver Supply 8.2 mA Digital core supply 1.7 mA 2.5V output driver supply, sine wave input, FIN = 1MHz 2.8 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 2.3 mA 14.8 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 8.8 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 23.7 mW 9.9 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 15.2 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 7.7 mW Power Down Dissipation Rev 0.1.1 Analog Power Dissipation Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC 20 MSPS 15 MSPS www.cadeka.com CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters SNR FIN = 2MHz 6 PRELIMINARY Data Sheet Electrical Characteristics - CDK2308B (AVDD=1.8V, DVDD=1.8V, DVDDCLK=1.8V, OVDD=2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNDR SFDR HD2 HD3 ENOB XTALK Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Crosstalk 61.6 dBFS FIN = 8MHz 61.6 dBFS FIN = FS / 2 61.6 dBFS FIN = 30MHz 61.5 dBFS FIN = 2MHz 61.6 dBFS FIN = 8MHz 61.6 dBFS FIN = FS / 2 61.2 dBFS FIN = 30MHz 61.4 dBFS FIN = 2MHz 78.8 dBc FIN = 8MHz 82.3 dBc FIN = FS / 2 72.0 dBc FIN = 30MHz 82.5 dBc FIN = 2MHz -87.9 dBc FIN = 8MHz -92.0 dBc FIN = FS / 2 -84.8 dBc FIN = 30MHz -88.8 dBc FIN = 2MHz -81.8 dBc FIN = 8MHz -85.7 dBc FIN = FS / 2 -72.0 dBc FIN = 30MHz -83.9 dBc FIN = 2MHz 9.9 bits FIN = 8MHz 9.9 bits FIN = FS / 2 9.9 bits FIN = 30MHz 9.9 bits -102 dBc Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD Output Driver Supply 14.4 mA Digital core supply 3.4 mA 2.5V output driver supply, sine wave input, FIN = 1MHz 5.1 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 4.2 mA 25.9 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 16.6 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 42.5 mW 9.7 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 25.7 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 11.3 mW Power Down Dissipation Rev 0.1.1 Analog Power Dissipation Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC 40 MSPS 20 MSPS www.cadeka.com CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters SNR FIN = 2MHz 7 PRELIMINARY Data Sheet Electrical Characteristics - CDK2308C (AVDD=1.8V, DVDD=1.8V, DVDDCLK=1.8V, OVDD=2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNDR SFDR HD2 HD3 ENOB XTALK Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Crosstalk 61.6 dBFS FIN = 20MHz 61.6 dBFS FIN = FS / 2 61.5 dBFS FIN = 40MHz 61.3 dBFS FIN = 8MHz 61.6 dBFS FIN = 20MHz 61.6 dBFS FIN = FS / 2 60.4 dBFS FIN = 40MHz 61.1 dBFS FIN = 8MHz 80.6 dBc FIN = 20MHz 85.6 dBc FIN = FS / 2 66.4 dBc FIN = 40MHz 76.9 dBc FIN = 8MHz -91.4 dBc FIN = 20MHz -93 dBc FIN = FS / 2 -83.8 dBc FIN = 40MHz -90.7 dBc FIN = 8MHz -80.6 dBc FIN = 20MHz -86.4 dBc FIN = FS / 2 -66.4 dBc FIN = 40MHz -76.9 dBc FIN = 8MHz 9.9 bits FIN = 20MHz 9.9 bits FIN = FS / 2 9.7 bits FIN = 40MHz 9.9 bits -97.0 dBc Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD Output Driver Supply 22.0 mA Digital core supply 5.2 mA 2.5V output driver supply, sine wave input, FIN = 1MHz 7.9 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 6.4 mA 39.6 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 25.4 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 65.0 mW 9.3 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 38.2 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 15.7 mW Power Down Dissipation Rev 0.1.1 Analog Power Dissipation Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC 65 MSPS 40 MSPS www.cadeka.com CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters SNR FIN = 8MHz 8 PRELIMINARY Data Sheet Electrical Characteristics - CDK2308D (AVDD=1.8V, DVDD=1.8V, DVDDCLK=1.8V, OVDD=2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNDR SFDR HD2 HD3 ENOB XTALK Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Crosstalk 61.6 dBFS FIN = 20MHz 61.2 dBFS FIN = 30MHz 61.3 dBFS FIN = FS / 2 61.3 dBFS FIN = 8MHz 61.3 dBFS FIN = 20MHz 60.7 dBFS FIN = 30MHz 61.0 dBFS FIN = FS / 2 58.7 dBFS FIN = 8MHz 74.8 dBc FIN = 20MHz 73.9 dBc FIN = 30MHz 74.7 dBc FIN = FS / 2 61.7 dBc FIN = 8MHz -88.5 dBc FIN = 20MHz -95.0 dBc FIN = 30MHz -88.9 dBc FIN = FS / 2 -79.0 dBc FIN = 8MHz -74.8 dBc FIN = 20MHz -75.0 dBc FIN = 30MHz -74.7 dBc FIN = FS / 2 -61.7 dBc FIN = 8MHz 9.9 bits FIN = 20MHz 9.8 bits FIN = 30MHz 9.8 bits FIN = FS / 2 9.5 bits -95.0 dBc Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD Output Driver Supply 26.5 mA Digital core supply 6.1 mA 2.5V output driver supply, sine wave input, FIN = 1MHz 9.5 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 7.6 mA 47.7 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 30.0 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 77.7 mW 9.1 µW Sleep Mode 1 Power Dissipation, Sleep mode one channel 46.1 mW Sleep Mode 2 Power Dissipation, Sleep mode both channels 18.3 mW Power Down Dissipation Rev 0.1.1 Analog Power Dissipation Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC 80 MSPS 65 MSPS www.cadeka.com CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters SNR FIN = 8MHz 9 PRELIMINARY Data Sheet Digital and Timing Electrical Characteristics (AVDD=1.8V, DVDD=1.8V, DVDDCLK=1.8V, OVDD=2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 80 % high Clock Inputs 20 Compliance CMOS, LVDS, LVPECL, Sine Wave Differential input swing -200 200 mVpp Differential input swing, sine wave clock input -800 800 mVpp Input Common Mode Voltage Keep voltages within ground and voltage of OVDD 0.3 VOVDD -0.3 V Input Resistance Differential TBD kΩ Input Capacitance Differential 1.7 pF TPD Start Up Time Active Mode From Power Down Mode to References has eached 99% of final value TSLP Start Up Time Mode From Sleep Mode to Active TOVR Out Of Range Recovery Time TAP Aperture Delay 0.8 ns TLAT Pipeline Delay 12 clk cycles TD Output Delay (see timing diagram) TDC Output Delay (see timing diagram) Input Range Timing 580 5pF load on output bits clk cycles 0.5 µs 4 clk cycles 4 10pF load on output bits ns TBD Relative to CLK_EXT ns 2 ns Logic Inputs VIH High Level Input Voltage VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V VOVDD ≥ 3.0V 2 V 0.8 • VOVDD V 0 0.8 V VIL Low Level Input Voltage 0 0.2 • VOVDD V IIH High Level Input Leakage Current -10 10 µA IIL Low Level Input Leakage Current -10 10 µA CI Input Capacitance VOVDD = 1.7V – 3.0V 3 pF Logic Outputs VOH High Level Output Voltage VOL Low Level Output Voltage CL Max Capacitive Load -0.1 +VOVDD V Post-driver supply voltage equal to pre-driver supply voltage VOVDD = VOCVDD Post-driver supply voltage above 2.25V (1) 0.1 V 5 pF 10 pF Note: ©2008 CADEKA Microcircuits LLC www.cadeka.com Rev 0.1.1 (1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum. CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Duty Cycle 10 PRELIMINARY Data Sheet +F1 +F4 +F +F2 +F0 + N-12 N-11 N-10 N-9 N-8 CLK_EXT Figure 1. Timing Diagram Recommended Usage DC-Coupling Analog Input Figure 3 shows a recommended configuration for DCcoupling. Note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_EXT output should be used as a reference to set the common mode voltage. The analog inputs to the CDK2308 is a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The CM_EXT pin provides a voltage suitable as common mode voltage reference. The internal buffer for the CM_EXT voltage can be switched off, and driving capabilities can be changed by using the CM_EXTBC control input. Ω pF Ω Rev 0.1.1 Figure 2 shows a simplified drawing of the input network. The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22Ω) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. The input amplifier could be inside a companion chip or it could be a dedicated amplifier. Several suitable single ended to differential driver amplifiers exist in the market. The system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the CDK2308 input specifications. Figure 3. DC-Coupled Input Detailed configuration and usage instructions must be found in the documentation of the selected driver. AC-Coupling Figure 2. Input Configuration ©2008 CADEKA Microcircuits LLC A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 4 shows a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected, www.cadeka.com CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters N-13 N-13 11 PRELIMINARY Data Sheet If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. If this problem could not be avoided, the circuit in Figure 6 can be used. Note that startup time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. If the input signal has a long traveling distance, and the kick-backs from the ADC not are effectively terminated at the signal source, the input network of figure 8 can be used. The configuration in figure 8 is designed to attenuate the kickback from the ADC and to provide an input impedance that looks as resistive as possible for frequencies below Nyquist. Values of the series inductor will however depend on board design and conversion rate. In some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pF) may improve ADC performance further. This capacitor attenuate the ADC kickback even more, and minimize the kicks traveling towards the source. However, the impedance match seen into the transformer becomes worse. 120nH 33Ω 1:1 33Ω optional RT 47Ω RT 68Ω 220Ω pF 120nH 33Ω 33Ω Figure 4. Transformer-Coupled Input Ω pF Ω Figure 5. AC-Coupled Input ©2008 CADEKA Microcircuits LLC Clock Input And Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In the CDK2308 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, and hence a wide common mode voltage range is accepted. Differential clock sources as LVDS, LVPECL or differential sine wave can be connected directly to the input pins. For CMOS inputs, the CLKN pin should be connected to ground, and the CMOS clock signal should be connected to CLKP. For differential sine wave clock input the amplitude must be at least 1Vpp. www.cadeka.com 12 Rev 0.1.1 Figure 5 shows AC-coupling using capacitors. Resistors from the CM_EXT output, RCM, should be used to bias the differential input signals to the correct voltage. The series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. Figure 6. Alternative Input Network CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters and that the bandwidth of the transformer is appropriate. The bandwidth should exceed the sampling rate of the ADC with at least a factor of 10. It is also important to keep phase mismatch between the differential ADC inputs small for good HD2 performance. This type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. PRELIMINARY Data Sheet The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation 1. • π • FIN • εt) where FIN is the signal frequency, and εt is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be retimed with a low jitter master clock as the last operation before it is applied to the ADC clock input. Digital Outputs The timing is described in the Timing Diagram section. Note that the load or equivalent delay on CLK_EXT always should be lower than the load on data outputs to ensure sufficient timing margins. The digital outputs can be set in tristate mode by setting the OE_N signal high. ©2008 CADEKA Microcircuits LLC The output data are presented on offset binary form when DFRMT is low (connect to OVSS). Setting DFRMT high (connect to OVDD) results in 2’s complement output format. Details are shown in Table 1 on page 14. Reference Voltages The reference voltages are internally generated and buffered based on a bandgap voltage reference. No external decoupling is necessary, and the reference voltages are not available externally. This simplifies usage of the ADC since two extremely sensitive pins, otherwise needed, are removed from the interface. Operational Modes The operational modes are controlled with the PD_N and SLP_N pins. If PD_N is set low, all other control pins are overridden and the chip is set in Power Down mode. In this mode all circuitry is completely turned off and the internal clock is disabled. Hence, only leakage current contributes to the Power Down Dissipation. The startup time from this mode is longer than for other idle modes as all references need to settle to their final values before normal operation can resume. The SLP_N bus can be used to power down each channel independently, or to set the full chip in Sleep Mode. In this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. However, Sleep Mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. The input clock should be kept running in all idle modes. However, even lower power dissipation is possible in Power Down mode if the input clock is stopped. In this case it is important to start the input clock prior to enabling active mode. www.cadeka.com 13 Rev 0.1.1 Digital output data are presented on parallel CMOS form. The voltage on the OVDD pin set the levels of the CMOS outputs. The output drivers are dimensioned to drive a wide range of loads for OVDD above 2.25V, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. In applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the ADC chip. Data Format Selection CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters SNRjitter = 20 • log (2 The CDK2308 employs digital offset correction. This means that the output code will be 4096 with the positive and negative inputs shorted together(zero differential). However, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also results in possible loss of codes at the edges of the full scale range. With “NO” offset correction, the ADC would clip in one end before the other, in practice resulting in code loss at the opposite end. With the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. When out of range flags are set, the code is forced to all ones for over-range and all zeros for under-range. PRELIMINARY Data Sheet Table 1: Data Format Description for 2Vpp Full Scale Range Output Data: Dx_9 : Dx_0 (DFRMT = 0, offset binary) (DFRMT = 1, 2’s complement) 1.0 V 11 1111 1111 01 1111 1111 +0.24mV 10 0000 0000 00 0000 0000 -0.24mV 01 1111 1111 11 1111 1111 -1.0V 00 0000 0000 10 0000 0000 Mechanical Dimensions TQFP-64 Package Symbol A A1 A2 D D1 E E1 R2 R1 θ θ1 θ2 θ3 c L L1 S b e D2 E2 aaa bbb ccc ddd Min – 0.002 0.037 0.003 0.003 0° 0° 11° 11° 0.004 0.018 0.008 0.007 Inches Typ – – 0.039 0.472 BSC 0.393 BSC 0.472 BSC 0.393 BSC – – 3.5° – 12° 12° – 0.24 0.039 REF – 0.008 0.020 BSC 0.295 0.295 0.008 0.008 0.003 0.003 Max 0.047 0.006 0.041 Min – 0.05 0.95 0.008 – 7° – 13° 13° 0.008 0.030 0.08 0.08 0° 0° 11° 11° 0.09 0.45 – 0.011 0.20 0.17 Millimeters Typ – – 1.00 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC – – 3.5° – 12° 12° 0.20 0.75 1.00 REF – 0.20 0.520 BSC 7.50 7.50 0.20 0.20 0.08 0.08 Max – 0.15 1.05 0.20 – 7° – 13° 13° – 0.27 NOTE: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maxmum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. 3. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Output data: Dx_9 : Dx_0 Differential Input Voltage (IPx - INx) Rev 0.1.1 For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) A m p l i fy t h e H u m a n E x p e r i e n c e CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. designed by