ATMEL ATR2434-PLT Wirelessusb 2.4-ghz dsss radio soc Datasheet

Features
• 2.4-GHz Radio Transceiver
• Operates in the Unlicensed Industrial, Scientific, and Medical (ISM) Band
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(2.4 GHz to 2.483 GHz)
-95 dBm Reception Sensitivity
Up to 0 dBm Output Power
Range of up to 50 Meters or More
Data Throughput of up to 62.5 kbits/s
Highly Integrated, Low Cost, Minimal Number of External Components Required
Dual DSSS Reconfigurable Baseband Correlators
SPI Microcontroller Interface (up to 2-MHz Data Rate)
13-MHz Input Clock Operation
Low Standby Current < 1 µA
Integrated 32-bit Manufacturing ID
Operating Voltage from 2.7 V to 3.6 V
Operating Temperature from -40°C to +85°C
Offered in a Small Footprint QFN48 Package
Applications
WirelessUSB™
2.4-GHz DSSS
Radio SoC
ATR2434
• PC Human Interface Devices
– Mice
– Keyboards
– Joysticks
• Peripheral Gaming Devices
– Game Controllers
– Console Keyboards
• General
– Presenter Tools
– Remote Controls
– Consumer Electronics
– Barcode Scanners
– POS Peripherals
– Toys
Preliminary
Functional Description
The ATR2434 transceiver is a single-chip 2.4-GHz Direct Sequence Spread Spectrum
(DSSS) Gaussian Frequency Shift Keying (GFSK) baseband modem radio that connects directly to a microcontroller.
Rev. 4822C–ISM–09/04
Figure 1. Simplified Block Diagram
D IO V A L
D IO
IR Q
SS
SCK
M IS O
M OSI
D ig ita l
SERDES
A
DSSS
B aseband
A
SERDES
B
DSSS
B aseband
B
RESET
PD
GFSK
M o d u la to r
RFOUT
GFSK
D e m o d u la to r
R F IN
X13IN
X13
X13OUT
S y n th e s iz e r
Pin Configuration
NC
NC
NC
NC
X13
VCC
VCC
VCC
VCC
37
NC
48 47 46 45 44 43 42 41 40 39 38
NC
2
RFIN
Figure 2. Pinning QFN48
NC
1
36
NC
NC
2
35
X13IN
NC
3
34
PACTL
NC
4
33
PD
RFOUT
5
32
VCC
VCC
6
31
NC
30
NC
ATR2434
NC
8
29
VCC
VCC
9
28
VCC
NC
10
27
NC
NC
11
26
X13OUT
NC
12
25
SCK
MISO
MOSI
SS
DIO
DIOVAL
NC
NC
VCC
NC
21 22 23 24
RESET
13 14 15 16 17 18 19 20
IRQ
7
GND
NC
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Pin Description
Pin No.
Symbol
Type
Default
Function
46
RFIN
Input
Input
RF input. Modulated RF signal received.
5
RFOUT
Output
N/A
RF output. Modulated RF signal to be transmitted.
Analog RF
Crystal/Power Control
38
X13
Input
N/A
Crystal input (see section “Clocking and Power Management” on page 5).
35
X13IN
Input
N/A
Crystal input (see section “Clocking and Power Management” on page 5).
26
X13OUT
Output/Hi-Z
Output
System clock. Buffered 13-MHz system clock.
33
PD
Input
N/A
Power down. Asserting this input (low), will put the IC in the suspend
mode (X13OUT is 0 when PD is low).
14
RESET
Input
N/A
Active LOW reset. Device reset.
34
PACTL
I/O
Input
PACTL. External power amplifier control. Pull-down or make output.
SERDES Bypass Mode Communications/Interrupt
20
DIO
I/O
Input
Data input/output. SERDES bypass mode data transmit/receive.
19
DIOVAL
I/O
Input
Data I/O valid. SERDES bypass mode data transmit/receive valid.
21
IRQ
Output/Hi-Z
Output
IRQ. Interrupt and SERDES bypass mode DIOCLK.
SPI Communications
23
MOSI
Input
N/A
Master-output-slave-input data. SPI data input pin.
24
MISO
Output/Hi-Z
Hi-Z
Master-input-slave-output data. SPI data output pin.
25
SCK
Input
N/A
SPI input clock. SPI clock.
22
SS
Input
N/A
Slave select enable. SPI enable.
Power and Ground
6, 9, 16, 28,
29, 32, 41,
42, 44, 45
VCC
VCC
H
VCC = 2.7 V to 3.6 V.
13
GND
GND
L
Ground = 0 V.
1, 2, 3, 4, 7,
8, 10, 11,
12, 15, 17,
18, 27, 30,
31, 36, 37,
39, 40, 43,
47, 48
NC
N/A
N/A
Tie to ground.
Exposed
paddle
GND
GND
L
Must be tied to ground.
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4822C–ISM–09/04
Applications Support
The ATR2434 is supported by both the WirelessUSB Development Kit and the WirelessUSB N:1 Development Kit. The development kit provides all of the materials and
documents needed to cut the cord on multipoint to point and point to point low bandwidth high node density applications including four small form-factor sensor boards and
a hub board that connect to WirelessUSB RF module boards, comprehensive WirelessUSB protocol code examples and all of the associated schematics, gerber files and
bill of materials. The WirelessUSB N:1 Development Kit is also supported by the WirelessUSB Listener Tool.
Functional Overview
The ATR2434 provides a complete WirelessUSB SPI to antenna radio modem. The
ATR2434 is designed to implement wireless devices operating in the worldwide 2.4-GHz
Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz to 2.4835 GHz). It
is intended for systems compliant with world-wide regulations covered by
ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries);
FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB STD-T66 (Japan).
The ATR2434 contains a 2.4-GHz radio transceiver, a GFSK modem and a dual DSSS
reconfigurable baseband. The radio and baseband are both code- and frequency-agile.
Forty-nine spreading codes selected for optimal performance (Gold codes) are supported across 78 1-MHz channels yielding a theoretical spectral capacity of 3822
channels. The ATR2434 supports a range of up to 50 meters or more.
2.4-GHz Radio
The receiver and transmitter are a single-conversion low-Intermediate Frequency
(low-IF) architecture with fully integrated IF channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides
an output power control range of 30 dB in seven steps.
Both the receiver and transmitter integrated Voltage Controlled Oscillator (VCO) and
synthesizer have the agility to cover the complete 2.4-GHz GFSK radio transmitter ISM
band. The VCO loop filter is also integrated on-chip.
GFSK Modem
The transmitter uses a DSP-based vector modulator to convert the 1-MHz chips to an
accurate GFSK carrier.
The receiver uses a fully integrated Frequency Modulator (FM) detector with automatic
data slicer to demodulate the GFSK signal.
Dual DSSS Baseband
Data is converted to DSSS chips by a digital spreader. De-spreading is performed by an
oversampled correlator. The DSSS baseband cancels spurious noise and assembles
properly correlated data bytes.
The DSSS baseband has four operating modes: 64 chips/bit single channel, 32 chips/bit
dual channel, 32 chips/bit single channel 2 × oversampled, and 32 chips/bit single
channel Dual Data Rate (DDR).
64 Chips/Bit Single Channel
4
The baseband supports a single data stream operating at 15.625 kbits/s. The advantage
of selecting this mode is its ability to tolerate a noisy environment. This is because the
15.625 kbits/s data stream utilizes the longest PN code resulting in the highest probability for recovering packets over the air. This mode can also be selected for systems
requiring data transmissions over longer ranges.
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
32 Chips/Bit Dual Channel
The baseband supports two non-simultaneous data streams each operating at
31.25 kbits/s.
32 Chips/Bit Single Channel
2 × Oversampled
The baseband supports a single data stream operating at 31.25 kbits/s that is sampled
twice as much as the other modes. The advantage of selecting this mode is its ability to
tolerate a noisy environment.
32 Chips/Bit Single Channel
Dual Data Rate (DDR)
The baseband spreads bits in pairs and supports a single data stream operating at
62.5 kbits/s.
Serializer/Deserializer
(SERDES)
The ATR2434 provides a data Serializer/Deserializer (SERDES), which provides
byte-level framing of transmit and receive data. Bytes for transmission are loaded into
the SERDES and receive bytes are read from the SERDES via the SPI interface. The
SERDES provides double buffering of transmit and receive data. While one byte is
being transmitted by the radio the next byte can be written to the SERDES data register
insuring there are no breaks in transmitted data.
After a receive byte has been received it is loaded into the SERDES data register and
can be read at any time until the next byte is received, at which time the old contents of
the SERDES data register will be overwritten.
Application Interfaces
The ATR2434 has a fully synchronous SPI slave interface for connectivity to the application MCU. Configuration and byte-oriented data transfer can be performed over this
interface. An interrupt is provided to trigger real time events.
An optional SERDES Bypass mode (DIO) is provided for applications that require a synchronous serial bit-oriented data path. This interface is for data only.
Clocking and Power
Management
A 13-MHz crystal is directly connected to X13IN and X13 without the need for external
capacitors. The ATR2434 has a programmable trim capability for adjusting the on-chip
load capacitance supplied to the crystal. The Radio Frequency (RF) circuitry has onchip decoupling capacitors. The ATR2434 is powered from a 2.7 V to 3.6 V DC supply.
The ATR2434 can be shutdown to a fully static state using the PD pin.
Below are the requirements for the crystal to be directly connected to X13IN and X13:
•
Nominal frequency: 13 MHz
•
Operating mode: fundamental mode
•
Resonance mode: parallel resonant
•
Frequency stability: ±30 ppm
•
Series resistance: ≤ 100 Ω
•
Load capacitance: 10 pF
•
Drive level: 10 µW to 100 µW
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4822C–ISM–09/04
Receive Signal Strength
Indicator (RSSI)
The RSSI register (Reg 0x22) returns the relative signal strength of the ON-channel
signal power and can be used to:
1. determine the connection quality,
2. determine the value of the noise floor, and
3. check for a quiet channel before transmitting.
The internal RSSI voltage is sampled through a 5-bit Analog-to-Digital Converter (ADC).
A state machine controls the conversion process. Under normal conditions, the RSSI
state machine initiates a conversion when an ON-channel carrier is detected and
remains above the noise floor for over 50 µs. The conversion produces a 5-bit value in
the RSSI register (Reg 0x22, bits 4:0) along with a valid bit, RSSI register
(Reg 0x22, bit 5). The state machine then remains in HALT mode and does not reset for
a new conversion until the receive mode is toggled off and on. Once a connection has
been established, the RSSI register can be read to determine the relative connection
quality of the channel. A RSSI register value lower than 10 indicates that the received
signal strength is low, a value greater than 28 indicates a strong signal level.
To check for a quiet channel before transmitting, first set up the receive mode properly
and read the RSSI register (Reg 0x22). If the valid bit is zero, then force the Carrier
Detect register (Reg 0x2F, bit 7 = 1) to initiate an ADC conversion. Then, wait a minimum of 50 µs and read the RSSI register again. Next, clear the Carrier Detect register
(Reg 0x2F, bit 7 = 0) and turn the receiver OFF. Measuring the noise floor of a quiet
channel is inherently a noisy process so, for best results, this procedure should be
repeated several times (~20) to compute an average noise floor level. A RSSI register
value of 0-10 indicates a channel that is relatively quiet. A RSSI register value greater
than 10 indicates the channel is probably being used. A RSSI register value greater than
28 indicates the presence of a strong signal.
Application Interfaces
SPI Interface
The ATR2434 has a four-wire SPI communication interface between an application
MCU and one or more slave devices. The SPI interface supports single-byte and multibyte serial transfers. The four-wire SPI communications interface consists of Master
Out-Slave In (MOSI), Master In-Slave Out (MISO), Serial Clock (SCK), and Slave Select
(SS).
The SPI receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the
MISO pin. The active-low Slave Select (SS) pin must be asserted to initiate an SPI
transfer.
The application MCU can initiate an SPI data transfer via a multi-byte transaction. The
first byte is the Command/Address byte, and the following bytes are the data bytes as
shown in Table 1 on page 7 and Figure 3 through Figure 5 on page 7. The SS signal
should not be deasserted between bytes. The SPI communications is as follows:
6
•
Command direction (bit 7) = 0 enables SPI read transaction. A 1 enables SPI write
transactions.
•
Command increment (bit 6) = 1 enables SPI auto address increment. When set, the
address field automatically increments at the end of each data byte in a burst
access, otherwise the same address is accessed.
•
Six bits of address.
•
Eight bits of data.
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
The SPI communications interface has a burst mechanism, where the command byte
can be followed by as many data bytes as desired. A burst transaction is terminated by
deasserting the slave select (SS = 1).
The SPI communications interface single read and burst read sequences are shown in
Figure 3 and Figure 4, respectively.
The SPI communications interface single write and burst write sequences are shown in
Figure 5 and Figure 6 on page 8, respectively.
Table 1. SPI Transaction Format
Byte 1
Bit #
Bit Name
Byte 1 + N
7
6
[5:0]
[7:0]
DIR
INC
Address
Data
Figure 3. SPI Single Read Sequence
SCK
SS
cm d
M OSI
D IR
0
IN C
0
addr
A5
A4
A3
A2
A1
A0
d a ta to m c u
M IS O
D7
D6
D7
D6
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
Figure 4. SPI Burst Read Sequence
SCK
SS
cm d
MOSI
D IR
0
addr
IN C
1
A5
A4
A3
A2
A1
A0
d a ta to m c u
M IS O
D5
D4
D3
D2
d a ta to m c u
1
D7
D6
D5
D4
D3
D2
1+N
D1
D0
Figure 5. SPI Single Write Sequence
SCK
SS
cm d
M OS I
DIR
1
INC
0
addr
A5
A4
A3
A2
data from m cu
A1
A0
D5
D4
D3
D2
D1
D0
M ISO
7
4822C–ISM–09/04
Figure 6. SPI Burst Write Sequence
SCK
SS
cm d
M OSI
D IR
a d dr
da ta from m cu
d a ta fro m m cu
1
1 +N
IN C
1
1
A5
A4
A3
A2
A1
A0
D7
D5
D6
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
M IS O
DIO Interface
The DIO communications interface is an optional SERDES bypass data-only transfer
interface. In receive mode, DIO and DIOVAL are valid after the falling edge of IRQ,
which clocks the data as shown in Figure 7. In transmit mode, DIO and DIOVAL are
sampled on the falling edge of the IRQ, which clocks the data as shown in Figure 8. The
application MCU samples the DIO and DIOVAL on the rising edge of IRQ.
Figure 7. DIO Receive Sequence
IRQ
DIOVAL
v0
v1
v2
v3
v4
v5
v6
v7
v8
v9
v10
v11
v12
v13
v14
v...
d10
d11
d12
d13
d14
d...
data to mcu
DIO
d0
d1
d2
d3
d4
d5
d6
d8
d7
d9
Figure 8. DIO Transmit Sequence
IRQ
DIOVAL
v0
v1
v2
v3
v4
v5
v6
v7
v8
v9
v10
v11
v12
v13
v14
v...
d11
d12
d13
d14
d...
data from mcu
DIO
8
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Interrupts
The ATR2434 features three sets of interrupts: transmit, receive, and a wake interrupt.
These interrupts all share a single pin (IRQ), but can be independently enabled/
disabled. In transmit mode, all receive interrupts are automatically disabled, and in
transmit mode all receive interrupts are automatically disabled. However, the contents of
the enable registers are preserved when switching between transmit and receive
modes.
Interrupts are enabled and the status reads through 6 registers: Receive Interrupt
Enable (Reg 0x07), Receive Interrupt Status (Reg 0x08), Transmit Interrupt Enable
(Reg 0x0D), Transmit Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).
If more than 1 interrupt is enabled at any time, it is necessary to read the relevant interrupt status register to determine which event caused the IRQ pin to assert. Even when a
given interrupt source is disabled, the status of the condition that would otherwise cause
an interrupt can be determined by reading the appropriate interrupt status register. It is
therefore possible to use the devices without making use of the IRQ pin at all. Firmware
can poll the interrupt status register(s) to wait for an event, rather than using the IRQ
pin.
The polarity of all interrupts can be set by writing to the Configuration register
(Reg 0x05), and it is possible to configure the IRQ pin to be open drain (if active low) or
open source (if active high).
Wake Interrupt
When the PD pin is low, the oscillator is stopped. After PD is deasserted, the oscillator
takes time to start, and until it has done so, it is not safe to use the SPI interface. The
wake interrupt indicates that the oscillator has started, and that the device is ready to
receive SPI transfers.
The wake interrupt is enabled by setting bit 0 of the Wake Enable register (Reg 0x1C,
bit 0 = 1). Whether or not a wake interrupt is pending is indicated by the state of bit 0 of
the Wake Status register (Reg 0x1D, bit 0). Reading the Wake Status register
(Reg 0x1D) clears the interrupt.
Transmit Interrupts
Four interrupts are provided to flag the occurrence of transmit events. The interrupts are
enabled by writing to the Transmit Interrupt Enable register (Reg 0x0D), and their status
may be determined by reading the Transmit Interrupt Status register (Reg 0x0E). If more
than 1 interrupt is enabled, it is necessary to read the Transmit Interrupt Status register
(Reg 0x0E) to determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in detail in the section
“Register Descriptions” on page 10.
Receive Interrupts
Eight interrupts are provided to flag the occurrence of receive events, four each for
SERDES A and B. In 64 chips/bit and 32 chips/bit DDR modes, only the SERDES A
interrupts are available, and the SERDES B interrupts will never trigger, even if enabled.
The interrupts are enabled by writing to the Receive Interrupt Enable register
(Reg 0x07), and their status may be determined by reading the Receive Interrupt Status
register (Reg 0x08). If more than one interrupt is enabled, it is necessary to read the
Receive Interrupt Status register (Reg 0x08) to determine which event caused the IRQ
pin to assert.
The function and operation of these interrupts are described in detail in the section
“Register Descriptions” on page 10.
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4822C–ISM–09/04
Register
Descriptions
Table 2 displays the list of registers inside the ATR2434 that are addressable through
the SPI interface. All registers are read and writable, except where noted.
Table 2. Register Map(1)
Register Name
Mnemonic
Address
Default
Access
Revision ID
REG_ID
0x00
0x07
RO
Synthesizer A Counter
REG_SYN_A_CNT
0x01
0x00
RW
Synthesizer N Counter
REG_SYN_N_CNT
0x02
0x00
RW
Control
REG_CONTROL
0x03
0x00
RW
Data Rate
REG_DATA_RATE
0x04
0x00
RW
Configuration
REG_CONFIG
0x05
0x01
RW
SERDES Control
REG_SERDES_CTL
0x06
0x03
RW
Receive Interrupt Enable
REG_RX_INT_EN
0x07
0x00
RW
Receive Interrupt Status
REG_RX_INT_STAT
0x08
0x00
RO
Receive Data A
REG_RX_DATA_A
0x09
0x00
RO
Receive Valid A
REG_RX_VALID_A
0x0A
0x00
RO
Receive Data B
REG_RX_DATA_B
0x0B
0x00
RO
Receive Valid B
REG_RX_VALID_B
0x0C
0x00
RO
Transmit Interrupt Enable
REG_TX_INT_EN
0x0D
0x00
RW
Transmit Interrupt Status
REG_TX_INT_STAT
0x0E
0x00
RO
Transmit Data
REG_TX_DATA
0x0F
0x00
RW
Transmit Valid
REG_TX_VALID
0x10
0x00
RW
PN Code
REG_PN_CODE
0x11-0x18
0x1E8B6A3DE0E9B222
RW
Threshold Low
REG_THRESHOLD_L
0x19
0x08
RW
Threshold High
REG_THRESHOLD_H
0x1A
0x38
RW
Wake Enable
REG_WAKE_EN
0x1C
0x00
RW
Wake Status
REG_WAKE_STAT
0x1D
0x01
RO
Analog Control
REG_ANALOG_CTL
0x20
0x04
RW
Channel
REG_CHANNEL
0x21
0x00
RW
Receive Signal Strength Indicator
REG_RSSI
0x22
0x00
RO
Power Control
REG_PA
0x23
0x00
RW
Crystal Adjust
REG_CRYSTAL_ADJ
0x24
0x00
RW
VCO Calibration
REG_VCO_CAL
0x26
0x00
RW
AGC Control
REG_AGC_CTL
0x2E
0x00
RW
Carrier Detect
REG_CARRIER_DETECT
0x2F
0x00
RW
Clock Manual
REG_CLOCK_MANUAL
0x32
0x00
RW
Clock Enable
REG_CLOCK_ENABLE
0x33
0x00
RW
Synthesizer Lock Count
REG_SYN_LOCK_CNT
0x38
0x64
RW
Manufacturing ID
REG_MID
0x3C-0x3F
-
RO
Note:
10
1. All registers are accessed Little Endian.
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Table 3. Revision ID Register
Addr: 0x00
7
REG_ID
6
5
4
Default: 0x07
3
2
Silicon ID
1
0
Product ID
Bit
Name
Description
7:4
Silicon ID
These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only.
3:0
Product ID
These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.
Table 4. Synthesizer A Counter
Addr: 0x01
7
REG_SYN_A_CNT
6
5
4
3
Reserved
Default: 0x00
2
1
0
Count
Bit
Name
Description
7:5
Reserved
These bits are reserved and should be written with zeros.
4:0
Count
The Synthesizer A Counter register is used for diagnostic purposes and is not recommended for normal
operation. The Channel register is the recommended method of setting the Synthesizer frequency.
The Synthesizer A Count along with the Synthesizer N Count can be used to generate the Synthesizer frequency.
The range of valid values of the Synthesizer A Count is 0 through 31. Using the Synthesizer A and N Count
register is an alternative to using the Channel register. Selection between the use of the Channel register or the A
and N registers is done through the Channel register (Reg 0x21, bit 7). When in Channel mode the A and N Count
bits can be used to read the A and N values derived directly from the Channel.
Table 5. Synthesizer N Counter
Addr: 0x02
7
REG_SYN_N_CNT
6
5
4
Reserved
3
Default: 0x00
2
1
0
Count
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6:0
Count
The Synthesizer N Counter register is used for diagnostic purposes and therefore is not recommended for normal
operation. The Channel register is the recommended method of setting the Synthesizer frequency.
The Synthesizer N Count along with the Synthesizer A Count can be used to generate the Synthesizer frequency.
The range of valid values of the Synthesizer N Count is 74 through 76. Using the Synthesizer A and N Count
register is an alternative to using the Channel register. Selection between the use of the Channel register or the A
and N registers is done through the Channel register (Reg 0x21, bit 7). When in Channel mode the A and N
Count bits can be used to read the A and N values derived directly from the Channel.
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4822C–ISM–09/04
Table 6. Control
Addr: 0x03
REG_CONTROL
Default: 0x00
7
6
5
4
3
2
1
0
RX
Enable
TX
Enable
PN Code
Select
Auto Syn
Count Select
Auto PA
Disable
PA Enable
Auto Syn
Disable
Syn Enable
Bit
Name
Description
7
RX Enable
The Receive Enable bit is used to place the IC in receive mode.
1 = Receive Enabled
0 = Receive Disabled
6
TX Enable
The Transmit Enable bit is used to place the IC in transmit mode.
1 = Transmit Enabled
0 = Transmit Disabled
5
PN Code
Select
The Pseudo-noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code.
1 = 32 Most Significant Bits of PN code are used
0 = 32 Least Significant Bits of PN code are used
This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2 = 1).
4
Auto Syn
Count Select
The Auto Synthesizer Count Select bit is used to select the method of determining the settle time of the
synthesizer. The two options are a programmable settle time based on the value in the Syn Lock Count
register (Reg 0x38), in units of 2 µs, or by the auto detection of the synthesizer lock.
1 = Synthesizer settle time is based on a count in the Syn Lock Count register (Reg 0x38)
0 = Synthesizer settle time is based on the internal synthesizer lock signal
It is recommended that the Auto Syn Count Select bit is set to 1 as that guarantees a consistent settle time for
the synthesizer.
3
Auto PA
Disable
The Auto Power Amplifier Disable bit is used to determine the method of controlling the Power Amplifier. The
two options are automatically controlled by the baseband or by firmware through register writes.
1 = Register controlled PA Enable.
0 = Auto PA Enable
When this bit is set to 1 the state of the PA enable is directly controlled by bit PA Enable (Reg 0x03, bit 2). It is
recommended that this bit is set to 0 leaving the PA control to the baseband.
2
PA Enable
The PA Enable bit is used to enable or disable the Power Amplifier.
1 = Power Amplifier Enabled
0 = Power Amplifier Disabled
This bit only applies when the Auto PA Disable bit is selected (Reg 0x03, bit 3 = 1), otherwise this bit is do not
care.
1
Auto Syn
Disable
The Auto Synthesizer Disable bit is used to determine the method of controlling the Synthesizer. The two
options are automatic control by the baseband or by firmware through register writes.
1 = Register controlled Synthesizer Enable
0 = Auto Synthesizer Enable
When this bit is set to 1 the state of the Synthesizer is directly controlled by bit Syn Enable (Reg 0x03, bit 0).
When this bit is set to 0 the state of the Synthesizer is controlled by the Auto Syn Count Select bit (Reg 0x03,
bit 4). It is recommended that this bit be set to 0 leaving the Synthesizer control to the baseband.
0
Syn Enable
The Synthesizer Enable bit is used to enable or disable the Synthesizer.
1 = Synthesizer Enabled
0 = Synthesizer Disabled
This bit only applies when Auto Syn Disable bit is selected (Reg 0x03, bit 1 = 1), otherwise this bit is do not
care.
12
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Table 7. Data Rate
Addr: 0x04
7
REG_DATA_RATE
6
5
4
3
Reserved
Default: 0x00
2
1
0
Code Width
Data Rate
Sample Rate
Bit
Name
Description
7:3
Reserved
These bits are reserved and should be written with zeros.
Code
Width
The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.
1 = 32 chips/bit PN codes
0 = 64 chips/bit PN codes
The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to
interference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled
(when double data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as
well as more robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register
bits are impacted and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg
0x04, bit 1), and Sample Rate (Reg 0x04, bit 0).
1(1)
Data Rate
The Data Rate bit allows the user to select a Double Data Rate mode of operation which delivers a raw data rate
of 62.5 kbits/sec.
1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)
0 = Normal Data Rate - 1 bit per PN code
This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit
(Reg 0x04, bit 2 = 1). When using the Double Data Rate, the raw data throughput is 62.5 kbits/s because every
32 chips/bit PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is
placed in the PN code register. This 64 chips/bit PN code is then split into two and used by the baseband to
offer the Double Data Rate capability. When using the Normal Data Rate, the raw data throughput is
32 kbits/sec. Additionally, Normal Data Rate enables the user to potentially correlate data using two differing 32
chips/bit PN codes.
0(1)
Sample
Rate
The Sample Rate bit allows the use of the 12 ×sampling when using 32 chips/bit PN codes and the Normal Data
Rate.
1 = 12 × Oversampling
0 = 6 × Oversampling
Using 12 × oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or the
Double Data Rate this bit is do not care. When in the Normal Data Rate setting and choosing 12 ×
oversampling, eliminates the ability to receive from two different PN codes. Therefore the only time when 12 ×
oversampling is to be selected is when a 32 chips/bit PN code is being used and there is no need to receive
data from sources with two different PN codes.
2
(1)
Note:
1. The following Reg 0x04, bits 2:0 values are not valid:
· 001-Not Valid
· 010-Not Valid
· 011-Not Valid
· 111-Not Valid
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4822C–ISM–09/04
Table 8. Configuration
Addr: 0x05
7
REG_CONFIG
6
5
Reserved
Bit
Default: 0x01
4
3
2
Receive
Invert
Transmit
Invert
Reserved
1
0
IRQ Pin Select
Name
Description
7:5
Reserved
These bits are reserved and should be written with zeros.
4
Receive
Invert
The Receive Invert bit is used to invert the received data.
1 = Inverted over-the-air Receive data
0 = Non-inverted over-the-air Receive data
3
Transmit
Invert
The Transmit Invert bit is used to invert the data that is to be transmitted.
1 = Inverted Transmit Data
0 = Non-inverted Transmit Data
2
Reserved
This bit is reserved and should be written with zero.
1:0
IRQ Pin
Select
The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.
11 = Open Drain (asserted = 0, deasserted = Hi-Z)
10 = Open Source (asserted = 1, deasserted = Hi-Z)
01 = CMOS (asserted = 1, deasserted = 0)
00 = CMOS Inverted (asserted = 0, deasserted = 1)
Table 9. SERDES Control
Addr: 0x06
7
REG_SERDES_CTL
6
5
4
3
Default: 0x03
2
SERDES
Enable
Reserved
1
0
EOF Length
Bit
Name
Description
7:4
Reserved
These bits are reserved and should be written with zeros.
3
SERDES
Enable
The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.
1 = SERDES enabled
0 = SERDES disabled, bit-serial mode enabled
When the SERDES is enabled data can be written to and read from the IC one byte at a time through the use
of the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the
use of the DIO/DIOVAL pins. It is recommended that the SERDES mode be used to avoid the need to
manage the timing required by the bit-serial mode.
2:0
EOF Length
The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap
without valid data before an EOF event is generated. When in receive mode and a valid bit has been received
the EOF event can then be identified by the number of bit times that expire without correlating any new data.
The EOF event causes data to be moved to the proper SERDES Data Register and can also be used to
generate interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid
reception.
Table 10. Receive Interrupt Enable
Addr: 0x07
REG_RX_INT_EN
Default: 0x00
7
6
5
4
3
2
1
0
Underflow B
Overflow B
EOF B
Full B
Underflow A
Overflow A
EOF A
Full A
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ATR2434 [Preliminary]
Bit
Name
Description
7
Underflow B
The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B)
when it is empty.
6
Overflow B
The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Overflow B interrupt enabled for Receive SERDES Data B
0 = Overflow B interrupt disabled for Receive SERDES Data B
An overflow condition occurs when new received data is written into the Receive SERDES Data B register
(Reg 0x0B) before the prior data is read out.
5
EOF B
The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.
1 = EOF B interrupt enabled for Channel B Receiver
0 = EOF B interrupt disabled for Channel B Receiver
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length
field. If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ
is cleared by reading the receive status register
4
Full B
The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B)
having data placed in it.
1 = Full B interrupt enabled for Receive SERDES Data B
0 = Full B interrupt disabled for Receive SERDES Data B
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES
Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs
whether or not a complete byte has been received.
3
Underflow A
The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data A register (Reg 0x09)
1 = Underflow A interrupt enabled for Receive SERDES Data A
0 = Underflow A interrupt disabled for Receive SERDES Data A
An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09)
when it is empty.
2
Overflow A
The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data A register (0x09)
1 = Overflow A interrupt enabled for Receive SERDES Data A
0 = Overflow A interrupt disabled for Receive SERDES Data A
An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg
0x09) before the prior data is read out.
1
EOF A
The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the
Channel A Receiver.
1 = EOF A interrupt enabled for Channel A Receiver
0 = EOF A interrupt disabled for Channel A Receiver
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field.
If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is
cleared by reading the receive status register.
0
Full A
The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09)
having data written into it.
1 = Full A interrupt enabled for Receive SERDES Data A
0 = Full A interrupt disabled for Receive SERDES Data A
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES
Data A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs
whether or not a complete byte has been received.
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4822C–ISM–09/04
Table 11. Receive Interrupt Status
Addr: 0x08
REG_RX_INT_STAT
Default: 0x00
7
6
5
4
3
2
1
0
Valid B
Flow Violation B
EOF B
Full B
Valid A
Flow Violation A
EOF A
Full A
Note:
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example,
the receive status will read 0 if the IC is not in receive mode. These register are read-only.
Bit
Name
Description
7
Valid B
The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.
1 = All bits are valid for Receive SERDES Data B
0 = Not all bits are valid for Receive SERDES Data B
When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within
the byte that has been written are valid. This bit cannot generate an interrupt.
6
Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the
Receive SERDES Data B register (Reg 0x0B).
1 = Overflow/underflow interrupt pending for Receive SERDES Data B
0 = No overflow/underflow interrupt pending for Receive SERDES Data B
Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B)
before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data
B register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status
register (Reg 0x08)
5
EOF B
The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive.
1 = EOF interrupt pending for Channel B
0 = No EOF interrupt pending for Channel B
An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times
specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is
cleared by reading the Receive Interrupt Status register (Reg 0x08)
4
Full B
The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data.
1 = Receive SERDES Data B full interrupt pending
0 = No Receive SERDES Data B full interrupt pending
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data
B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
3
Valid A
The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid.
1 = All bits are valid for Receive SERDES Data A
0 = Not all bits are valid for Receive SERDES Data A
When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within
the byte that has been written are valid. This bit cannot generate an interrupt.
2
Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the
Receive SERDES Data A register (Reg 0x09).
1 = Overflow/underflow interrupt pending for Receive SERDES Data A
0 = No overflow/underflow interrupt pending for Receive SERDES Data A
Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09)
before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data
A register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status
register (Reg 0x08)
16
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
1
EOF A
The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive.
1 = EOF interrupt pending for Channel A
0 = No EOF interrupt pending for Channel A
An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times
specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared
by reading the Receive Interrupt Status register (Reg 0x08).
0
Full A
The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data.
1 = Receive SERDES Data A full interrupt pending
0 = No Receive SERDES Data A full interrupt pending
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data
A Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs
whether or not a complete byte has been received.
Table 12. Receive SERDES Data A
Addr: 0x09
7
REG_RX_DATA_A
6
5
4
3
Default: 0x00
2
1
0
Data
Bit
Name
Description
7:0
Data
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by
bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Table 13. Receive SERDES Valid A
Addr: 0x0A
7
REG_RX_VALID_A
6
5
4
3
Default: 0x00
2
1
0
Valid
Bit
Name
Description
7:0
Valid
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that
the corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES
Data A register (Reg 0x09) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg
0x0A). The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4,
followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Table 14. Receive SERDES Data B
Addr: 0x0B
7
REG_RX_DATA_B
6
5
4
3
Default: 0x00
2
1
0
Data
Bit
Name
Description
7:0
Data
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit
3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
17
4822C–ISM–09/04
Table 15. Receive SERDES Valid B
Addr: 0x0C
7
REG_RX_VALID_B
6
5
4
3
Default: 0x00
2
1
0
Valid
Bit
Name
Description
7:0
Valid
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates
that the corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES
Data B register (Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register
(Reg 0x0C).The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed
by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Table 16. Transmit Interrupt Enable
Addr: 0x0D
7
REG_TX_INT_EN
6
5
4
Reserved
Default: 0x00
3
2
1
0
Underflow
Overflow
Done
Empty
Bit
Name
Description
7:4
Reserved
These bits are reserved and should be written with zeros.
3
Underflow
The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the
Transmit SERDES Data register (Reg 0x0F)
1 = Underflow interrupt enabled
0 = Underflow interrupt disabled
An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F)
does not have any data.
2
Overflow
The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit
SERDES Data register (0x0F).
1 = Overflow interrupt enabled
0 = Overflow interrupt disabled
An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg
0x0F) before the preceding data has been transferred to the transmit shift register.
1
Done
The Done bit is used to enable the interrupt that signals the end of the transmission of data.
1 = Done interrupt enabled
0 = Done interrupt disabled
The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data
and there is no more data for it to transmit.
0
Empty
The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is
empty.
1 = Empty interrupt enabled
0 = Empty interrupt disabled
The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit
buffer and it's safe to load the next byte
18
ATR2434 [Preliminary]
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ATR2434 [Preliminary]
Table 17. Transmit Interrupt Status
Addr: 0x0E
7
REG_TX_INT_STAT
6
5
Reserved
Note:
4
Default: 0x00
3
2
1
0
Underflow
Overflow
Done
Empty
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For
example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only.
Bit
Name
Description
7:4
Reserved
These bits are reserved. This register is read-only.
3
Underflow
The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data
register (Reg 0x0F) has occurred.
1 = Underflow Interrupt pending
0 = No Underflow Interrupt pending
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An
underflow occurs when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit
SERDES Data register (Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This
bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
2
Overflow
The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data
register (0x0F) has occurred.
1 = Overflow Interrupt pending
0 = No Overflow Interrupt pending
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow
occurs when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous
data has been sent. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
1
Done
The Done bit is used to signal the end of a data transmission.
1 = Done Interrupt pending
0 = No Done Interrupt pending
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This
will only assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit
Interrupt Status register (Reg 0x0E)
0
Empty
The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.
1 = Empty Interrupt pending
0 = No Empty Interrupt pending
This IRQ will assert when the transmit SERDES is empty. When this IRQ is asserted it is ok to write to the
Transmit SERDES Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear
this IRQ. It will be set when the data is loaded into the transmitter, and it is ok to write new data.
Note:
1. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be
implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6).
For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only.
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4822C–ISM–09/04
Table 18. Transmit SERDES Data
Addr: 0x0F
7
REG_TX_DATA
6
5
4
Default: 0x00
3
2
1
0
Data
Bit
Name
Description
7:0
Data
Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed
by bit 4, followed by bit 5, followed by bit 6, followed by bit 7.
Table 19. Transmit SERDES Valid
Addr: 0x10
REG_TX_VALID
7
6
5
4
Default: 0x00
3
2
1
0
Valid
Bit
Name
7:0
Valid
Note:
(1)
Description
The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid.
1 = Valid transmit bit
0 = Invalid transmit bit
1. The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the data byte. Data is sent LSB first. The SERDES will continue to send data until there are
no more VALID bits in the shifter. For example, writing 0x0F to the Transmit SERDES Valid register (Reg 0x10) will send
half a byte.
Table 20. PN Code
Addr: 0x11-18
Default:
0x1E8B6A3DE0E9B222
REG_PN_CODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Address 0x18
31
30
29 28 27 26
Address 0x14
Address 0x17
25
24 23
22
21 20 19 18
Address 0x13
Address 0x16
17
16
15
14
13 12 11 10
Address 0x12
Address 0x15
9
8
7
6
5
4
3
2
Address 0x11
1
0
Bit
Name
Description
63:0
PN Codes
The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes
can be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32
chips/bit PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64
chips/bit value can be used as a PN code as there are certain characteristics that are needed to minimize the
possibility of multiple PN codes interfering with each other or the possibility of invalid correlation. The over-the-air
order is bit 0 followed by bit 1, followed by bit 62, followed by bit 63.
20
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4822C–ISM–09/04
ATR2434 [Preliminary]
Table 21. Threshold Low
Addr: 0x19
7
REG_THRESHOLD_L
6
5
4
Reserved
3
Default: 0x08
2
1
0
Threshold Low
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6:0
Threshold Low
The Threshold Low value is used to determine the number of missed chips allowed when attempting to
correlate a single data bit of value 0. A perfect reception of a data bit of 0 with a 64 chips/bit PN code would
result in zero correlation matches, meaning the exact inverse of the PN code has been received. By setting
the Threshold Low value to 0x08 for example, up to eight chips can be erroneous while still identifying the
value of the received data bit. This value along with the Threshold High value determine the correlator count
values for logic 1 and logic 0. The threshold values used determine the sensitivity of the receiver to
interference and the dependability of the received data. By allowing a minimal number of erroneous chips the
dependability of the received data increases while the robustness to interference decreases. On the other
hand increasing the maximum number of missed chips means reduced data integrity but increased
robustness to interference and increased range.
Table 22. Threshold High
Addr: 0x1A
7
REG_THRESHOLD_H
6
5
Reserved
4
3
Default: 0x38
2
1
0
Threshold High
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6:0
Threshold High
The Threshold High value is used to determine the number of matched chips allowed when attempting to
correlate a single data bit of value 1. A perfect reception of a data bit of 1 with a 64 chips/bit or a 32 chips/bit
PN code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was
received perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be
erroneous while still identifying the value of the received data bit. This value along with the Threshold Low
value determine the correlator count values for logic 1 and logic 0. The threshold values used determine the
sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal
number of erroneous chips the dependability of the received data increases while the robustness to
interference decreases. On the other hand increasing the maximum number of missed chips means reduced
data integrity but increased robustness to interference and increased range.
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4822C–ISM–09/04
Table 23. Wake Enable
Addr: 0x1C
7
REG_WAKE_EN
6
5
4
3
Default: 0x00
2
1
0
Wake-up
Enable
Reserved
Bit
Name
Description
7:1
Reserved
These bits are reserved and should be written with zeros.
0
Wake-up
Enable
Wake-up interrupt enable.
0 = Disabled
1 = Enabled
A wake-up event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI
communications.
Table 24. Wake Status
Addr: 0x1D
7
REG_WAKE_STAT
6
5
4
3
Reserved
Default: 0x01
2
1
0
Wake-up Status
Bit
Name
Description
7:1
Reserved
These bits are reserved. This register is read-only.
0
Wake-up
Status
Wake-up status.
0 = Wake interrupt not pending
1 = Wake interrupt pending
This IRQ will assert when a wake-up condition occurs. This bit is cleared by reading the Wake Status register
(Reg 0x1D). This register is read-only.
22
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Table 25. Analog Control
Addr: 0x20
REG_ANALOG_CTL
Default: 0x00
7
6
5
4
3
2
1
0
Reserved
AGC Disable
MID Read
Enable
Reserved
Reserved
PA Output
Enable
PaInv
Rst
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6
AGC RSSI
Control
Enables AGC/RSSI control via Reg 0x2E and Reg 0x2F.
5
MID Read
Enable
The MID Read Enable bit must be set to read the contents of the Manufacturing ID register
(Reg 0x3C-0x3F). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should
only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
4:3
Reserved
These bits are reserved and should be written with zeros.
2
PA Output
Enable
The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power
amplifier.
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
1
PA Invert
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set
high. PA Output Enable and PA Invert cannot be simultaneously changed.
1 = PACTL active low
0 = PACTL active high
0
Reset
The Reset bit is used to generate a self clearing device reset.
1 = Device Reset. All registers are restored to their default values
0 = No Device Reset
Table 26. Channel
Addr: 0x21
7
REG_CHANNEL
6
5
A+N
4
3
Default: 0x00
2
1
0
Channel
Bit
Name
Description
7
A+N
The A+N bit is used to specify whether the Synthesizer frequency is generated through the use of the
Channel register (Reg 0x21) or through the use of the Synthesizer A Counter register (Reg 0x01) and the
Synthesizer N Counter register (Reg 0x02).
1 = Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) registers
used to generate Synthesizer frequency
0 = Channel register (Reg 0x21) is used to generate Synthesizer frequency
When set to 1 the channel value is ignored and the values written in the Synthesizer A Counter register (Reg
0x01) and the Synthesizer N Counter register (Reg 0x02) are used. When set to 0 the values written to the
Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) are ignored
and the channel value is used by the synthesizer. It is recommended that the Channel register (Reg 0x21) is
used as opposed to the Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register
(Reg 0x02) method.
6:0
Channel
The Channel register (Reg 0x21) is used to determine the Synthesizer frequency when the A+N bit is set to
0. Use of other channels may be restricted by certain regulatory agencies. A value of 1 corresponds to a
communication frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The
channels are separated from each other by 1 MHz intervals.
23
4822C–ISM–09/04
Table 27. Receive Signal Strength Indicator (RSSI)
Addr: 0x22
7
REG_RSSI
6
5
Reserved
Note:
4
Default: 0x00
3
2
Valid
1
0
RSSI
The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7 = 1).
Bit
Name
Description
7:6
Reserved
These bits are reserved. This register is read-only.
5
Valid
The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is read only.
1 = RSSI value is valid
0 = RSSI value is invalid
4:0
RSSI
The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a
read only value with the higher values indicating stronger received signals meaning more reliable
transmissions.
Table 28. Power Control
Addr: 0x23
7
REG_PA
6
5
4
Default: 0x00
3
2
Reserved
1
0
PA Bias
Bit
Name
Description
7:3
Reserved
These bits are reserved and should be written with zeros.
2:0
PA Bias
The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing
(values up to 7) or decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the
register value the higher the transmit power. By changing the PA Bias value signal strength management
functions can be accomplished. For general purpose communication a value of 7 is recommended.
Table 29. Crystal Adjust
Addr: 0x24
REG_CRYSTAL_ADJ
7
6
5
Reserved
Clock Output
Disable
4
3
Default: 0x00
2
1
0
Crystal Adjust
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6
Clock Output
Disable
The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin.
1 = No 13 MHz clock driven externally
0 = 13 MHz clock driven externally
If the 13 MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by -4 dBm on
channels 5+13n. By default the 13 MHz clock output pin is enabled. This pin is useful for adjusting the
13 MHz clock, but it interferes with every 13th channel beginning with 2.405 GHz channel. Therefore, it is
recommended that the 13 MHz clock output pin be disabled when not in use.
5:0
Crystal Adjust
The Crystal Adjust value is used to calibrate the on-chip load capacitance supplied to the crystal. The
Crystal Adjust value will depend on the parameters of the crystal being used. Refer to the appropriate
reference material for information about choosing the optimum Crystal Adjust value.
24
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Table 30. VCO Calibration
Addr: 0x26
7
REG_VCO_CAL
6
5
4
Default: 0x00
3
VCO Slope Enable
2
1
0
Reserved
Bit
Name
Description
7:6
VCO Slope
Enable
(Write-Only)
The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance
automatically added to the VCO.
11 = -5/+5 VCO adjust. The application MCU must configure this option during initialization
10 = -2/+3 VCO adjust
01 = Reserved
00 = No VCO adjust
These bits are undefined for read operations.
5:0
Reserved
These bits are reserved and should be written with zeros.
Table 31. AGC Control
Addr: 0x2E
7
REG_AGC_CTL
6
5
4
AGC Lock
3
Default: 0x00
2
1
0
Reserved
Bit
Name
Description
7
AGC Lock
When set, this bit disables the on-chip LNA AGC system, powers down unused circuitry, and locks the LNA
to maximum gain. The user must set Reg 20, bit 6 = 1 to enable writes to Reg 0x2E. It is recommended
this bit be set during initialization to save power.
6:0
Reserved
These bits are reserved and should be written with zeros.
Table 32. Carrier Detect
Addr: 0x2F
7
REG_CARRIER_DETECT
6
5
Carrier Detect
Override
4
3
Default: 0x00
2
1
0
Reserved
Bit
Name
Description
7
Carrier Detect
Override
When set, this bit overrides the carrier detect. The user must set Reg 20, bit 6 = 1 to enable writes to
Reg 0x2F.
6:0
Reserved
These bits are reserved and should be written with zeros.
25
4822C–ISM–09/04
Table 33. Clock Manual
Addr: 0x32
7
REG_CLOCK_MANUAL
6
5
4
3
Default: 0x00
2
1
0
Manual Clock Overrides
Bit
Name
Description
7:0
Manual Clock
Overrides
This register must be written with 0x41 after reset for correct operation
Table 34. Clock Enable
Addr: 0x33
7
REG_CLOCK_ENABLE
6
5
4
3
Default: 0x00
2
1
0
Manual Clock Enables
Bit
Name
Description
7:0
Manual Clock
Enables
This register must be written with 0x41 after reset for correct operation
Table 35. Synthesizer Lock Count
Addr: 0x38
7
REG_SYN_LOCK_CNT
6
5
4
3
Default: 0x64
2
1
0
Count
Bit
Name
Description
7:0
Count
Determines the length of delay in 2 µs increments for the synthesizer to lock when auto synthesizer is
enabled via Control register (0x03, bit 1 = 0) and not using the PLL lock signal.
Table 36. Manufacturing ID
Addr: 0x3C-3F
REG_MID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address 0x3F
Address 0x3E
Address 0x3D
9
8
7
6
5
4
3
2
1
0
Address 0x3C
Bit
Name
Description
31:0
Address[31:0]
These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read
unless the MID Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the
Manufacturing ID register (Reg 0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog
Control register (Reg 0x20, bit 5) should only be set when reading the contents of the Manufacturing
ID register (Reg 0x3C to 0x3F). This register is read-only.
26
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Value
Unit
Storage temperature
Pin
Symbol
-65 to +150
°C
Ambient temperature with power applied
-55 to +125
°C
Supply voltage on VCC relative to VSS
-0.3 to +3.9
V
DC voltage to logic inputs
-0.3 to VCC +0.3
V
DC voltage applied to outputs in high-Z state
-0.3 to VCC +0.3
V
> 2000
V
500
V
+200, -200
mA
(1)
Static discharge voltage (digital)
(2)
Static discharge voltage (RF)
Latch-up current
Notes:
1. It is permissible to connect voltages above VCC to inputs through a series resistor limiting input current to 1 mA.
This cannot be done during power down mode. AC timing not guaranteed.
2. Human Body Model (HBM).
Operating Conditions
Parameters
Supply voltage
Ambient temperature under bias
Symbol
Unit
VCC
2.7 to 3.6
V
TA
-40 to +85
°C
0
V
13
MHz
Ground voltage
Oscillator or crystal frequency)
Value
FOSC
27
4822C–ISM–09/04
DC Parameters
Description
Conditions
Symbol
Min.
Typ.(1)
Max.
3.6
Unit
VCC
2.7
3.0
Output high voltage condition 1
At IOH = -100.0 µA
VOH1
VCC - 0.1
VCC
V
Output high voltage condition 2
At IOH = -2.0 mA
VOH2
2.4
3.0
V
Output low voltage
At IOL = 2.0 mA
VOL
Supply voltage
0.0
V
0.4
V
(2)
Input high voltage
VIH
2.0
VCC
Input low voltage
VIL
-0.3
+0.8
V
IIL
-1
0.26
+1
µA
CIN
3.5
10
pF
10
µA
Input leakage current
0 < VIN < VCC
Pin input capacitance (except
X13, X13IN, RFIN)
V
Current consumption during
power-down mode
PD = LOW
ISleep
0.24
Current consumption without
synthesizer
PD = HIGH
IDLE ICC
3
mA
STARTUP
ICC
1.8
mA
ICC from PD high to oscillator
stable
Average transmitter current
consumption(3)
No handshake
TX AVG
ICC1
5.9
mA
Average transmitter current
consumption(4)
With handshaking
TX AVG
ICC2
8.1
mA
57.7
mA
69.1
mA
28.7
mA
Current consumption during
receive
RX ICC
Current consumption during
transmit
TX ICC
Current consumption with
synthesizer on, no transmit or
receive
Notes:
28
(PEAK)
(PEAK)
SYNTH
SETTLE
ICC
1. Typical values measured with VCC = 3.0 V at 25°C.
2. It is permissible to connect voltages above VCC to inputs through a series resistor limiting input current to 1 mA.
3. Average ICC when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB
1-way protocol.
4. Average ICC when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB
2-way protocol.
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
AC Characteristics(1): SPI Interface(3)
Description
Parameter
Min.
Typ.
Max.
Unit
tSCK_CYC
476
ns
SPI clock high time
tSCK_HI (BURST READ)(2)
238
ns
SPI clock high time
tSCK_HI
158
ns
SPI clock low time
tSCK_LO
158
ns
SPI clock period
SPI input data set-up time
tDAT_SU
10
ns
SPI input data hold time
tDAT_HLD
97(3)
ns
SPI output data valid time
tDAT_VAL
77(3)
SPI slave select set-up time before first positive edge of
SCK(4)
tSS_SU
250
ns
SPI slave select hold time after last negative edge of
SCK
tSS_HLD
80
ns
Notes:
1.
2.
3.
4.
174(3)
ns
AC values are not guaranteed if voltages on any pin exceed VCC.
This stretch only applies to every 9th SCK HI pulse for SPI burst reads only.
For FOSC = 13 MHz, 3.3 V at 25°C.
SCK must start low, otherwise the success of SPI transactions are not guaranteed.
Figure 9. SPI Timing Diagram
tS CK _CY C
tSCK_HI
tSCK _LO
SCK
SS
MOSI
tSS_SU
SA
M
tD AT_S U
PL
D
E
tDA T_HLD
RI
tS S_HLD
VE
d a ta fro m m cu
d a ta fro m m c u
d a ta fro m m cu
d a ta
d a ta to m c u
d a ta
tDA T_VA L
M IS O
d a ta to m c u
Figure 10. SPI Burst Read Every 9th SCK HI Stretch Timing Diagram
t SCK_CYC
t S CK_HI
SCK
every 8
t SCK _LO
t SCK _HI (BURS T RE AD)
every 9 th SCK _HI
SCK_HI
D
SS
M ISO
th
RI
DR
VE
data to mcu
every 10th SC K_HI
data to mcu
IV
D
E
data to mcu
RI
VE
data
t D AT_VA L
29
4822C–ISM–09/04
DIO Interface
Parameter
Description
Min.
Typ.
Max.
Unit
Transmit
tTX_DIOVAL_SU
DIOVAL set-up time
2.1
µs
tTX_DIO_SU
DIO set-up time
2.1
µs
tTX_DIOVAL_HLD
DIOVAL hold time
0
µs
tTX_DIO_HLD
DIO hold time
0
tTX_IRQ_HI
tTX_IRQ_LO
µs
Minimum IRQ high time - 32 chips/bit DDR
8
µs
Minimum IRQ high time - 32 chips/bit
16
µs
Minimum IRQ high time - 64 chips/bit
32
µs
Minimum IRQ low time - 32 chips/bit DDR
8
µs
Minimum IRQ low time - 32 chips/bit
16
µs
Minimum IRQ low time - 64 chips/bit
32
µs
Receive
tRX_DIOVAL_VLD
tRX_DIO_VLD
tRX_IRQ_HI
tRX_IRQ_LO
DIOVAL valid time - 32 chips/bit DDR
-0.01
+6.1
µs
DIOVAL valid time - 32 chips/bit
-0.01
+8.2
µs
DIOVAL valid time - 64 chips/bit
-0.01
+16.1
µs
DIO valid time - 32 chips/bit DDR
-0.01
+6.1
µs
DIO valid time - 32 chips/bit
-0.01
+8.2
µs
DIO valid time - 64 chips/bit
-0.01
+16.1
µs
Minimum IRQ high time - 32 chips/bit DDR
1
µs
Minimum IRQ high time - 32 chips/bit
1
µs
Minimum IRQ high time - 64 chips/bit
1
µs
Minimum IRQ low time - 32 chips/bit DDR
8
µs
Minimum IRQ low time - 32 chips/bit
16
µs
Minimum IRQ low time - 64 chips/bit
32
µs
Figure 11. DIO Receive Timing Diagram
tRX_IRQ_LO
tRX_IRQ_HI
IRQ
DIO/
DIOVAl
SA
SA
MP
LE
data
MP
LE
data
data
tRX_DIO_VLD
tRX_DIOVAL_VLD
30
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Figure 12. DIO Transmit Timing Diagram
tTX_IRQ_LO
tTX_IRQ_HI
SA
MP
LE
SA
MP
LE
IRQ
DIO/
DIOVAl
data
tTX_DIO_SU
data
tTX_DIO_HLD
tTX_DIOVAL_HLD
tTX_DIOVAL_SU
Radio Parameters
Parameter Description
Conditions
RF frequency range
(1)
Min.
Typ.
2.400
Max.
Unit
2.483
GHz
Radio Receiver (VCC = 3.3 V, fosc = 13.000 MHz, X13OUT off, 64 chips/bit, Threshold Low = 8, Threshold High = 56, BER < 10-3)
Sensitivity
-85
-95
dBm
Maximum received signal
-20
-6
dBm
RSSI value for PWRin > -40 dBm
28 31
RSSI value for PWRin < -95 dBm
0 -10
Interference Performance
Co-channel interference rejection Carrier-to-Interference (C/I)
C = -60 dBm
Adjacent (1 MHz) channel selectivity C/I 1 MHz
C = -60 dBm
-2
dB
Adjacent (2 MHz) channel selectivity C/I 2 MHz
C = -60 dBm
-32
dB
Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz
C = -67 dBm
-40
dB
C = -67 dBm
-31
dB
C = -67 dBm
-38
dB
C = -67 dBm
-24
dBm
2498 MHz to 12.75 GHz, except (FO/N and FO × N ±1 MHz)
C = -67 dBm
-22
dBm
Intermodulation
C = -64 dBm
∆f = 5,10 MHz
-31
dBm
(2)
Image
frequency interference, C/I image
Adjacent (1 MHz) interference to in-band image frequency,
C/I image ±1 MHz
9
dB
Out-of-band Blocking Interference Signal Frequency
30 MHz to 2399 MHz except (FO/N and FO/N ±1 MHz)(3)
(3)
Spurious Emission
30 MHz to 1 GHz
-57
dBm
1 GHz to 12.75 GHz except (4.8 GHz to 5.0 GHz)
-47
dBm
-37(4)
dBm
4.8 GHz to 5.0 GHz
Radio Transmitter (VCC = 3.3 V, fosc = 13.000 MHz)
Maximum RF transmit power
RF power control range
Notes:
1.
2.
3.
4.
PA = 7
-0.5
dBm
28.9
dB
Subject to regulation.
Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection).
FO = Tuned Frequency, N = Integer.
Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory
requirements.
31
4822C–ISM–09/04
Radio Parameters (Continued)
Parameter Description
Conditions
Min.
Typ.
Max.
Unit
RF power range control step size
Seven steps, monotonic
4.1
dB
Frequency deviation
PN code pattern 10101010
276
kHz
Frequency deviation
PN code pattern 11110000
317
kHz
±80
ns
898
kHz
±44.6
kHz
Zero crossing eError
100-kHz resolution
bandwidth, -6 dBc
Occupied bandwidth
500
Initial frequency offset
In-band Spurious
Second channel power (±2 MHz)
-41
-30
dBm
≥ Third channel power (>3 MHz)
-49
-40
dBm
-57
dBm
Second harmonic
-20
dBm
Third harmonic
-30
dBm
Fourth and greater harmonics
-47
dBm
Non-Harmonically Related Spurs
30 MHz to 12.75 GHz
Harmonic Spurs
Notes:
1.
2.
3.
4.
Subject to regulation.
Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection).
FO = Tuned Frequency, N = Integer.
Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory
requirements.
Power Management Timing
Parameter
Conditions
tPDN_X13
Time from PD deassert to X13OUT
tSPI_RDY
Time from oscillator stable to start of SPI transactions
tPWR_RST
Power On to RESET deasserted
tRST
PD deassert to clocks running
tSLEEP
tSTABLE
PD deassert to clock stable
to within ±10 ppm
Unit
µs
1300
µs
1
µs
1300
µs
10
PD deassert to IRQ(3) assert (wake interrupt)(4)
Max.
µs
2000
PD assert to low power mode
tWAKE_INT
Typ
1
(2)
Minimum PD asserted pulse width
tPD
Notes:
VCC at 2.7 V
Power on to PD deasserted(1)
tWAKE
Min.
2000
Minimum RESET asserted pulse width
tPWR_PD
32
Description
µs
µs
50
µs
2000
µs
2100
µs
1. The PD pin must be asserted at power up to ensure proper crystal start-up.
2. When X13OUT is enabled.
3. Both the polarity and the drive method of the IRQ pin are programmable. See page 14 for more details.
Figure 14 illustrates default values for the Configuration register (Reg 0x05, bits 1:0).
4. A wake-up event is triggered when the PD pin is deasserted. Figure 14 illustrates a wake-up event configured to trigger an
IRQ pin event via the Wake Enable register (Reg 0x1C, bit 0 = 1).
ATR2434 [Preliminary]
4822C–ISM–09/04
ATR2434 [Preliminary]
Figure 13. Power On Reset/Reset Timing
tPDN_X13
X 13O U T
S
VCC
t S P I_ R D Y
A
T
T
R
tPW R_RST
PD
tPW R_PD
P
U
RESET
tRST
Figure 14. Sleep/Wake Timing
tW A KE
X 13O U T
W
tPD
E
K
A
P
E
LE
S
PD
tSTABLE
Q
IR
t S LE E P
t W A K E _IN T
IR Q
AC Test Loads and Waveforms for Digital Pins
Figure 15. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
DC Test Load
OUTPUT
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
VCC
5 pF
R1
OUTPUT
INCLUDING
JIG AND
SCOPE
Max
R2
Typical
ALL INPUT PULSES
Parameter
R1
R2
RTH
VTH
VCC
1071
937
500
1.4
3.00
Unit
Ω
Ω
Ω
V
V
VCC
GND
90%
10%
Rise time: 1 V/ns
90%
10%
Fall time: 1 V/ns
THÉVENIN EQUIVALENT
RTH
VTH
OUTPUT
Equivalent to:
33
4822C–ISM–09/04
Ordering Information
Extended Type Number
Package
Remarks
ATR2434-PLT
QFN48 - 7x7
Tray
ATR2434-PLT
QFN48 - 7x7
Samples
Package Information
34
ATR2434 [Preliminary]
4822C–ISM–09/04
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
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