TI1 CSD17578Q5A 30v n-channel nexfet power mosfet Datasheet

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CSD17578Q5A
SLPS526 – MARCH 2015
CSD17578Q5A 30 V N-Channel NexFET™ Power MOSFETs
1 Features
•
•
•
•
•
•
•
•
Product Summary
Low Qg and Qgd
Low RDS(on)
Low Thermal Resistance
Avalanche Rated
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5 mm × 6 mm Plastic Package
1
TA = 25°C
30
V
Qg
Gate Charge Total (4.5 V)
7.9
nC
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On-Resistance
VGS(th)
Threshold Voltage
mΩ
VGS = 10 V
5.9
mΩ
1.5
V
Device
Media
Qty
Package
Ship
13-Inch Reel
2500
CSD17578Q5AT
7-Inch Reel
250
SON 5 x 6 mm
Plastic Package
Tape and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
This 30 V, 5.9 mΩ, SON 5 mm x 6 mm NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
Top View
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
30
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package limited)
25
Continuous Drain Current (Silicon limited),
TC = 25°C
59
ID
8
1
(1)
S
2
7
D
S
3
6
D
16
Pulsed Drain Current(2)
132
Power Dissipation(1)
3.1
Power Dissipation, TC = 25°C
42
TJ,
Tstg
Operating Junction and
Storage Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 22 A, L = 0.1 mH
23
mJ
PD
D
5
4
D
P0093-01
A
Continuous Drain Current
D
IDM
G
nC
7.9
CSD17578Q5A
3 Description
S
2.0
VGS = 4.5 V
.
Ordering Information(1)
Point-of-Load Synchronous Buck Converter for
Applications in Networking, Telecom, and
Computing Systems
Optimized for Control FET Applications
•
UNIT
Drain-to-Source Voltage
2 Applications
•
TYPICAL VALUE
VDS
A
W
(1) Typical RθJA = 40°C/W on a 1 inch2, 2 oz. Cu pad on a 0.06
inch thick FR4 PCB.
(2) Max RθJC = 3.8°C/W, pulse duration ≤100 μs, duty cycle ≤1%
.
.
RDS(on) vs VGS
Gate Charge
10
TC = 25° C, I D = 10 A
TC = 125° C, I D = 10 A
24
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
28
20
16
12
8
4
0
ID = 10 A
VDS = 15 V
8
6
4
2
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
0
3
6
9
12
Qg - Gate Charge (nC)
15
18
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD17578Q5A
SLPS526 – MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.1 Trademarks ............................................................... 7
6.2 Electrostatic Discharge Caution ................................ 7
6.3 Glossary .................................................................... 7
1
1
1
2
3
7
7.1
7.2
7.3
7.4
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Mechanical, Packaging, and Orderable
Information ............................................................. 8
Device and Documentation Support.................... 7
Q5A Package Dimensions ........................................ 8
Recommended PCB Pattern..................................... 9
Recommended Stencil Opening ............................. 10
Q5A Tape and Reel Information ............................. 10
4 Revision History
2
DATE
REVISION
NOTES
March 2015
*
Initial release.
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5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-Source Leakage Current
VGS = 0 V, VDS = 24 V
1
μA
IGSS
Gate-to-Source Leakage Current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-Source Threshold Voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-Source On-Resistance
gƒs
Transconductance
30
1.1
V
1.5
1.9
V
VGS = 4.5 V, ID = 10 A
7.9
9.3
mΩ
VGS = 10 V, ID = 10 A
5.9
6.9
mΩ
VDS = 3 V, ID = 10 A
44
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
RG
Series Gate Resistance
Qg
Gate Charge Total (4.5 V)
Qg
Gate Charge Total (10 V)
Qgd
Gate Charge Gate-to-Drain
Qgs
Gate Charge Gate-to-Source
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
td(off)
Turn Off Delay Time
tƒ
Fall Time
VGS = 0 V, VDS = 15 V, ƒ = 1 MHz
VDS = 15 V, ID = 10 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 10 V,
IDS = 10 A, RG = 0 Ω
1170
1510
pF
136
177
pF
58
75
pF
1.8
3.6
Ω
7.9
10.3
nC
17.2
22.3
nC
2.0
nC
3.1
nC
1.7
nC
4.2
nC
4
ns
22
ns
17
ns
2
ns
DIODE CHARACTERISTICS
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 10 A, VGS = 0 V
0.8
VDS= 15 V, IF = 10 A,
di/dt = 300 A/μs
6.5
1.0
nC
V
6.8
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
(1)
RθJC
Junction-to-Case Thermal Resistance
RθJA
Junction-to-Ambient Thermal Resistance (1) (2)
(1)
(2)
MIN
TYP
MAX
3.8
50
UNIT
°C/W
RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm ×
3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
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CSD17578Q5A
SLPS526 – MARCH 2015
GATE
www.ti.com
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick)
Cu.
Source
Max RθJA = 140°C/W
when mounted on a
minimum pad area of
2 oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
60
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
100
80
60
40
20
VGS = 4.5 V
VGS = 6 V
VGS = 10 V
0
TC = 125° C
TC = 25° C
TC = -55° C
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
VDS - Drain-to-Source Voltage (V)
1.4
1.6
1
1.5
D002
2
2.5
3
VGS - Gate-to-Source Voltage (V)
3.5
D003
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
8
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
6
4
1000
100
2
10
0
0
3
6
9
12
Qg - Gate Charge (nC)
ID = 10 A
15
0
18
5
D004
30
D005
Figure 5. Capacitance
28
RDS(on) - On-State Resistance (m:)
2.1
VGS(th) - Threshold Voltage (V)
25
VDS = 15 V
Figure 4. Gate Charge
1.9
1.7
1.5
1.3
1.1
0.9
0.7
-75
10
15
20
VDS - Drain-to-Source Voltage (V)
TC = 25° C, I D = 10 A
TC = 125° C, I D = 10 A
24
20
16
12
8
4
0
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
125
150
175
0
2
D006
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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SLPS526 – MARCH 2015
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100
1.8
VGS = 4.5 V
VGS = 10 V
ISD - Source-to-Drain Current (A)
Normalized On-State Resistance
2
1.6
1.4
1.2
1
0.8
0.6
0.4
-75
TC = 25° C
TC = 125° C
10
1
0.1
0.01
0.001
0.0001
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
125
150
175
0
0.2
D008
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D009
ID = 10 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
100
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
100
10
1
DC
10 ms
1 ms
0.1
0.1
100 µs
10 µs
1
10
VDS - Drain-to-Source Voltage (V)
100
TC = 25q C
TC = 125q C
10
1
0.01
0.1
TAV - Time in Avalanche (ms)
D010
0.8
D011
Single Pulse, Max RθJC = 3.8°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current (A)
30
25
20
15
10
5
0
-50
-25
0
25
50
75
100 125
TC - Case Temperature (° C)
150
175
D012
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS526 – MARCH 2015
6 Device and Documentation Support
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD17578Q5A
SLPS526 – MARCH 2015
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
2
3
4
5
4
5
6
3
6
7
2
7
1
8
1
DIM
8
8
7.1 Q5A Package Dimensions
MILLIMETERS
MIN
NOM
MAX
A
0.90
1.00
1.10
b
0.33
0.41
0.51
c
0.20
0.25
0.34
D1
4.80
4.90
5.00
D2
3.61
3.81
4.02
E
5.90
6.00
6.10
E1
5.70
5.75
5.80
E2
3.38
3.58
3.78
E3
3.03
3.13
3.23
e
1.17
1.27
1.37
e1
0.27
0.37
0.47
e2
0.15
0.25
0.35
H
0.41
0.56
0.71
K
1.10
L
0.51
0.61
0.71
L1
0.06
0.13
0.20
θ
0°
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12°
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SLPS526 – MARCH 2015
7.2 Recommended PCB Pattern
F1
F7
F3
8
1
F2
F11
F5
F9
5
4
F6
F8
F4
F10
M0139-01
DIM
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
F1
6.205
6.305
0.244
0.248
F2
4.46
4.56
0.176
0.18
F3
4.46
4.56
0.176
0.18
F4
0.65
0.7
0.026
0.028
F5
0.62
0.67
0.024
0.026
F6
0.63
0.68
0.025
0.027
F7
0.7
0.8
0.028
0.031
F8
0.65
0.7
0.026
0.028
F9
0.62
0.67
0.024
0.026
F10
4.9
5
0.193
0.197
F11
4.46
4.56
0.176
0.18
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
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7.3 Recommended Stencil Opening
(0.020) 8x
0.500
(0.020)
0.500
5
4
0.500
(0.020) 8x
1.585
(0.062)
1.235
(0.049)
(0.024)
0.620
(0.170) 4.310
0.385
(0.015)
1.270 (0.050)
1
8
1.570 (0.062)
4x
0.615
(0.024)
1.105
(0.044)
3.020
(0.119)
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
7.4 Q5A Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
R 0.30 TYP
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket
10
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PACKAGE OPTION ADDENDUM
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10-Mar-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD17578Q5A
ACTIVE
VSONP
DQJ
8
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
CSD17578
CSD17578Q5AT
ACTIVE
VSONP
DQJ
8
250
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
CSD17578
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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10-Mar-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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