PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 a FEATURES Nonvolatile Memory Preset Maintains Wiper Settings AD5231 Single, 1024 Position Resolution AD5232 Dual, 256 Position Resolution AD5233 Quad, 64 Position Resolution 10K, 50K, 100K Ohm Terminal Resistance Linear or Log taper Settings Increment/Decrement Commands, Push Button Command SPI Compatible Serial Data Input with Readback Function +3 to +5V Single Supply or ±2.5V Dual Supply Operation User EEMEM nonvolatile memory for constant storage APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment DIP Switch Setting GENERAL DESCRIPTION The AD5231/AD5232/AD5233 family provides a single/dual-/quad-channel, digitally controlled variable resistor (VR) with resolutions of 1024/256/64 positions respectively. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD523X’s versatile programming via a Micro Controller allows multiple modes of operation and adjustment. In the direct program mode a predetermined setting of the RDAC register can be loaded directly from the micro controller. Another key mode of operation allows the RDAC register to be refreshed with the setting previously stored in the EEMEM register. When changes are made to the RDAC register to establish a new wiper position, the value of the setting can be saved into the EEMEM by executing an EEMEM save operation. Once the settings are saved in the EEMEM register these values will be transferred automatically to the RDAC register to set the wiper position at system power ON. Such operation is enabled by the internal preset strobe and the preset can also be accessed externally. The basic mode of adjustment is the increment and decrement command controlling the present setting of the Wiper position setting (RDAC) register. An internal scratch pad RDAC register can be moved UP or DOWN, one step of the nominal terminal resistance between terminals A-and-B. This linearly changes the wiper to B terminal resistance (RWB) by one position segment of the device's end-to-end resistance (RAB). For exponential/logarithmic changes in wiper setting, a left/right shift command adjusts levels in +/-6dB steps, which can be useful for sound and light alarm applications. The AD523X are available in the thin TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +85°C. FUNCTIONAL BLOCK DIAGRAMS AD 523 1 CS AD DR D ECO D E CLK SDI SDI GND S E R IA L IN T E R F A C E SDO SDO WP RDY RDAC1 R E G IS T E R W1 D IG IT A L 2 R E G IS T E R 28 B Y TE S USER EEMEM SDI GND S E R IA L IN T E R F A C E SDO SDO RDY RDAC1 R E G IS T E R 14 BYTES USER EEM EM V SS SDI SDO A1 B1 RDAC2 A2 W2 B2 EEM EM 2 V SS RDAC1 R E G IS T E R O1 O2 A1 W1 EEM EM 1 RDAC2 R E G IS T E R B1 RDAC2 A2 EEM EM CONTRO L W2 B2 11 BY T ES USER EEM EM D IG IT A L OUTPUT BUFFER RDAC3 R E G IS T E R RDAC3 A3 W3 EEM EM 3 B3 2 D IG IT A L 5 R E G IS T E R RDAC4 R E G IS T E R RDAC4 A4 W4 PR EEM EM 5 EEM EM 4 B4 V SS REV PrF, 22 MAR '01 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. V DD RDAC1 EEM EM 2 GND V DD RDAC1 A D 5233 AD D R D EC O D E S E R IA L IN T E R F A C E RDY O2 W1 RDAC2 R E G IS T E R C LK WP O1 EEM EM 1 CS SDO D IG IT A L O UTPUT BU FFER EEM EM CONTRO L PR SDI 2 A D 5232 AD D R D EC O D E C LK WP B1 EEMEM2 CS SDI A1 EEMEM1 EEMEM C ON TR O L PR V DD RDAC1 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax:617/326-8703 © Analog Devices, Inc., 1999 PRELIMINARY TECHNICAL DATA AD5231/AD5232/AD5233 - SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS (VDD = +3V±10% or +5V±10% and VSS=0V, VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.) Parameter Symbol Conditions 1 Min Typ ±1/4 ±1/2 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs Resistor Differential Nonlinearity2 Resistor Nonlinearity2 R-DNL R-INL RWB, VA=NC RWB, VA=NC -1 -1 Nominal resistor tolerance Resistance Temperature Coefficent Wiper Resistance Wiper Resistance ∆R RAB/∆T RW RW TA = 25°C, VAB = VDD,Wiper (VW) = No connect VAB = VDD, Wiper (VW) = No Connect IW = 1 V/R, VDD = +5V IW = 1 V/R, VDD = +3V -30 500 50 200 +1 +1 LSB %FS 30 % ppm/°C Ω Ω 100 DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution Integral Nonlinearity3 Differential Nonlinearity3 Voltage Divider Temperature Coefficent Full-Scale Error Zero-Scale Error N INL DNL ∆VW/∆T VWFSE VWZSE AD5231/AD5232/AD5233 Code = Half-scale Code = Full-scale Code = Zero-scale VA,B,W CA,B CW ICM f = 1 MHz, measured to GND, Code = Half-scale f = 1 MHz, measured to GND, Code = Half-scale VA = VB = VDD/2 10 / 8 / 6 –1 –1 ±1/2 ±1/4 15 –3 0 +1 +1 +0 +3 Bits %FS LSB ppm/°C %FS %FS RESISTOR TERMINALS Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-mode Leakage Current6 VSS VDD 45 60 0.01 1 V pF pF µA DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High Output Logic High Output Logic Low Input Current Input Capacitance5 VIH VIL VIH VIL VOH VOH VOL IIL CIL with respect to GND, VDD = 5V with respect to GND, VDD = 5V with respect to GND, VDD = 3V with respect to GND, VDD = 3V RPULL-UP = 2.2KΩ to +5V IOH = 40µA, VLOGIC = +5V IOL = 1.6mA, VLOGIC = +5V VIN = 0V or VDD Single-Supply Power Range VDD VSS = 0V Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current13 Negative Supply Current Power Dissipation7 Power Supply Sensitivity VDD/VSS IDD IDD(PG) IDD(READ) ISS PDISS PSS VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V VIH = VDD or VIL = GND ∆VDD = +5V ±10% Bandwidth –3dB Total Harmonic Distortion VW Settling Time BW_10K THDW tS R = 10KΩ VA =1Vrms, VB = 0V, f=1KHz VA= VDD, VB=0V, 50% of final value Resistor Noise Voltage eN_WB For RAB = 10K/50K/100K RWB = 5KΩ, f = 1KHz Crosstalk (CW1/CW2) CT 2.4 0.8 2.1 0.6 4.9 4 0.4 ±1 5 V V V V V V V µA pF POWER SUPPLIES 2.7 5.5 ±2.25 ±2.75 20 2 35 0.9 0.002 9 10 0.1 0.01 V V µA mA mA µA mW %/% DYNAMIC CHARACTERISTICS5, 8 VA = VDD, VB = 0V, Measure VW with adjacent VR making full scale change 600 0.003 1/3/6 9 -65 KHz % µs nV√Hz dB NOTES: See bottom of table next page. REV PrF 2 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA AD5231/AD5232/AD5233 - SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS (V = +3V±10% to +5V±10% and V =0V, DD SS VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.) Parameter Symbol Conditions Min INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 9) Clock Cycle Time t1 Input Clock Pulse Width t 2, t 3 Clock level high or low CS Setup Time t4 Data Setup Time t5 From Positive CLK transition Data Hold Time t6 From Positive CLK transition CLK Shutdown Time t7 CS Rise to Clock Rise Setup t8 CS High Pulse Width t9 CLK to SDO Propagation Delay10 t 10 RP = 1KΩ, CL < 20pF Store to Nonvolatile EEMEM Save Time11 t 12 Applies to Command 2H, 3H, 9H CS to SDO - SPI line acquire t13 CS to SDO - SPI line release t14 RDY Rise to CS Fall t15 Startup Time t16 CLK Setup Time t17 For 1 CLK period (t4 - t3 = 1 CLK period) Preset Pulse Width (Asynchronous) tPR Preset Response Time tPRESP PR pulsed low then high Typ 20 10 10 5 5 0 10 10 1 1 Max 25 25 50 70 Units ns ns ns ns ns ns ns ns ns ms ns ns ns ms ns ns us NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typicals represent average readings at +25°C and VDD = +5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+3V or VDD=+5V. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. Resistor terminals A, B, W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. Common mode leakage current is a measure of the DC leakage from any terminal A, B, W to a common mode bias level of VDD / 2. PDISS is calculated from (IDD x VDD) + (ISS X VSS). All dynamic characteristics use VDD = +5V. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using both VDD = +3V or +5V. Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text. Low only for instruction commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms Dual Supply Operation primarily affects the POT terminals. Read Mode current is not continuous. Timing Diagram C LK t 17 t1 t3 t2 t7 t4 t8 CS t9 t5 t6 MSB SDI t 13 SDO1 LSB t 10 t 14 MSB SDO2 LSB MSB LSB t 15 t 16 RDY SD O 1 C LK ID LES L O W t 12 SD O 2 C LK ID LES H IG H Figure 1. Timing Diagram REV PrF 3 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 Absolute Maximum Rating (TA = +25°C, unless Digital Inputs & Output Voltage to GND .................. 0V, +7V Operating Temperature Range ........................ -40°C to +85°C Maximum Junction Temperature (TJ MAX) .................. +150°C Storage Temperature ..................................... -65°C to +150°C Lead Temperature (Soldering, 10 sec) ......................... +300°C Package Power Dissipation ........................ (TJMAX - TA) / θJA otherwise noted) VDD to GND ..............................................................-0.3, +7V VSS to GND .................................................................0V, -7V VDD to VSS .........................................................................+7V VA, VB, VW to GND..................................................VSS, VDD AX – BX, AX – WX, BX – WX Intermittent ...................................................±20mA Continuous................................................... ±1.3mA Ox to GND .................................................................. 0V, VDD Thermal Resistance θJA, TSSOP-16 ..................................................... 150°C/W TSSOP-24 ..................................................... 128°C/W Ordering Guide Model Number of Channels End to End R (k Ohm) Temp Range Package Description Package #Devices Top Mark Option per Container AD5231BRU10 AD5231BRU10-REEL7 AD5231BRU50 AD5231BRU50-REEL7 AD5231BRU100 AD5231BRU100-REEL7 X1 X1 X1 X1 X1 X1 10 10 50 50 100 100 -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 AD5232BRU10 AD5232BRU10-REEL7 AD5232BRU50 AD5232BRU50-REEL7 AD5232BRU100 AD5232BRU100-REEL7 X2 X2 X2 X2 X2 X2 10 10 50 50 100 100 -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 AD5233BRU10 AD5233BRU10-REEL7 AD5233BRU50 AD5233BRU50-REEL7 AD5233BRU100 AD5233BRU100-REEL7 X4 X4 X4 X4 X4 X4 10 10 50 50 100 100 -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 1,000 1,000 1,000 1,000 1,000 1,000 The AD5231/AD5232/AD5233 contains 9,646 transistors. Die size: 69 mil x 115 mil, 7,993 sq. mil REV PrF 4 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 AD5231 PIN CONFIGURATION O1 1 AD5232 PIN CONFIGURATION 16 O2 CLK 1 16 RDY SDI 2 15 CS SDI 3 14 CS SDO 3 14 PR SDO 4 13 PR GND 4 13 WP GND 5 12 WP VSS 5 12 VDD VSS 6 11 VDD A1 6 11 A2 T1 7 10 A1 W1 7 10 W2 B1 8 9 B1 8 9 CLK 2 15 RDY W1 B2 AD5231 PIN FUNCTION DESCRIPTION # Name Description AD5232 PIN FUNCTION DESCRIPTION # Name Description 1 O1 1 CLK 2 CLK 2 SDI 3 4 SDI SDO 3 SDO 4 5 GND VSS 6 7 A1 W1 8 9 10 B1 B2 W2 5 6 GND VSS 7 T1 8 9 B1 W1 10 A1 11 VDD 12 13 14 15 16 WP PR CS RDY O2 Non-Volatile Digital Output #1, ADDR(O1) = 1H, data bit position D0 Serial Input Register clock pin. Shifts in one bit at a time on positive clock CLK edges. Serial Data Input Pin. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 & 10 activate the SDO output. See Instruction operation Truth Table. Other commands shift out the previously loaded bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. Ground pin, logic ground reference. Negative Supply. Connect to zero volts for single supply applications. Used as digital input during factory test mode. Leave pin floating or connect to VDD or VSS. B terminal of RDAC1. Wiper terminal of RDAC1, ADDR(RDAC1) = 0H A terminal of RDAC1. Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 & 10 activate the SDO output. See Instruction operation Truth Table. Other commands shift out the previously loaded bit pattern delayed by 16 clock pulses. This allows daisy-chain operation of multiple packages. Ground pin, logic ground reference Negative Supply. Connect to zero volts for single supply applications. A terminal of RDAC1. Wiper terminal of RDAC1, ADDR(RDAC1) = 0H. B terminal of RDAC1. B terminal of RDAC2. Wiper terminal of RDAC2, ADDR(RDAC2) = 1H. A terminal of RDAC2. Positive Power Supply Pin. Should be ≥ the input-logic HIGH voltage. 11 A2 Write Protect Pin. When active low WP prevents any changes to the present contents except retrieving EEMEM contents and RESET. 12 VDD Positive Power Supply Pin. Should be ≥ the input-logic HIGH voltage. 13 WP Write Protect Pin. When active low, WP prevents any changes to the present contents, except retrieving EEMEM content and RESET. 14 PR Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 80H until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). 15 CS 16 RDY Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10. Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 200H until EEMEM loaded with a new value by the user (PR is activated at the rising logic high transition) Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10. Non-Volatile Digital Output #2, ADDR(O2) = 1H, data bit position D1. REV PrF 5 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 AD5233 PIN CONFIGURATION O1 1 CLK 2 24 O2 23 RDY SDI 3 22 CS SDO 4 21 PR GND 5 20 WP VSS 6 19 VDD A1 7 18 A4 W1 8 17 W4 B1 9 16 B4 A2 10 15 A3 W2 11 14 W3 B2 12 13 B3 AD5233 PIN FUNCTION DESCRIPTION # Name Description 1 2 3 4 O1 CLK SDI SDO 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND VSS A1 W1 B1 A2 W2 B2 B3 W3 A3 B4 W4 A4 Non-Volatile Digital Output #1, ADDR(O1) = 4H, data bit position D0. Serial Input Register clock pin. Shifts in one bit at a time on positive clock CLK edges. Serial Data Input Pin. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 & 10 activate the SDO output. See Instruction operation Truth Table. Other commands shift out the previously loaded bit pattern delayed by 16 clock pulses. This allows daisy-chain operation of multiple packages. Ground pin, logic ground reference Negative Supply. Connect to zero volts for single supply applications. A terminal of RDAC1. Wiper terminal of RDAC1, ADDR(RDAC1) = 0H. B terminal of RDAC1. A terminal of RDAC2. Wiper terminal of RDAC2, ADDR(RDAC2) = 1H. B terminal of RDAC2. B terminal of RDAC3. Wiper terminal of RDAC3, ADDR(RDAC3) = 2H. A terminal of RDAC3. B terminal of RDAC4. Wiper terminal of RDAC4, ADDR(RDAC4) = 3H. A terminal of RDAC4. 19 VDD Positive Power Supply Pin. Should be ≥ the input-logic HIGH voltage. 20 WP Write Protect Pin. When active low, WP prevents any changes to the present contents, except retrieving EEMEM content and RESET. 21 PR Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 20H until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). 22 23 24 CS RDY O2 Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10. Non-Volatile Digital Output #2, ADDR(O2) = 4H, data bit position D1. REV PrF 6 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 OPERATIONAL OVERVIEW The AD5231/32/33 digital potentiometer family is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS<VTERM<VDD. The basic voltage range is limited to a |VDD VSS| < 5.5V. Control of the digital potentiometer allows both scratch pad register (RDAC register) changes to be made, as well as, 100,000 nonvolatile electrically erasable memory (EEMEM) register operations. The EEMEM update process takes approximately 20.2ms, during this time the shift register is locked preventing any changes from taking place. The RDY pin flags the completion of this EEMEM save. The EEMEM retention is designed to last 15 years at 85°C, which is equivalent to 90 years at 55°C, without refresh. The scratch pad register can be changed incrementally by using the software controlled Increment/Decrement instruction or the Shift Left/Right instruction command. Once an Increment, Decrement or Shift command has been loaded into the shift register subsequent CS strobes will repeat this command. This is useful for push button control applications. Alternately the scratch pad register can be programmed with any position value using the standard SPI serial interface mode by loading the representative data word. The scratch pad register can be loaded with the current contents of the nonvolatile EEMEM register under program control. At system power ON, the default value of the scratch pad memory is the value previously saved in the EEMEM register. The factory EEMEM preset value is midscale. The scratch pad (wiper) register can be loaded with the current contents of the nonvolatile EEMEM register under hardware control by pulsing the PR pin. Beware that the PR pulse first sets the wiper at midscale when brought to logic zero, and then on the positive transition to logic high, it reloads the DAC wiper register with the contents of EEMEM. Similarly, the saved EEMEM value will automatically be retrieved to the scratch pad register during system power ON. A serial data output pin is available for daisy chaining and for readout of the internal register contents. The serial input data register uses a 16 or 24-bit instruction/address/data WORD. Write protect (WP) disables any changes of current content in the scratch pad register regardless of the commands, except that EEMEM setting can be retrieved using commands 1 and 9. Therefore, write-protect (WP) pin provides hardware EEMEM protection feature. DIGITAL INPUT/OUTPUT CONFIGURATION All digital inputs are ESD protected high input impedance that can be driven directly from most digital sources. For PR and WP, which are active at logic low, can be tied directly to VDD if they are not being used. The SDO and RDY pins are open drain digital outputs where pull-up resistors are needed only if using these functions. A resistor value in the range of 1k to 10k ohm optimizes the power and switching speed trade off. SERIAL DATA INTERFACE The AD523X family contains a four-wire SPI compatible digital interface (SDI, SDO, CS, and CLK). Key features of this interface include: • • Independently Programmable Read & Write to all registers Direct parallel refresh of all RDAC wiper registers from corresponding internal EEMEM registers • Increment & Decrement instructions for each RDAC wiper register • Left & right Bit Shift of all RDAC wiper registers to achieve 6dB level changes • Nonvolatile storage of the present scratch pad RDAC register values into the corresponding EEMEM register • Extra bytes of user addressable electrical-erasable memory The serial interface contains three different word formats to support the single AD5231, dual AD5232, and the quad AD5233 digital potentiometer devices. The AD5232 and AD5233 use a 16-bit serial data word loaded MSB first, while the AD5231 uses a 24-bit serial word loaded MSB first. The format of the SPI compatible word is shown in Table 1 and 2. The Command Bits (Cx) control the operation of the digital potentiometer according to the command instructions shown in Table 3, 4, and 5. The Address Bits (Ax) determine which register is activated. The Data Bits (Dx) are the values that are loaded into the decoded register. The last instruction executed prior to a period of no programming activity should be the No OPeration (NOP) instruction. This will place the internal logic circuitry in a minimum power dissipation state. PR V A L ID CO MMAND CO UNTER C LK CO MMAND PROCESSOR & ADDRESS DECODE +5V R P U L LU P S E R IA L R E G IS T E R SDO CS GND SDI Figure 2. Equivalent Digital Input-Output Logic The equivalent serial data input and output logic is shown in figure 2. The open drain output SDO is disabled whenever chip select CS is logic high. The SPI interface can be used in two slave modes CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA and CPOL refer to the control bits, which dictate SPI timing in the following microprocessors/Micro Converters: ADuC812/824, M68HC11, and MC68HC16R1/916R1. REV PrF 7 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 Table 1. AD5232 & AD5233 16-bit Serial Data Word MSB AD5232 C3 C2 C1 C0 A3 A2 A1 A0 AD5233 C3 C2 C1 C0 A3 A2 A1 A0 D7 X D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 LSB D0 D0 Table 2. AD5231 24-bit Serial Data Word M S B AD5231 C C C C A3 A2 A1 A0 X X X X X X D D D D D D D 3 2 1 0 9 8 7 6 5 4 3 Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in tables 3, 4, & 5. D 2 D 1 REV PrF 8 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] L S B D 0 PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 Table 3. AD5231 Instruction/Operation Truth Table Inst No. Instruction Byte 1 B15 •••••••••••••••• B8 Data Byte 0 B7 ••• B0 C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 X X X X Data Byte 1 B15 •••• B8 X ••• D9 D8 X ••• X X 0 1 0 0 0 1 << ADDR >> X ••• X X X ••• X Write contents of EEMEM(ADDR) to RDAC(ADDR) Register 2 0 0 1 0 << ADDR >> X ••• X X X ••• X SAVE WIPER SETTING: Write contents of RDAC(ADDR) to EEMEM(ADDR) 3 0 0 1 1 << ADDR >> X ••• D9 D8 D7 ••• D0 Write contents of Serial Register Data Byte 0 & 1 to EEMEM(ADDR) 4 0 1 0 0 << ADDR >> X ••• X X X ••• X Decrement 6dB: Right Shift contents of RDAC(ADDR), stops at all "Zeros". 5 0 1 0 1 X X X ••• X X X ••• X Decrement All 6dB: Right Shift contents of all RDAC Registers, stops at all "Zeros". 6 0 1 1 0 << ADDR >> X ••• X X X ••• X Decrement contents of RDAC(ADDR) by "One", stops at all "Zeros". 7 0 1 1 1 X X X X X ••• X X X ••• X Decrement contents of RDAC Register by "One", stops at all "Zeros". 8 1 0 0 0 0 0 0 0 X ••• X X X ••• X RESET: Load all RDACs with their corresponding EEMEM previously-saved values 9 1 0 0 1 << ADDR >> X ••• X X X ••• X Write contents of EEMEM(ADDR) to Serial Register Data Byte 0 & 1 10 1 0 1 0 << ADDR >> X ••• X X X ••• X Write contents of RDAC(ADDR) to Serial Register Data Byte 0 & 1 11 1 0 1 1 << ADDR >> X ••• D9 D8 D7 ••• D0 Write contents of Serial Register Data Byte 0 &1 to RDAC(ADDR) 12 1 1 0 0 << ADDR >> X ••• X X X ••• X Increment 6dB: Left Shift contents of RDAC(ADDR), stops at all "Ones". 13 1 1 0 1 X X X ••• X X X ••• X Increment All 6dB: Left Shift contents of all RDAC Registers, stops at all "Ones". 14 1 1 1 0 << ADDR >> X ••• X X X ••• X Increment contents of RDAC(ADDR) by "One", stops at all "Ones". 15 1 1 1 1 X X ••• X X X ••• X Increment contents of RDAC Register by "One", stops at all "Ones". X X X X X X X D7 ••• D0 X ••• X Operation No Operation (NOP): Do nothing NOTES: 1. The SDO output shifts-out the last 16-bits of data clocked into the serial register for daisy chain operation. Exception: following Instruction #9 or #10 the selected internal register data will be present in data byte 0 & 1. Instructions following #9 & #10 must be a full 24-bit data word to completely clock out the contents of the serial register. 2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile EEMEM register. 3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0. 4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high. REV PrF 9 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 Table 4. AD5232 Instruction/Operation Truth Table Inst No. Instruction Byte 1 B15 •••••••••••••••• B8 Data Byte 0 B7 ••••••••••••••••• B0 0 C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 X X X X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X 1 0 0 0 1 << ADDR >> X X X X X X X X Write contents of EEMEM(ADDR) to RDAC(ADDR) Register 2 0 0 1 0 << ADDR >> X X X X X X X X SAVE WIPER SETTING: Write contents of RDAC(ADDR) to EEMEM(ADDR) 3 0 0 1 1 << ADDR >> D7 D6 D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data Byte 0 to EEMEM(ADDR) 4 0 1 0 0 << ADDR >> X X X X X X X X Decrement 6dB: Right Shift contents of RDAC(ADDR) , stops at all "Zeros". 5 0 1 0 1 X X X X X X X X X X Decrement All 6dB: Right Shift contents of all RDAC Registers, stops at all "Zeros". 6 0 1 1 0 << ADDR >> X X X X X X X X Decrement contents of RDAC(ADDR) by "One", stops at all "Zeros". 7 0 1 1 1 X X X X X X X X X X X X Decrement contents of all RDAC Registers by "One", stops at all "Zeros". 8 1 0 0 0 0 0 0 0 X X X X X X X X RESET: Load all RDACs with their corresponding EEMEM previously-saved values 9 1 0 0 1 << ADDR >> X X X X X X X X Write contents of EEMEM(ADDR) to Serial Register Data Byte 0 10 1 0 1 0 << ADDR >> X X X X X X X X Write contents of RDAC(ADDR) to Serial Register Data Byte 0 11 1 0 1 1 << ADDR >> D7 D6 D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data Byte 0 to RDAC(ADDR) 12 1 1 0 0 << ADDR >> X X X X X X X X Increment 6dB: Left Shift contents of RDAC(ADDR), stops at all "Ones". 13 1 1 0 1 X X X X X X X X X X Increment All 6dB: Left Shift contents of all RDAC Registers, stops at all "Ones". 14 1 1 1 0 << ADDR >> X X X X X X X X Increment contents of RDAC(ADDR) by "One", stops at all "Ones". 15 1 1 1 1 X X X X X X X X X Increment contents of all RDAC Registers "One", stops at all "Ones". X X X X X X X Operation No Operation (NOP): Do nothing NOTES: 1. The SDO output shifts-out the last 8-bits of data clocked into the serial register for daisy chain operation. Exception: following Instruction #9 or #10 the selected internal register data will be present in data byte 0. Instructions following #9 & #10 must be a full 16-bit data word to completely clock out the contents of the serial register. 2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile EEMEM register. 3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0. 4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high. REV PrF 10 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 Table 5. AD5233 Instruction/Operation Truth Table Inst No. Instruction Byte 1 B15 •••••••••••••••• B8 Data Byte 0 B7 ••••••••••••••••• B0 0 C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 X X X X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X 1 0 0 0 1 << ADDR >> X X X X X X X X Write contents of EEMEM(ADDR) to RDAC(ADDR) Register 2 0 0 1 0 << ADDR >> X X X X X X X X SAVE WIPER SETTING: Write contents of RDAC(ADDR) to EEMEM(ADDR) 3 0 0 1 1 << ADDR >> D7 D6 D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data Byte 0 to EEMEM(ADDR) 4 0 1 0 0 << ADDR >> X X X X X X X X Decrement 6dB: Right Shift contents of RDAC(ADDR), stops at all "Zeros". 5 0 1 0 1 X X X X X X X X X X Decrement All 6dB: Right Shift contents of all RDAC Registers, stops at all "Zeros". 6 0 1 1 0 << ADDR >> X X X X X X X X Decrement contents of RDAC(ADDR) by "One", stops at all "Zeros". 7 0 1 1 1 X X X X X X X X X X X X Decrement contents of all RDAC Registers by "One", stops at all "Zeros". 8 1 0 0 0 0 0 0 0 X X X X X X X X RESET: Load all RDACs with their corresponding EEMEM previously-saved values 9 1 0 0 1 << ADDR >> X X X X X X X X Write contents of EEMEM(ADDR) to Serial Register Data Byte 0 10 1 0 1 0 << ADDR >> X X X X X X X X Write contents of RDAC(ADDR) to Serial Register Data Byte 0 11 1 0 1 1 << ADDR >> D7 D6 D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data Byte 0 to RDAC(ADDR) 12 1 1 0 0 << ADDR >> X X X X X X X X Increment 6dB: Left Shift contents of RDAC(ADDR), stops at all "Ones". 13 1 1 0 1 X X X X X X X X X X Increment All 6dB: Left Shift contents of all RDAC Registers, stops at all "Ones". 14 1 1 1 0 << ADDR >> X X X X X X X X Increment contents of RDAC(ADDR) by "One", stops at all "Ones". 15 1 1 1 1 X X X X X X X X X Increment contents of all RDAC Registers by "One", stops at all "Ones". X X X X X X X Operation No Operation (NOP): Do nothing NOTES: 1. The SDO output shifts-out the last 8-bits of data clocked into the serial register for daisy chain operation. Exception: following Instruction #9 or #10 the selected internal register data will be present in data byte 0. Instructions following #9 & #10 must be a full 16-bit data word to completely clock out the contents of the serial register. The wiper only has 64 positions that correspond to the lower 6-bits of register data. 2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile EEMEM register. 3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0. 4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high. REV PrF 11 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 Latched Digital Outputs A pair of digital outputs, O1 & O2, is available on the AD5231, and the AD5233 parts that provide a nonvolatile logic 0 or logic 1 setting. O1 & O2 are standard CMOS logic outputs shown in figure 2A. These outputs are ideal to replace functions often provided by DIP switches. In addition, they can be used to drive other standard CMOS logic controlled parts that need an occasional setting change. VDD OUTPUTS O1 & O2 P IN S GND Figure 2A. Logic Outputs O1 & O2. Detail Programmable Potentiometer Operation The actual structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of connected resistor segments, with an array of analog switches that act as the wiper connection to several points along the resistor array. The number of points is the resolution of the device. For example, the AD5232 has 256 connection points allowing it to provide better than 0.5% setability resolution. Figure 3 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. The SWA and SWB will always be ON while one of the switches SW(0) to SW(2N-1) will be ON one at a time depending upon the resistance step decoded from the Data Bits. Note there are two 50 ohm wiper resistances, RW. The resistance contributed by RW must be accounted for in the output resistance. At terminals A-to-wiper, RW is the sum of the resistances of SWA and SWX. Similarly, RW is the sum of the resistances SWB and SWX at terminals B-to-Wiper. SW A Using Additional internal Nonvolatile EEMEM The AD523x family of devices contains additional internal user storage registers (EEMEM) for saving constants and other 8-bit data. Table 6 provides an address map of the internal storage registers shown in the functional block diagrams as EEMEM1, EEMEM2, … EEMEMn, and bytes of USER EEMEM. S W (2 N -1 ) RD AC W IP E R WX RS S W (2 N -2 ) R E G IS T E R Table 6: EEMEM Address Map & EEMEM EEMEM Contents of each device Address EEMEM(ADDR) (ADDR) AX DECO D ER RS S W (1 ) AD5231 (16B) AD5232 (8B) AD5233 (8B) 0000 RDAC RDAC1 RDAC1 0001 O1 & O2 RDAC2 RDAC2 0010 USER 1 USER 1 RDAC3 0011 USER 2 USER 2 RDAC4 0100 USER 3 USER 3 O1 & O2 0101 USER 4 USER 4 USER 1 TEST CIRCUITS *** *** *** *** 1111 USER 14 USER 14 USER 11 Figures X7 to X15 define the test conditions used in the product specification's table. NOTES: 1. RDAC data stored in EEMEM locations are transferred to their corresponding RDAC REGISTER at Power ON, or when the following instructions are executed Inst#1 and Inst#8. 2. O1 & O2 data stored in EEMEM locations are transferred to their corresponding DIGITAL REGISTER at Power ON, or when the following instructions are executed Inst#1 and Inst#8. 3. USER data are internal nonvolatile EEMEM registers available to store and retrieve constants using Inst#3 and Inst#9 respectively. 4. AD5231 EEMEM locations are 2 bytes each (16-bits) of data, while the AD5232 & AD5233 are 1 byte each (8-bits). RS S W (0 ) R S = R AB / N D IG IT A L C IR C U IT R Y O M IT T E D F O R C L A R IT Y SW B BX Figure 3. Equivalent RDAC structure Figure X7. Potentiometer Divider Nonlinearity error test circuit (INL, DNL) REV PrF 12 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 Figure X8. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure X14. Incremental ON Resistance Test Circuit Figure X9. Wiper Resistance test Circuit Figure X15. Common Mode Leakage current test circuit TYPICAL PERFORMANCE GRAPHS TBD Figure X10. Power supply sensitivity test circuit (PSS, PSSR) Figure X11. Inverting Gain test Circuit Figure X12. Non-Inverting Gain test circuit Figure X13. Gain Vs Frequency test circuit REV PrF 13 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected] PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) REV PrF 14 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; [email protected]