[AK4254] AK4254 Capacitor-less Video Amp with 7:2 Video Switch GENERAL DESCRIPTION The AK4254 is a 2ch Video AMP with 7:2 video switch, input clamp circuit, LPF and charge pump circuit. The integrated charge pump circuit can generate the negative power supply and remove the output coupling capacitor. The AK4254 suits Car Navigation system. The AK4254 is offered in a space saving 30pin VSOP package. FEATURES 1. Video Section • Composite Signal Inputs/Output • Selector for 7 inputs and 2 outputs • Video Driver for Composite Signal Output (+6dB) • On-Chip Sync-tip Clamp Circuit • 6MHz Low Pass Filter • Charge pump circuit for negative power supply • Parallel I/F or Serial µP I/F (I2C, 3-wires serial) 2. Power Supply: 2.7V ~ 3.6V 3. Ta=-40 ∼ +85°C 4. Package: 30pin VSOP 0.1uF VIN1 0.1uF VIN2 0.1uF VIN3 0.1uF VIN4 0.1uF VIN5 0.1uF VIN6 0.1uF VIN7 SW1 LPF +6dB VOUT1 Sync-tip Clamp SW2 AVDD AVSS LPF +6dB TEST VOUT2 PDN P/S I2C/SEL22 Clock CDTI/SDA/SEL21 CCLK/SCL/SEL20 CSN/SEL12 Control Clock Generator Generator I/F CAD1/SEL11 Charge Charge CAD0/SEL10 Pump Pump CVDD2 CP2 CN2 CVEE2 CVSS2 1uF CVSS1 1uF CVEE1 1uF CP1 CN1 CVDD1 1uF Figure 1. Block Diagram MS0586-E-01 2007/08 -1- [AK4254] ■ Ordering Guide AK4254VF AKD4254 -40 ∼ +85°C 30pin VSOP Evaluation board for AK4254 ■ Pin Layout CVDD1 1 30 CVDD2 CP1 2 29 CP2 CN1 3 28 CN2 CVSS1 4 27 CVSS2 CVEE1 5 26 CVEE2 VOUT1 6 25 VOUT2 AVDD 7 24 PDN AVSS 8 23 I2C/SEL22 TEST 9 22 CDTI/SDA/SEL21 P/S 10 21 CCLK/SCL/SEL20 VIN1 11 20 CSN/SEL12 VIN2 12 19 CAD1/SEL11 VIN3 13 18 CAD0/SEL10 VIN4 14 17 VIN7 VIN5 15 16 VIN6 AK4254 Top View MS0586-E-01 2007/08 -2- [AK4254] PIN/FUNCTION No. 1 Pin Name CVDD1 I/O - 2 CP1 O 3 CN1 I 4 CVSS1 - 5 CVEE1 O 6 7 8 VOUT1 AVDD AVSS O - 9 TEST I 10 P/S I 11 12 13 14 15 16 17 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 CAD0 SEL10 CAD1 SEL11 I I I I I I I I I I I CSN I SEL12 CCLK SCL SEL20 CDTI SDA SEL21 I I I I I I/O I I2C I SEL22 I 18 19 20 21 22 23 Function Charge Pump Power Supply pin, 2.7V∼3.6V Positive Charge Pump Capacitor Terminal 1 Pin. Connect to CN1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Negative Charge Pump Capacitor Terminal 1 Pin Connect to CP1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Charge Pump Ground Pin, 0V Connect to VEE1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CVSS1 pin. Non polarity capacitors can also be used. Negative Voltage Output Pin for Video Amplifier 1 Connect to CVSS1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CVSS1 pin. Non polarity capacitors can also be used. Video Output #1 Pin Analog Power Supply Pin, 2.7V∼3.6V Analog Ground Pin, 0V Test Pin This pin should be connected to AVSS. Parallel/Serial Control Mode Pin “L”: Serial Control Mode, “H”: Parallel Control Mode Video Input #1 Pin Video Input #2 Pin Video Input #3 Pin Video Input #4 Pin Video Input #5 Pin Video Input #6 Pin Video Input #7 Pin Chip Address 0 in Serial Control Mode Input Selector 1 Control #0 Pin in Parallel Control Mode Chip Address 1 in Serial Control Mode Input Selector 1 Control #1 Pin in Parallel Control Mode Chip Select Pin in Serial Control Mode, I2C pin = “L” This pin should be connected to AVSS in Serial Control Mode. I2C pin =“H” Input Selector 1 Control #2 Pin in Parallel Control Mode. Control Data Clock Pin in Serial Control Mode, I2C pin = “L” Control Data Clock Pin in Serial Control Mode, I2C pin = “H” Input Selector 2 Control #0 Pin in Parallel Control Mode Control Data Input Pin in Serial Control Mode, I2C pin = “L” Control Data Pin in Serial Control Mode, I2C pin = “H” Input Selector 2 Control #1 Pin in Parallel Control Mode. Control Mode Select Pin in Serial Control Mode “L”: 3-wire Serial Mode, “H”: I2C Bus mode Input Selector 2 Control #2 Pin in Parallel Control Mode MS0586-E-01 2007/08 -3- [AK4254] No. Pin Name I/O Function Power-Down Mode Pin 24 PDN I When at “L”, the AK4254 is in the power-down mode and held in reset, the AK4254 must always be reset upon power-up in Serial Control Mode (P/S pin= “L”). 25 VOUT2 O Video Output #2 Pin. Negative Voltage Output Pin for Video Amplifier 2 Connect to CVSS2 with a 1.0μF capacitor that has the low ESR (Equivalent Series 26 Resistance) over all temperature range. When this capacitor has the polarity, the CVEE2 O positive polarity pin should be connected to the CVSS2 pin. Non-polarity capacitors can also be used. Charge Pump Ground Pin, 0V Connect to CVEE2 with a 1.0μF capacitor that has the low ESR (Equivalent Series 27 CVSS2 Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CVSS2 pin. Non-polarity capacitors can also be used. Negative Charge Pump Capacitor Terminal 2 Pin Connect to CP2 with a 1.0μF capacitor that has the low ESR (Equivalent Series 28 CN2 I Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP2 pin. Non polarity capacitors can also be used. Positive Charge Pump Capacitor Terminal 2 Pin Connect to CN2 with a 1.0μF capacitor that has the low ESR (Equivalent Series 29 CP2 O Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP2 pin. Non polarity capacitors can also be used. 30 CVDD2 Charge Pump Power Supply Pin, 2.7V∼3.6V Note: All digital input pins (CADO/SEL10, CADT/SEL11, CSN/SEL12, CCLK/SCL/SEL20, CDTI/SDA/SEL21, I2C/SEL22) must not be left floating. ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name VIN1-7 CSN/SEL12 Setting These pins should be open. These pins should be connected to AVDD or AVSS. MS0586-E-01 2007/08 -4- ASAHI KASEI [AK4254] ABSOLUTE MAXIMUM RATINGS (AVSS=CVSS1=CVSS2=0V; Note: 1) Parameter Power Supply (Note: 2) Symbol AVDD CVDD1 CVDD2 IIN VIN min -0.3 -0.3 -0.3 -0.3 max 4.0 4.0 4.0 ±10 AVDD+0.3 or 4.0 Units V V V mA V Input Current (any pins except for supplies) Input Voltage (Note: 3) (VIN1-7, I2C/SEL22, CDTI/SDA/SEL21, CCLK/SCL/SEL20, CSN/SEL12, CAD1/SEL11, CAD0/SEL10, PDN, P/S pins) Ambient Operating Temperature Ta -40 85 °C Storage Temperature Tstg -65 150 °C Note: 1. All voltages are with respect to ground. Note: 2. AVSS, CVDSS1 and CVSS2 must be connected to the same analog ground plane. Note: 3. The external pull-up resistors at the SDA and SCL pins should be connected to the maximum voltage or less. Max is smaller value between AVDD+0.3V and 4.0V. The voltage must not be applied to the CN1 and CN2 pins. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=CVSS1=CVSS2=0V; Note: 1) Parameter Symbol Min Typ Power Supply (Note: 4) AVDD 2.7 3.0 CVDD1, CVDD2 AVDD Note: 4. AVDD, CVDD1 and CVDD2 must be the same voltage. max 3.6 Units V V typ - max 30%AVDD 0.4 Units V V V - ± 10 μA *AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. DIGITAL CHARACTERISTICS (Ta = -40∼85°C; AVDD=CVDD1=CVDD2=2.7V∼3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%AVDD Low-Level Input Voltage VIL Low-Level Output Voltage VOL (SDA pin: Iout= 3mA) Input Leakage Current Iin - MS0586-E-01 2007/08 -5- ASAHI KASEI [AK4254] ANALOG CHARACTERISTICS (Ta = 25°C; AVDD=CVDD1=CVDD2=3.0V; unless otherwise specified. Note: 5, Note: 6) Parameter Conditions min Gain Input=0.3Vp-p, 100kHz 5.3 Frequency Response Response at 6MHz -2.0 Input=0.3Vpp, Sin Wave Response at 27MHz (0dB at 100kHz) Group Delay Distortion |GD3MHz - GD6MHz| Dynamic Output Signal f=100kHz, maximum with distortion < 1.0%. 2.52 Inter channel Isolation f=4.43MHz, 1Vp-p input S/N Reference Level = 0.7Vp-p, BW= 100kHz to 6MHz. Differential Gain 0.7Vpp 5steps modulated staircase. Chrominance & burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. Chrominance & burst are 280mVpp, 4.43MHz. Load Resistance R1+R2 (Note: 9) 140 Load Capacitance C1 (Note: 9) C2 (Note: 9) Power Supply Current AVDD+CVDD1+CVDD2 Normal Operation (PDN pin = “H”, Note: 7) AVDD+CVDD1+CVDD2 Power-Down Mode (PDN pin = “L”, Note: 8) typ 6 -40 max 6.7 +2.0 -20 Units dB dB dB 10 100 65 65 - ns Vpp dB dB +0.4 - % +2.5 - Degree 150 400 15 Ω pF pF 20 30 mA 10 100 μA Note: 5. Video analog characteristics are measured at the pin directly. Note: 6. Input Sync Tip Level=-0.43V∼-0.14V (It is the difference with Pedestal Level and Sync Tip Level.) Horizontal Line Sync Pulse=4.0μs ∼5.4μs, Equalizing Pulse=2.0μs ∼2.7μs, Serration Pulse=4.0μs ∼5.4μs Note: 7. VIN Black level input, no load Note: 8. All digital input pins (P/S, I2C/SEL22, CDTI/SDA/SEL21, CCLK/SCL/SEL20, SN/SEL12, CAD1/SEL11, CAD0/SEL10) are held at AVSS. Note: 9. Refer to the Figure 2. R1 75 Ω VOUT R2 75 Ω C2 max: 15pF (C2) C1 max: 400pF (C1) Figure 2. Load Resistance R1+R2 and Load Capacitance C1/C2 MS0586-E-01 2007/08 -6- ASAHI KASEI [AK4254] SWITCHING CHARACTERISTICS (Ta =-40∼85°C; AVDD=CVDD1=CVDD2=2.7V∼3.6V; CL = 20pF) Parameter Symbol Min typ max Units Control Interface Timing (3-wire Serial mode) tPDCS 150 ns PDN “↑” to CSN “↓” tCCK 200 ns CCLK Period tCCKL 80 ns CCLK Pulse Width Low tCCKH 80 ns Pulse Width High tCDS 40 ns CDTI Setup Time tCDH 40 ns CDTI Hold Time tCSW 150 ns CSN “H” Time tCSS 50 ns CSN “↓” to CCLK “↑” tCSH 50 ns CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): SCL Clock Frequency fSCL 400 kHz PDN “↑” to SDA “↓” @SCL = “H” tPDSD 1.3 μs Bus Free Time Between Transmissions tBUF 1.3 μs Start Condition Hold Time tHD:STA 0.6 μs (Prior to first clock pulse) Clock Low Time tLOW 1.3 μs Clock High Time tHIGH 0.6 μs Setup Time for Repeated Start Condition tSU:STA 0.6 μs SDA Hold Time from SCL Falling (Note: 10) tHD:DAT 0 μs SDA Setup Time from SCL Rising tSU:DAT 0.1 μs Rise Time of Both SDA and SCL Lines tR 0.3 μs Fall Time of Both SDA and SCL Lines tF 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 μs Pulse Width of Spike Noise tSP 0 50 ns Suppressed by Input Filter Capacitive load on bus Cb 400 pF Reset Timing tPD 150 ns PDN Pulse Width (Note: 11) Note: 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note: 11. In Serial Control Mode (P/S pin= “L”), it is recommended that the AK4254 is powered up at the PDN pin=“L”. In Parallel Control Mode, resetting by the PDN pin = “L” is not needed when power up. Note: 12. I2C is a registered trademark of Philips Semiconductors. MS0586-E-01 2007/08 -7- ASAHI KASEI [AK4254] ■ Timing Diagram VIH PDN VIL tPDCS VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS C0 C1 CDTI A4 R/W VIH VIL WRITE Command Input Timing (3-wire Serial mode) tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL WRITE Data Input Timing (3-wire Serial mode) VIH PDN VIL tPDSD VIH SDA VIL tLOW tR tHIGH tF VIH SCL VIL tHD:STA tHD:DAT Start tSU:DAT tSU:STA Start I2C Bus Mode Timing 1 MS0586-E-01 2007/08 -8- ASAHI KASEI [AK4254] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT Start tSU:DAT tSU:STA tSU:STO Start Stop I2C Bus Mode Timing 2 tPD VIH PDN VIL Power down & Reset timing MS0586-E-01 2007/08 -9- ASAHI KASEI [AK4254] OPERATION OVERVIEW ■ System Reset In Serial Control Mode (P/S pin= “L”), it is recommended that AK4254 is powered up when the PDN pin= “L”. If the AK4254 is powered up when the PDN pin = “H”, the AK4254 should be reset by the PDN pin = “L” after power up. The control registers are initialized to their default values by resetting. In Parallel Control Mode, resetting by the PDN pin = “L” is not needed when power up. ■ Parallel Control Mode (P/S pin = “H”) The AK4524 is in Parallel Control Mode at P/S pin = “H”. When the AK4524 is in Parallel Control Mode, all registers can not be accessed. Mode Power Down mode Normal mode PDN pin L H H SEL12-10 pin x “LLL” Except for “LLL” CVEE1 pin GND GND -CVDD1 VOUT1 pin GND GND Video signal output (x: Don’t Care) Table 1. VOUT1 mode setting (Parallel Control Mode) Mode Power Down mode Normal mode PDN pin L H H SEL22-20 pin x “LLL” Except for “LLL” CVEE2 pin GND GND -CVDD1 VOUT2 pin GND GND Video signal output (x: Don’t Care) Table 2. VOUT2 mode setting (Parallel Control Mode) (a) Power Down mode (PDN pin= “L”) The AK4524 is in Power Down mode at the PDN pin = “L”. When the AK4524 is in the Power Down mode, the VOUT1-2 outputs are “GND”. (b) Normal mode (PDN pin= “H”) The AK4524 have 7:2 video switches. In Parallel Control Mode, the each input of VOUT1-2 is set by SEL12-10 pins and SEL22-20 pins. SEL12 pin SEL11 pin SEL10 pin VOUT1 pin L L L Off Note: 13) L L H VIN1 L H L VIN2 L H H VIN3 H L L VIN4 H L H VIN5 H H L VIN6 H H H VIN7 Note: 13. When the input setting is “Off”, VOUT1 output is “GND”. Table 3. Input Selector 1 (Parallel Control Mode) MS0586-E-01 2007/08 - 10 - ASAHI KASEI [AK4254] SEL22 pin SEL21 pin SEL20 pin VOUT2 pin L L L Off Note: 14) L L H VIN1 L H L VIN2 L H H VIN3 H L L VIN4 H L H VIN5 H H L VIN6 H H H VIN7 Note: 14. When the input setting is “Off”, VOUT2 output is “GND”. Table 4. Input Selector 2 (Parallel Control Mode) ■ Serial Control Mode (P/S pin = “L”) The AK4524 is in Serial Control Mode at P/S pin = “L”. Mode Power Down mode PDN pin L H Normal mode H SEL 12-10 bit x “000” Except for “000” CVEE1 pin GND GND VOUT1 pin GND GND -CVDD1 Video signal output (x: Don’t Care) Table 5. VOUT1 mode setting (Serial Control Mode) Mode Power Down mode PDN pin L H Normal mode H SEL 22-20 bit x “000” Except for “000” CVEE2 pin GND GND VOUT2 pin GND GND -CVDD1 Video signal output (x: Don’t Care) Table 6. VOUT2 mode setting (Serial Control Mode) (a) Power Down mode (PDN pin= “L”) When PDN pin =“L”, the register is reset and the AK4254 is in Power Down mode. When the AK4524 is in the Power Down mode, the VOUT1-2 outputs are “GND”. (b) Normal mode (PDN pin= “H”) The AK4524 have 7:2 video switches. In the Serial Control Mode, the each input of VOUT1-2 is set by SEL12-10 bits and SEL22-20 bits. SEL12 bit SEL11 bit SEL10 bit VOUT1 pin 0 0 0 Off Note: 15) (default) 0 0 1 VIN1 0 1 0 VIN2 0 1 1 VIN3 1 0 0 VIN4 1 0 1 VIN5 1 1 0 VIN6 1 1 1 VIN7 Note: 15. When the input setting is “Off”, VOUT1 output is “GND”. Table 7. Input Selector 1 (Serial Control Mode) MS0586-E-01 2007/08 - 11 - ASAHI KASEI [AK4254] SEL22 bit SEL21 bit SEL20 bit VOUT2 pin 0 0 0 Off Note: 16) (default) 0 0 1 VIN1 0 1 0 VIN2 0 1 1 VIN3 1 0 0 VIN4 1 0 1 VIN5 1 1 0 VIN6 1 1 1 VIN7 Note: 16. When the input setting is “Off”, VOUT2 output is “GND”. Table 8. Input Selector 2 (Serial Control Mode) ■ Video Block The Video Amp has drivability for a load resistance of 150Ω. The AK4254 has composite input and output with low pass filter (LPF). Internal negative power supply circuit supplies the negative voltage to the video amp and the video amp 0V output is used for a pedestal level. Therefore, the output coupling capacitor can be removed. The negative power supply circuit needs capacitors of Ca and Cb with 1.0μ, which should have the low ESR (Equivalent Series Resistance). When those capacitors have the polarity, each positive polarity pins should be connected to CP and VSS side. The negative power supply circuit generates the negative voltage to use the clock that corresponds to the input video signal. When there is no video input signal and the negative voltage is insufficient (CVEE > -0.8V) in case of low quality input signal (Note: 17), the negative power supply circuit generates the negative voltage by using the internal oscillator circuit. The VOUT outputs –0.6V(typ) when there is no video signal input. Note: 17. Low quality video signal has the following characteristics. Input Sync Tip Level= -0.43V~ -0.14V (from the pedestal voltage) Horizontal Line Sync Pulse=4.0μs ∼5.4μs, Equalizing Pulse=2.0μs ∼2.7μs, Serration Pulse=4.0μs ∼5.4μs AK4254 CVDD1 Charge Pump CP1 CN1 Negative Power CVSS1 (+) 1uF Cb CVEE1 1uF (+) Ca Figure 3. Negative Power Supply Circuit MS0586-E-01 2007/08 - 12 - ASAHI KASEI [AK4254] AK4254 75Ω VOUT1 (VOUT2) 75Ω 0V Figure 4. Video Signal Output ■ Serial Interface The AK4254 can select 3-wire Serial mode (I2C pin = “L”) or I2C Bus mode (I2C pin =“H”). 1.3-wire Serial mode (I2C pin = “L”) Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI pins). The data on this interface consists of a 2-bit Chip address (C1 and C2 are set by CAD1, CAD0pin), Read/Write (Fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). If the Chip address matches the setting of the CAD1 pin and CAD0pin, the AK4254 operation is executed. Each bit is clocked in on the rising edge (“↑”) of CCLK. Address and data are latched on the 16th CCLK rising edge (“↑”) after CSN falling edge (“↓”). CSN should be set to “H” once after 16 CCLKs for each address. Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by the PDN pin = “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1,C0: R/W: A4-A0: D7-D0: Chip Address: (C1= CAD1, C0 = CAD0) READ/WRITE (Fixed to “1”: WRITE) Register Address Control Data Figure 5. 3-wire Serial mode I/F timing MS0586-E-01 2007/08 - 13 - ASAHI KASEI [AK4254] 2. I2C Bus mode The AK4254 supports the fast-mode I2C-bus (max: 400kHz). 2-1. WRITE operations Figure 6 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates the START condition (Figure 12). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as “00100”. The next bits are CAD0-1 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0-1 pins) sets these device address bits(Figure 7). If the slave address matches that of the AK4254, the AK4254 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 13). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4254. The format is MSB first, and those most significant 7-bits are fixed to zeros (Figure 8). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 9). The AK4254 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 12). The AK4254 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4254 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 1-bit address counter is incremented by one, and the next data is automatically taken into the next address. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 14) except for the START and STOP conditions. S T A R T SDA S T O P R/W= "0" Slave S Address Sub Address(n) Data(n) A C K Data(n+1) A C K A C K Data(n+x) A C K P A C K A C K Figure 6. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 CAD1 CAD0 R/W Figure 7. The First Byte (Those CAD1/0 should match with CAD1/0 pins) 0 0 0 0 0 0 0 A0 D2 D1 D0 Figure 8. The Second Byte D7 D6 D5 D4 D3 Figure 9. Byte Structure after the Second Byte MS0586-E-01 2007/08 - 14 - ASAHI KASEI [AK4254] 2-2. READ Operations (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4254. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 2-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 01H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4254 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. 2-2-1. CURRENT ADDRESS READ The AK4254 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4254 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4254 ceases transmission. S T A R T SDA S T O P R/W = "1" Slave S Address Data(n+1) Data(n) A C K Data(n+2) A C K A C K Data(n+x) A C K A C K P A C K Figure 10. CURRENT ADDRESS READ 2-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4254 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4254 ceases transmission. S T A R T SDA S T A R T R/W = "0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W = "1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 11. RANDOM ADDRESS READ MS0586-E-01 2007/08 - 15 - ASAHI KASEI [AK4254] SDA SCL S P start condition stop condition Figure 12. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 13. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 14. Bit Transfer on the I2C-Bus MS0586-E-01 2007/08 - 16 - ASAHI KASEI [AK4254] ■ Register Map Addr 00H 01H Register Name Input Selector Control (Reserved) D7 0 0 D6 SEL22 0 D5 SEL21 0 D4 SEL20 0 D3 0 0 D2 SEL12 0 D1 SEL11 0 D0 SEL10 0 D1 SEL11 0 D0 SEL10 0 The PDN pin = “L” resets the all registers to their default values. (Note: 18) “The “0” register should be written “0”, the “1” register should be written “1” data. (Note: 19) Do not write any data to the register except 00H. ■ Register Definitions Addr 00H Register Name Input Selector Control Default D7 0 0 D6 SEL22 0 D5 SEL21 0 SEL12-10: Input Selector 1 Control (Table 7) The default is “000” (VOUT1 output is “GND”). SEL22-20: Input Selector 2 Control (Table 8) The default is “000” (VOUT2 output is “GND”). MS0586-E-01 D4 SEL20 0 D3 0 0 D2 SEL12 0 2007/08 - 17 - ASAHI KASEI [AK4254] SYSTEM DESIGN Figure 15∼Figure 17 show the system connection diagram. An evaluation board (AKD4254) is available in order to allow an easy study on the layout of a surrounding circuit. 1u 1u + + 1 CVDD1 CVDD2 30 2 CP1 CP2 29 3 CN1 CN2 28 4 CVSS1 CVSS2 27 5 CVEE1 CVEE2 26 6 VOUT1 VOUT2 25 7 AVDD PDN 24 + 10u 8 AVSS SEL22 23 9 TEST SEL21 22 10 P/S SEL20 21 11 VIN1 SEL12 20 12 VIN2 SEL11 19 + 1u 1u 75 75 Video out Power Supply 3V + AK4254 Video out 0.1u 0.1u DSP or μP 0.1u Video in 0.1u 0.1u 0.1u 13 VIN3 SEL10 18 14 VIN4 VIN7 17 15 VIN5 VIN6 16 0.1u Video in 0.1u Figure 15. Typical Connection Diagram (Parallel Control Mode) 1u 1u + + 1 CVDD1 CVDD2 30 2 CP1 CP2 29 3 CN1 CN2 28 4 CVSS1 CVSS2 27 5 CVEE1 CVEE2 26 6 VOUT1 VOUT2 25 10u 0.1u + 7 AVDD PDN 24 8 AVSS I2C 23 9 TEST CDTI 22 10 P/S CCLK 21 11 VIN1 CSN 20 12 VIN2 CAD1 19 13 VIN3 CAD0 18 14 VIN4 VIN7 17 15 VIN5 VIN6 16 + 1u 1u 75 75 Video out Power Supply 3V + AK4254 Video out 0.1u DSP or μP 0.1u Video in 0.1u 0.1u 0.1u 0.1u 0.1u Video in Figure 16. Typical Connection Diagram (Serial Control Mode: 3-wire Serial mode) MS0586-E-01 2007/08 - 18 - ASAHI KASEI [AK4254] 1u 1u + + 1 CVDD1 CVDD2 30 2 3 CP1 CP2 29 CN1 CN2 28 4 5 CVSS1 CVSS2 27 CVEE1 CVEE2 26 Video out 10u 0.1u + + 1u 1u 75 75 Power Supply 3V + 6 VOUT1 7 8 VOUT2 25 AVDD PDN 24 AVSS I2C 23 9 TEST SDA 22 10 P/S SCL 21 11 VIN1 CSN 20 12 VIN2 CAD1 19 13 VIN3 CAD0 18 14 VIN4 VIN7 17 15 VIN5 VIN6 16 AK4254 Video out 0.1u DSP or μP 0.1u Video in 0.1u 0.1u 0.1u 0.1u 0.1u Video in Figure 17. Typical Connection Diagram (Serial Control Mode: I2C Bus mode) 1. Grounding and Power Supply Decoupling The AK4254 requires careful attention to power supply and grounding arrangements. AVDD, CVDD1 and CVDD2 are usually supplied from the system’s analog supply. AVSS, CVSS1 and CVSS2 of the AK4254 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4254 as possible, with the small value ceramic capacitor being the nearest. 2. Analog Inputs Usually the input signal is AC coupled using 0.1uF capacitor (Figure 15, Figure 16, Figure 17). 3. The notes for drawing the board Analog input and output pins should be as short as possible in order to avoid unwanted coupling into the AK4254. The unused pins should be open. 4. Video Output The AK4254 are on-chip 2ch video amp for drive 150Ω resistance. The gain of each amp is +6dB (typ) (Figure 1). MS0586-E-01 2007/08 - 19 - ASAHI KASEI [AK4254] PACKAGE 30pin VSOP (Unit: mm) 1.5MAX *9.7±0.1 0.3 30 16 15 1 0.22±0.1 7.6±0.2 5.6±0.1 A 0.15 +0.10 -0.05 0.65 0.12 M 0.45±0.2 +0.10 0.08 0.10 -0.05 1.2±0.10 Detail A NOTE: Dimension "*" does not include mold flash. MS0586-E-01 2007/08 - 20 - ASAHI KASEI [AK4254] MARKING AKM AK4254VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) REVISION HISTORY Date (YY/MM/DD) 07/02/20 07/08/10 Revision 00 01 Reason First Edition Spec change Page Contents 6 Spec change 7 Spec change 8 Error correct 18, 19 Interchannel Isolation: typ.50dB Æ typ.65dB Switching characteristics PDN “↑” to CSN “↓”: tPDCS was added PDN “↑” to SDA “↓” @SCL = “H”: tPDSD was added Timing diagram WRITE command input timing was changed. (tPDCS was added) I2C Bus mode timing1 was added. (tPDSD was added) System design Figure15, Figure16, Figure17 were revised. (CVSS1 and CVSS2 were connected to GND) MS0586-E-01 2007/08 - 21 - ASAHI KASEI [AK4254] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0586-E-01 2007/08 - 22 -