AD ADL5513-EVALZ 1 mhz to 4 ghz, 80 db logarithmic detector/controller Datasheet

1 MHz to 4 GHz, 80 dB
Logarithmic Detector/Controller
ADL5513
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DET
NC
NC
CLPF
NC
16
15
14
13
DET
DET
DET
DET
I
V
12 VOUT
VPOS 1
INHI 2
I
INLO 3
ADL5513
VPOS 4
SLOPE
CONTROL
BAND GAP
REFERENCE
V
11 VSET
10 COMM
GAIN
BIAS
5
6
7
8
NC
NC
NC
NC
9 TADJ
07514-001
Wide bandwidth: 1 MHz to 4 GHz
80 dB dynamic range (±3 dB)
Constant dynamic range over frequency
Stability over −40oC to +85oC temperature range: ±0.5 dB
Operating temperature range: −40oC to +125oC
Sensitivity: −70 dBm
Low noise measurement/controller output (VOUT)
Pulse response time: 21 ns/20 ns (fall/rise)
Single-supply operation: 2.7 V to 5.5 V @ 31 mA
Power-down feature: 1 mW @ 5 V
Small footprint LFCSP
Fabricated using high speed SiGe process
Figure 1.
APPLICATIONS
RF transmitter power amplifier linearization and gain/power
control
Power monitoring in radio link transmitters
RSSI measurement in base stations, WLAN, WiMAX, RADAR
GENERAL DESCRIPTION
The ADL5513 is a demodulating logarithmic amplifier, capable
of accurately converting an RF input signal to a corresponding
decibel-scaled output. It employs the progressive compression
technique over a cascaded amplifier chain, each stage of which
is equipped with a detector cell. The device can be used in either
measurement or controller modes. The ADL5513 maintains
accurate log conformance for signals up to 4 GHz. The input
dynamic range is typically 80 dB (referred to 50 Ω) with error less
than ±3 dB and 74 dB with error less than ±1 dB. The ADL5513
has 20 ns response time that enables RF burst detection to a
pulse rate of beyond 50 MHz. The device provides unprecedented
logarithmic intercept stability vs. ambient temperature conditions.
A supply of 2.7 V to 5.5 V is required to power the device. Current
consumption is 31 mA, and it decreases to 200 μA when the
device is disabled.
The ADL5513 can be configured to provide a control voltage to
a power amplifier or a measurement output from the VOUT pin.
Because the output can be used for controller applications,
special attention has been paid to minimize wideband noise. In
this mode, the setpoint control voltage is applied to the VSET pin.
The feedback loop through an RF amplifier is closed via VOUT,
the output of which regulates the amplifier output to a magnitude corresponding to VSET. The ADL5513 provides 0 V to
(VPOS − 0.1 V) output capability at the VOUT pin, suitable
for controller applications. As a measurement device, VOUT
is externally connected to VSET to produce an output voltage,
VOUT, that increases linear-in-dB with RF input signal amplitude.
The logarithmic slope is 21 mV/dB, determined by the VSET
interface. The intercept is −88 dBm (referred to 50 Ω, continuous wave input, 900 MHz) using the INHI input. These
parameters are very stable against supply and temperature
variations.
The ADL5513 is fabricated on a SiGe bipolar IC process and
is available in a 3 mm × 3 mm, 16-lead LFCSP package for the
−40°C to +125°C operating temperature range. A fully populated
evaluation board is available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADL5513
TABLE OF CONTENTS
Features .............................................................................................. 1
Setpoint Interface ....................................................................... 15
Applications ....................................................................................... 1
Description of Characterization ............................................... 15
Functional Block Diagram .............................................................. 1
Error Calculations ...................................................................... 16
General Description ......................................................................... 1
Revision History ............................................................................... 2
Adjusting Accuracy Through Choice of Calibration
Points............................................................................................ 16
Specifications..................................................................................... 3
Temperature Compensation of Output Voltage ..................... 17
Absolute Maximum Ratings............................................................ 7
Device Calibration ..................................................................... 18
ESD Caution .................................................................................. 7
Power-Down Functionality ....................................................... 18
Pin Configuration and Function Descriptions ............................. 8
Measurement Mode ................................................................... 19
Typical Performance Characteristics ............................................. 9
Setting the Output Slope in Measurement Mode .................. 19
Theory of Operation ...................................................................... 13
Controller Mode ......................................................................... 20
Applications Information .............................................................. 14
Constant Power Operation ....................................................... 20
Basic Connections ...................................................................... 14
Increasing the Dynamic Range of the ADL5513 ................... 22
Input Signal Coupling ................................................................ 14
Evaluation Board ............................................................................ 23
Output Filtering .......................................................................... 14
Outline Dimensions ....................................................................... 25
Output Interface ......................................................................... 15
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADL5513
SPECIFICATIONS
VS = 5 V, TA = 25°C, Z0 = 50 Ω, Pin INHI and Pin INLO are ac-coupled, continuous wave (CW) input, single-ended input drive, VOUT
tied to VSET, error referred to best-fit line (linear regression −20 to −40 dBm), unless otherwise noted. (Temperature adjust voltage
optimized for 85°C.)
Table 1.
Parameter
OVERALL FUNCTION
Maximum Input Frequency
FREQUENCY = 100 MHz
Output Voltage: High Power Input
Output Voltage: Low Power Input
±3.0 dB Dynamic Range
±1.0 dB Dynamic Range
±0.5 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation at TA = 25°C
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Input Impedance
FREQUENCY = 900 MHz
Output Voltage: High Power Input
Output Voltage: Low Power Input
±3.0 dB Dynamic Range
±1.0 dB Dynamic Range
±0.5 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation at TA = 25°C
Deviation vs. Temperature
Conditions
Min
Typ
1
PIN = −10 dBm
PIN = −50 dBm
1.50
0.64
PIN = −10 dBm
PIN = −30 dBm
PIN = −50 dBm
Deviation from output at TA = 25°C
25°C < TA < 85°C; PIN = −10 dBm
−40°C < TA < +25°C; PIN = −10 dBm
25°C < TA < 125°C; PIN = −10 dBm
25°C < TA < 85°C; PIN = −30 dBm
−40°C < TA < +25°C; PIN = −30 dBm
25°C < TA < 125°C; PIN = −30 dBm
+25°C < TA < +85°C; PIN = −50 dBm
−40°C < TA < +25°C; PIN = −50 dBm
25°C < TA < 125°C; PIN = −50 dBm
19.5
PIN = −10 dBm
PIN = −50 dBm
PIN = −10 dBm
PIN = −30 dBm
PIN = −50 dBm
Deviation from output at TA = 25°C
25°C < TA < 85°C; PIN = −10 dBm
−40°C < TA < +25°C; PIN = −10 dBm
25°C < TA < 125°C; PIN = −10 dBm
25°C < TA < 85°C; PIN = −30 dBm
−40°C < TA < +25°C; PIN = −30 dBm
25°C < TA < 125°C; PIN = −30 dBm
25°C < TA < 85°C; PIN = −50 dBm
−40°C < TA < +25°C; PIN = −50 dBm
25°C < TA < 125°C; PIN = −50 dBm
Rev. 0 | Page 3 of 28
1.63
0.79
75
64
58
6
−58
0.27
0.003
−0.14
+0.15/−0.33
+0.23/−0.43
0.8
+0.12/−0.31
±0.31
+0.74
+0.35/−0.18
+0.25/−0.47
+0.52/−0.24
21
−87
1.3/0.4
Max
Unit
4000
MHz
1.76
0.94
V
V
dB
dB
dB
dBm
dBm
dB
dB
dB
22.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV/dB
dBm
kΩ/pF
1.64
0.79
76
70
68
8
−62
0.2
0.002
0.34
V
V
dB
dB
dB
dBm
dBm
dB
dB
dB
+0.25/−0.3
+0.2/−0.53
+0.72/−0.1
+0.2/−0.3
+0.28/−0.37
0.7
+0.4/−0.36
+0.37/−0.5
+0.67/−0.28
dB
dB
dB
dB
dB
dB
dB
dB
dB
ADL5513
Parameter
Logarithmic Slope
Logarithmic Intercept
Input Impedance
FREQUENCY = 1900 MHz
Output Voltage: High Power Input
Output Voltage: Low Power Input
±3.0 dB Dynamic Range
±1.0 dB Dynamic Range
±0.5 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation at TA = 25°C
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Input Impedance
FREQUENCY = 2140 MHz
Output Voltage: High Power Input
Output Voltage: Low Power Input
±3.0 dB Dynamic Range
±1.0 dB Dynamic Range
±0.5 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation at TA = 25°C
Deviation vs. Temperature
Conditions
Min
PIN = −10 dBm
PIN = −50 dBm
PIN = −10 dBm
PIN = −30 dBm
PIN = −50 dBm
Deviation from output at TA = 25°C
25°C < TA < 85°C; PIN = −10 dBm
−40°C < TA < +25°C; PIN = −10 dBm
25°C < TA < 125°C; PIN = −10 dBm
25°C < TA < 85°C; PIN = −30 dBm
−40°C < TA < +25°C; PIN = −30 dBm
25°C < TA < 125°C; PIN = −30 dBm
25°C < TA < 85°C; PIN = −50 dBm
−40°C < TA < +25°C; PIN = −50 dBm
25°C < TA < 125°C; PIN = −50 dBm
PIN = −10 dBm
PIN = −50 dBm
PIN = −10 dBm
PIN = −30 dBm
PIN = −50 dBm
Deviation from output at TA = 25°C
25°C < TA < 85°C; PIN = −10 dBm
−40°C < TA < +25°C; PIN = −10 dBm
25°C < TA < 125°C; PIN = −10 dBm
25°C < TA < 85°C; PIN = −30 dBm
−40°C < TA < +25°C; PIN = −30 dBm
25°C < TA < 125°C; PIN = −30 dBm
25°C < TA < 85°C; PIN = −50 dBm
−40°C < TA < +25°C; PIN = −50 dBm
25°C < TA < 125°C; PIN = −50 dBm
Logarithmic Slope
Logarithmic Intercept
Input Impedance
Rev. 0 | Page 4 of 28
Typ
21
−88
1.3/0.4
Max
Unit
mV/dB
dBm
kΩ/pF
1.66
0.80
75
70
68
8
−62
0.25
0.0012
0.52
V
V
dB
dB
dB
dBm
dBm
dB
dB
dB
+0.14/−0.41
+0.19/−0.51
0.9
+0.1/−0.38
+0.37/−0.26
0.83
+0.55/−0.3
+0.79/−0.16
+0.62/−0.41
21
−88
0.6/0.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV/dB
dBm
kΩ/pF
1.66
0.82
77
70
66
8
−62
0.33
0.02
0.23
V
V
dB
dB
dB
dBm
dBm
dB
dB
dB
±0.28
+0.2/−0.52
+0.7/−0.1
+0.15/−0.35
+0.24/−0.41
0.77
+0.2/−0.6
+0.1/−0.94
+0.8/−0.2
21
−89
0.5/0.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV/dB
dBm
kΩ/pF
ADL5513
Parameter
FREQUENCY = 2600 MHz
Output Voltage: High Power Input
Output Voltage: Low Power Input
±3.0 dB Dynamic Range
±1.0 dB Dynamic Range
±0.5 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation at TA = 25°C
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Input Impedance
FREQUENCY = 3.6 GHz
Output Voltage: High Power Input
Output Voltage: Low Power Input
±3.0 dB Dynamic Range
±1.0 dB Dynamic Range
±0.5 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation at TA = 25°C
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Input Impedance
SETPOINT INPUT
Nominal Range
Conditions
Min
PIN = −10 dBm
PIN = −50 dBm
PIN = −10 dBm
PIN = −30 dBm
PIN = −50 dBm
Deviation from output at TA = 25°C
25°C < TA < 85°C; PIN = −10 dBm
−40°C < TA < +25°C; PIN = −10 dBm
25°C < TA < 125°C; PIN = −10 dBm
25°C < TA < 85°C; PIN = −30 dBm
−40°C < TA < +25°C; PIN = −30 dBm
25°C < TA < 125°C; PIN = −30 dBm
25°C < TA < 85°C; PIN = −50 dBm
−40°C < TA < +25°C; PIN = −50 dBm
25°C < TA < 125°C; PIN = −50 dBm
PIN = −10 dBm
PIN = −50 dBm
PIN = −10 dBm
PIN = −30 dBm
PIN = −50 dBm
Deviation from output at TA = 25°C
25°C < TA < 85°C; PIN = −10 dBm
−40°C < TA < +25°C; PIN = −10 dBm
25°C < TA < 125°C; PIN = −10 dBm
25°C < TA < 85°C; PIN = −30 dBm
−40°C < TA < +25°C; PIN = −30 dBm
25°C < TA < 125°C; PIN = −30 dBm
25°C < TA < 85°C; PIN = −50 dBm
−40°C < TA < +25°C; PIN = −50 dBm
25°C < TA < 125°C; PIN = −50 dBm
Pin VSET
Log conformance error ≤ ±1 dB, RF input = 8 dBm
Log conformance error ≤ ±1 dB, RF input = −62 dBm
Logarithmic Scale Factor
Input Impedance
Rev. 0 | Page 5 of 28
Typ
Max
Unit
1.67
0.83
80
74
69
7
−67
0.33
0.02
0.01
V
V
dB
dB
dB
dBm
dBm
dB
dB
dB
+0.2/−0.4
+0.05/−0.68
+0.75/−0.05
+0.1/−0.37
+0.25/−0.4
0.8
+0.2/−0.6
±0.5
1.13
21
−89
0.4/0.6
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV/dB
dBm
kΩ/pF
1.74
0.84
76
62
58
1
−61
0.43
−0.05
−0.14
V
V
dB
dB
dB
dBm
dBm
dB
dB
dB
+0.32/−0.28
+0.27/−0.54
+0.58/−0.21
+0.3/−0.22
+0.38/−0.33
+0.67/−0.05
+0.41/−0.37
+0.41/−0.62
+0.8/−0.18
22.5
−87
0.5/0.4
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV/dB
dBm
kΩ/pF
2
0.58
47.1
40
V
V
dB/ V
kΩ
ADL5513
Parameter
OUTPUT INTERFACE
Voltage Swing
Capacitance Drive
Capacitance Drive
Current Source/Sink
Output Noise
PULSE RESPONSE TIME
Fall Time
Rise Time
Fall Time
Rise Time
Small Signal Video Bandwidth (or Envelope
Bandwidth)
TEMPERATURE ADJUST/POWER-DOWN
INTERFACE
Temperature Adjust Useful Range
Minimum Logic Level to Disable
Input Current
Enable Time
Disable Time
Input Impedance 1
POWER SUPPLY INTERFACE
Supply Voltage
Quiescent Current
Supply Current
1
Conditions
Pin VOUT
VSET = 0 V, RF input = open
VSET = 0.47 V, RF input = open
CLPF = open
CLPF = 20 pF
Output held at 1 V to 1% change
RF input = 100 MHz, 0 dBm
fNOISE = 100 kHz, CLPF = open
fNOISE = 100 kHz, CLPF = 1 nF
Input level = no signal to 0 dBm, 90% to 10%
CLPF = open, 1 µs pulse width
CLPF = open, 500 µs pulse width
CLPF = open, 1 µs pulse width
CLPF = open, 500 µs pulse width
CLPF = 1000 pF, 10 µs pulse width
CLPF = 1000 pF, 500 µs pulse width
CLPF = 1000 pF, 10 µs pulse width
CLPF = 1000 pF, 500 µs pulse width
CLPF = open, 3 dB video bandwidth
Min
Typ
Max
Unit
0.47
4.7
47
1
0.64/55
V
V
pF
nF
mA
145
82
nV/√Hz
nV/√Hz
21
5.5
20
20
4.2
5.5
3.2
4.3
10
ns
µs
ns
ns
µs
µs
µs
µs
MHz
0 to 1.3
VPOS − 0.3
31
200
V
V
mA
µA
84
ns
10.8
µs
165
ns
1.2
µs
13
kΩ
Pin TADJ
Logic high disables
Logic high TADJ = 0 V
Logic low TADJ = 4.7 V
PWDN low to VOUT at 100% final value, PWDN high
to VOUT at 10% final value
CLPF = open, RF input = 0 dBm, 100 MHz,
1 µs pulse width
CLPF = 1000 pF, RF input = 0 dBm, 100 MHz,
1 µs pulse width
CLPF = open, RF input = 0 dBm, 100 MHz,
1 µs pulse width
CLPF = 1000 pF, RF input = 0 dBm, 100 MHz,
1 µs pulse width
TADJ = 0.9 V, sourcing 70 µA
Pin VPOS
2.7
25°C, RF input = −55 dBm
When disabled
See the Temperature Compensation of Output Voltage section.
Rev. 0 | Page 6 of 28
5.5
31
<0.2
V
mA
mA
ADL5513
ABSOLUTE MAXIMUM RATINGS
ESD CAUTION
Table 2.
Parameter
Supply Voltage, VPOS
VSET Voltage
Input Power (Single-Ended, Re: 50 Ω)
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.5 V
0 V to VPOS
20 dBm
220 mW
79.3°C/W
150°C
−40°C to +125°C
−65°C to +150°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 28
ADL5513
12 VOUT
INHI 2
ADL5513
11 VSET
INLO 3
TOP VIEW
(Not to Scale)
9 TADJ
10 COMM
NC 8
NC 5
VPOS 4
NC 7
PIN 1
INDICATOR
NC 6
VPOS 1
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS INTERNALLY
CONNECTED TO COMM; SOLDER
TO A LOW IMPEDANCE GROUND
PLANE.
07514-002
14 CLPF
13 NC
16 NC
15 NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 4
2
3
5, 6, 7, 8,
13, 15, 16
9
Mnemonic
VPOS
INHI
INLO
NC
Description
Positive Supply Voltage, 2.7 V to 5.5 V.
RF Input. AC-coupled RF input.
RF Common for INHI. AC-coupled RF common.
No Connect. These pins can be left open or be soldered to a low impedance ground plane.
TADJ
10
11
12
14
COMM
VSET
VOUT
CLPF
15 (EPAD)
Exposed Paddle
(EPAD)
Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by
applying a specified voltage to the pin. The TADJ pin has dual functionality as a power-down pin, PWDN.
Applying a voltage of VPOS − 0.3 V disables the device.
Device Common.
Setpoint Input for Operation in Controller Mode. To operate in RSSI mode short VSET to VOUT.
Logarithmic/Error Output.
Loop Filter Capacitor Pin. In measurement mode, this capacitor pin sets the pulse response time and video
bandwidth. In controller mode, the capacitance on this node sets the response time of the error
amplifier/integrator.
Internally connected to COMM; solder to a low impedance ground plane.
Rev. 0 | Page 8 of 28
ADL5513
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.2
2.5
2.0
2.0
2.0
2.0
1.8
1.5
1.8
1.5
1.6
1.0
1.6
1.0
1.4
0.5
1.4
0.5
1.2
0
1.2
0
1.0
–0.5
1.0
–0.5
0.8
–1.0
–50
–40
–30
–20
PIN (dBm)
–10
0
–2.5
0.2
–3.0
10
0
–70
–2.5
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
2.4
3.0
2.5
2.2
2.5
2.0
2.0
2.0
2.0
1.8
1.5
1.8
1.5
1.6
1.0
1.6
1.0
1.4
0.5
1.4
0.5
1.2
0
1.2
0
1.0
–0.5
1.0
–0.5
0.8
–1.0
0.8
–1.5
0.6
–2.0
0.4
–2.5
0.2
+25°C
–40°C
+85°C
+125°C
0.4
0.2
0
–70
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
VOUT (V)
3.0
2.2
ERROR (dB)
2.4
0.6
0
–70
Figure 4. VOUT and Log Conformance vs. Input Amplitude at 900 MHz,
Typical Device, VTADJ = 0.86 V
–1.0
+25°C
–40°C
+85°C
+125°C
–1.5
–2.0
–2.5
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
Figure 7. VOUT and Log Conformance vs. Input Amplitude at 900 MHz,
Multiple Devices, VTADJ = 0.86 V
2.4
3.0
2.5
2.2
2.5
2.0
2.0
2.0
2.0
1.8
1.5
1.8
1.5
1.6
1.0
1.6
1.0
1.4
0.5
1.4
0.5
1.2
0
1.2
0
1.0
–0.5
1.0
–0.5
0.8
–1.0
0.6
+25°C
–40°C
+85°C
+125°C
0.4
0.2
0
–70
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
VOUT (V)
3.0
2.2
ERROR (dB)
2.4
0.8
–1.5
0.6
–2.0
0.4
–2.5
0.2
–3.0
10
0
–70
07514-007
VOUT (V)
–2.0
Figure 6. VOUT and Log Conformance vs. Input Amplitude at 100 MHz,
Multiple Devices, VTADJ = 0.89 V
07514-004
VOUT (V)
Figure 3. VOUT and Log Conformance vs. Input Amplitude at 100 MHz,
Typical Device, VTADJ = 0.89 V
–1.5
07514-005
–60
0.4
ERROR (dB)
0
–70
0.6
–2.0
07514-006
0.2
–1.5
Figure 5. VOUT and Log Conformance vs. Input Amplitude at 1900 MHz,
Typical Device, VTADJ = 0.80 V
ERROR (dB)
+25°C
–40°C
+85°C
+125°C
0.4
–1.0
+25°C
–40°C
+85°C
+125°C
–1.0
+25°C
–40°C
+85°C
125°C
–1.5
–2.0
–2.5
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
07514-010
0.6
0.8
ERROR (dB)
2.4
2.5
VOUT (V)
3.0
2.2
ERROR (dB)
2.4
07514-003
VOUT (V)
VPOS = 5 V; TA = +25°C, −40°C, +85°C, +125°C; CLPF = 0.1 μF, error is calculated by using the best-fit line between PIN = −20 dBm and PIN =
−40 dBm at the specified input frequency, unless otherwise noted.
Figure 8. VOUT and Log Conformance vs. Input Amplitude at 1900 MHz,
Multiple Devices, VTADJ = 0.80 V
Rev. 0 | Page 9 of 28
3.0
2.2
2.5
2.0
2.0
2.0
2.0
1.8
1.5
1.8
1.5
1.6
1.0
1.6
1.0
1.4
0.5
1.4
0.5
1.2
0
1.2
0
1.0
–0.5
1.0
–0.5
0.8
–1.0
0.8
–1.5
0.6
–2.0
0.4
–2.5
0.2
–50
–40
–30
–20
PIN (dBm)
–10
0
–2.5
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
Figure 12. VOUT and Log Conformance vs. Input Amplitude at 2140 MHz,
Multiple Devices, VTADJ = 0.84 V
2.4
3.0
2.5
2.2
2.5
2.0
2.0
2.0
2.0
1.8
1.5
1.8
1.5
1.6
1.0
1.6
1.0
1.4
0.5
1.4
0.5
1.2
0
1.2
0
1.0
–0.5
1.0
–0.5
0.8
–1.0
0.8
–1.5
0.6
–2.0
0.4
–2.5
0.2
0.6
+25°C
–40°C
+85°C
125°C
0.4
0.2
0
–70
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
VOUT (V)
3.0
2.2
ERROR (dB)
2.4
0
–70
07514-009
Figure 10. VOUT and Log Conformance vs. Input Amplitude at 2600 MHz,
Typical Device, VTADJ = 0.83 V
–1.0
+25°C
–40°C
+85°C
125°C
–1.5
–2.0
–2.5
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
Figure 13. VOUT and Log Conformance vs. Input Amplitude at 2600 MHz,
Multiple Devices, VTADJ = 0.83 V
3.0
2.4
3.0
2.2
2.5
2.2
2.5
2.0
2.0
2.0
2.0
1.8
1.5
1.8
1.5
1.6
1.0
1.6
1.0
1.4
0.5
1.4
0.5
1.2
0
1.2
0
1.0
–0.5
1.0
–0.5
0.8
–1.0
0.8
–1.5
0.6
–2.0
0.4
–2.5
0.2
+25°C
–40°C
+85°C
125°C
0.4
0.2
0
–70
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
0
–70
07514-013
0.6
ERROR (dB)
2.4
VOUT (V)
VOUT (V)
Figure 9. VOUT and Log Conformance vs. Input Amplitude at 2140 MHz,
Typical Device, VTADJ = 0.84 V
VOUT (V)
0
–70
Figure 11. VOUT and Log Conformance vs. Input Amplitude at 3600 MHz,
Typical Device, VTADJ = 0.90 V
07514-011
–60
–3.0
10
ERROR (dB)
0
–70
–2.0
07514-012
0.2
–1.5
ERROR (dB)
0.4
–1.0
+25°C
–40°C
+85°C
125°C
–1.0
+25°C
–40°C
+85°C
125°C
–1.5
–2.0
–2.5
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
–3.0
10
07514-016
+25°C
–40°C
+85°C
125°C
0.6
ERROR (dB)
2.4
2.5
VOUT (V)
3.0
2.2
ERROR (dB)
2.4
07514-008
VOUT (V)
ADL5513
Figure 14. VOUT and Log Conformance vs. Input Amplitude at 3600 MHz,
Multiple Devices, VTADJ = 0.90 V
Rev. 0 | Page 10 of 28
ADL5513
100k
1k
10
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1k
100
10
1k
07514-015
100
10k
1.6
1.2
4
3
1.0
0.8
2
PIN = –10dBm
4
1.4
PIN = –20dBm
1.2
PIN = –30dBm
1.0
PIN = –40dBm
0.8
PIN = –50dBm
3
2
PIN = –60dBm
0.4
1
0.4
1
2000
0
TIME (ns)
0
Figure 16. Output Response to RF Burst Input for Various RF Input Levels,
Carrier Frequency = 100 MHz, CLPF = Open
1.8
0
07514-019
1800
1900
1500
1600
1700
1400
900
1000
1100
1200
1300
800
700
500
600
0
100
200
300
400
0
10
20
30
40
50
TIME (ms)
60
70
0
80
07514-020
0.2
0.2
Figure 19. Output Response to RF Burst Input for Various RF Input Levels,
Carrier Frequency = 100 MHz, CLPF = 0.1 μF
1.8
5
1.6
5
1.6
4
0.8
0.6
0.4
3
2
0.2
POWER-DOWN PULSE
PIN = 0dBm
PIN = –10dBm
PIN = –20dBm
PIN = –30dBm
PIN = –40dBm
PIN = –50dBm
PIN = –60dBm
1.2
VOUT (V)
1.0
4
1.4
POWER-DOWN PULSE (V)
POWER-DOWN PULSE
PIN = 0dBm
PIN = –10dBm
PIN = –20dBm
PIN = –30dBm
PIN = –40dBm
PIN = –50dBm
PIN = –60dBm
1.2
1.0
0.8
0.6
0.4
1
3
2
1
0.2
0
POWER-DOWN PULSE (V)
1.4
Figure 17. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency = 100 MHz, CLPF = Open
900
800
700
0
07514-021
TIME (µs)
600
500
400
300
–0.2
200
800
700
600
0
07514-022
TIME (µs)
500
400
300
200
100
0
0
100
VOUT (V)
1.6
0.6
0.6
–0.2
RF PULSE
PIN = 0dBm
5
1.8
0
VOUT (V)
1.4
6
2.0
5
VOUT (V)
1.8
10M
2.2
INPUT PULSE (V)
2.0
1M
2.4
6
RF PULSE
PIN = 0dBm
PIN = –10dBm
PIN = –20dBm
PIN = –30dBm
PIN = –40dBm
PIN = –50dBm
PIN = –60dBm
2.2
100k
FREQUENCY (Hz)
Figure 18. Output Noise Spectral Density, CLPF = 1 nF
Figure 15. Output Noise Spectral Density, CLPF = Open
2.4
10k
INPUT PULSE (V)
10k
PIN = 0dBm
PIN = –10dBm
PIN = –20dBm
PIN = –40dBm
PIN = –60dBm
PIN = OFF
07514-018
PIN = 0dBm
PIN = –10dBm
PIN = –20dBm
PIN = –40dBm
PIN = –60dBm
PIN = OFF
NOISE SPECTRAL DENSITY (nV/ Hz)
NOISE SPECTRAL DENSITY (nV/ Hz)
100k
Figure 20. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency = 100 MHz, CLPF = 10 pF
Rev. 0 | Page 11 of 28
ADL5513
2.4
3.0
2.2
2.5
1600
MEAN = 21.0268
1.5
1.6
1.0
1.4
0.5
1.2
0
1.0
–0.5
0.8
–1.0
0.2
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
PIN (dBm)
0
200
–2.5
–3.0
5 10
j1
j2
100MHz
0
1/3
1
3
900MHz
1900MHz
2140MHz
2600MHz
–j2
3600MHz
–j1
07514-014
–j0.5
600
–2.0
Figure 21. Output Voltage Stability vs. Input Amplitude at 1900 MHz When
VPOS Varies from 2.7 V to 5.5 V
j0.5
800
400
–1.5
+25°C
–40°C
+85°C
+125°C
0.4
1000
Figure 22. Input Impedance vs. Frequency, No Termination Resistor on INHI,
Z0 = 50 Ω
Rev. 0 | Page 12 of 28
0
19.5
20.0
20.5
21.0
21.5
22.0
SLOPE @ 5V/100MHz @ 25°C (mV/dB)
Figure 23. Slope Distribution, 100 MHz
22.5
07514-056
0.6
1200
COUNT
2.0
1.8
ERROR (dB)
2.0
07514-017
VOUT (V)
1400
ADL5513
THEORY OF OPERATION
The ADL5513 is a demodulating logarithmic amplifier, specifically designed for use in RF measurement and power control
applications at frequencies up to 4 GHz. A block diagram is
shown in Figure 24. Sharing much of its design with the AD8313
logarithmic detector/controller, the ADL5513 maintains tight
intercept variability vs. temperature over a 80 dB range. Additional
enhancements over the AD8313, such as a reduced RF burst
response time of 20 ns and board space requirements of only
3 mm × 3 mm, add to the low cost and high performance
benefits found in the ADL5513.
DET
NC
NC
CLPF
NC
16
15
14
13
DET
DET
DET
I
V
INHI 2
I
BAND GAP
REFERENCE
SLOPE
CONTROL
11 VSET
10 COMM
GAIN
BIAS
5
6
7
8
NC
NC
NC
NC
9 TADJ
07514-024
VPOS 4
V
(1)
where:
ID is the internally set detector current.
VIN is the input signal voltage.
VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,
the output voltage is 0 V, if it were capable of going to 0).
12 VOUT
VPOS 1
ADL5513
The RF signal voltages are converted to a fluctuating differential
current having an average value that increases with signal level.
After the detector currents are summed and filtered, the following
function is formed at the summing node:
ID × log10(VIN/VINTERCEPT)
DET
INLO 3
The logarithmic function is approximated in a piecewise
fashion by cascaded gain stages. (For a more comprehensive
explanation of the logarithm approximation, see the AD8307
data sheet.) Using precision biasing, the gain is stabilized over
temperature and supply variations. The overall dc gain is high,
due to the cascaded nature of the gain stages.
Figure 24. Block Diagram
A fully differential design, using a proprietary, high speed SiGe
process, extends high frequency performance. The maximum
input with ±1 dB log conformance error is typically 10 dBm
(referred to 50 Ω). The noise spectral density of −70 dBm sets
the lower limit of the dynamic range. The common pin, COMM,
provides a quality low impedance connection to the printed circuit
board (PCB) ground. The package paddle, which is internally
connected to the COMM pin, should also be grounded to the
PCB to reduce thermal impedance from the die to the PCB.
Rev. 0 | Page 13 of 28
ADL5513
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5513 is specified for operation up to 4 GHz; as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 2.7 V
and 5.5 V should be applied to VPOS. Connect 100 pF and 0.1 µF
power supply decoupling capacitors close to this power supply pin.
VPOS
(SEE NOTE 1)
VPOS
R4
0Ω
NC 13
VSET 11
VOUT
COMM 10
9
7 NC
5 NC
4
C5
100pF
VOUT
ADL5513
3 INLO
C2
47nF
12
R12
0Ω
TADJ
(SEE NOTE 2)
The coupling time constant, 50 × CC/2, forms a high-pass
corner with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where
C1 = C2 = CC. Using the typical value of 47 nF, this high-pass
corner is ~68 kHz. In high frequency applications, fHP should be
as large as possible to minimize the coupling of unwanted low
frequency signals. In low frequency applications, a simple RC
network forming a low-pass filter should be added at the input
for similar reasons. This low-pass filter network should generally be
placed at the generator side of the coupling capacitors, thereby
lowering the required capacitance value for a given high-pass
corner frequency.
OUTPUT FILTERING
For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
CLPF pin be left unconnected and free of any stray capacitance.
Z1
C6
0.1µF
VPOS
07514-025
NOTES
1. SEE THE OUTPUT FILTERING SECTION.
2. SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE
AND POWER-DOWN FUNCTIONALITY SECTIONS.
Figure 25. Basic Connections
The output video bandwidth, which is 10 MHz, can be reduced by
connecting a ground-referenced capacitor (CFLT) to the CLPF pin,
as shown in Figure 27. This is generally done to reduce output
ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals).
The exposed paddle of the LFCSP package is internally connected
to COMM. For optimum thermal and electrical performance,
solder the paddle to a low impedance ground plane.
ILOG
+4
INPUT SIGNAL COUPLING
1kΩ
The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF, ceramic, 0402-style
capacitors for input frequencies of 1 MHz to 4 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the high-pass cutoff frequency of the input stage. The highpass corner is set by the input coupling capacitors and the
internal 20 pF high-pass capacitor. The dc voltage on INHI
and INLO is about one diode voltage drop below VPOS.
VPOS
7kΩ
7kΩ
15kΩ
INHI
2kΩ
GAIN
STAGE
OFFSET COMP
CLPF
CFLT
Figure 27. Lowering the Postdemodulation Bandwidth
CFLT is selected by
C FLT =
1
(2π × 1.5 kΩ × Video Bandwidth) − 3.0 pF
The video bandwidth should typically be set to a frequency
equal to about one-tenth the minimum input frequency. This
ensures that the output ripple of the demodulated log output,
which is at twice the input frequency, is well filtered.
07514-026
INLO
gm
VOUT
In many log amp applications, it may be necessary to lower the
corner frequency of the postdemodulation filter to achieve low
output ripple while maintaining a rapid response time to changes
in signal level. An example of a four-pole active filter is shown
in the AD8307 data sheet. Averaging the output measurement
can also be done when filtering is not possible.
20pF
15kΩ
3pF
07514-027
2 INHI
R1
52.3Ω
NC 15
1
6 NC
RFIN
VPOS
C1
47nF
CLPF 14
C4
100pF
NC 16
R11
0Ω
8 NC
C3
0.1µF
While the input can be reactively matched, in general, this is
not necessary. An external 52.3 Ω shunt resistor (connected to
the signal side of the input coupling capacitors, as shown in
Figure 25) combines with relatively high input impedance to
give an adequate broadband 50 Ω match.
Figure 26. Input Interface
Rev. 0 | Page 14 of 28
ADL5513
VSET
The VOUT pin is driven by a PNP output stage. An internal 10 Ω
resistor is placed in series with the output and the VOUT pin.
The rise time of the output is limited mainly by the slew on
CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is an
internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT
is placed in parallel with the internal pull-down resistor to
provide additional discharge current.
VPOS
CLPF
–
VOUT
400Ω
COMM
ISET
20kΩ
3.5kΩ
COMM
COMM
Figure 29. VSET Interface
The slope is given by ID × 2x × 3.5 kΩ = 20 mV/dB × x. For
example, if a resistor divider to ground is used to generate a VSET
voltage of VOUT/2, then x = 2. The slope is set to 800 V/decade
or 40 mV/dB. See the Measurement Mode section for more
information on setting the slope in measurement mode.
DESCRIPTION OF CHARACTERIZATION
1200Ω
07514-028
0.8V
VSET
Figure 28. Output Interface
The ADL5513 output can drive over 1 nF of capacitance. When
driving such high output capacitive loads, it is required to capacitively load the CLPF pin. The capacitance on the CLPF pin
should be at least 1/50th that of the capacitance on the VOUT pin.
SETPOINT INTERFACE
The VSET input drives the high impedance (40 kΩ) input of an
internal op amp. The VSET voltage appears across the internal
3.5 kΩ resistor to generate ISET. When a portion of VOUT is applied
to VSET, the feedback loop forces
ID × log10(VIN/VINTERCEPT) = ISET
The general hardware configuration used for most of the
ADL5513 characterization is shown in Figure 30. The signal
source and power supply used in this example are the Agilent
E8251A PSG signal generator and E3631A triple output power
supply. Output voltage was measured using the Agilent 34980A
switch box.
AGILENT E3631A
TRIPLE OUTPUT
POWER SUPPLY
AGILENT E8251A
PSG SIGNAL
GENERATOR
(2)
If VSET = VOUT/2x, ISET = VOUT/(2x × 3.5 kΩ).
VPOS
ADL5513
INHI
CHARACTERIZATION
BOARD
VOUT
AGILENT 34980A
SWITCH BOX
INLO
CONTROLLING
COMPUTER
Figure 30. General Characterization Configuration
The result is VOUT = (ID × 3.5 kΩ × 2x) × log10(VIN/VINTERCEPT).
Rev. 0 | Page 15 of 28
07514-030
10Ω
+
20kΩ
07514-029
OUTPUT INTERFACE
ADL5513
ERROR CALCULATIONS
The measured transfer function of the ADL5513 at 100 MHz is
shown in Figure 31. The figure shows plots of measured output
voltage, calculated error, and an ideal line. The input power and
output voltage are used to calculate the slope and intercept values.
The slope and intercept are calculated using linear regression
over the input range from −40 dBm to −20 dBm. The slope and
intercept terms are used to generate an ideal line. The error is
the difference in measured output voltage compared to the ideal
output line.
3.0
1.5
1.0
VOUT1
1.4
1.2
0.5
0
VOUT2
1.0
–0.5
0.8
–1.0
0.6
–1.5
0.4
–2.0
ADJUSTING ACCURACY THROUGH CHOICE OF
CALIBRATION POINTS
–2.5
–3.0
5
10
–5
0
–10
–20
–15
PIN1
–40
–35
–30
–25
–50
–45
PIN2
–60
–55
0
–80
–75
–70
–65
–90
–85
0.2
PIN (dBm)
07514-031
VOUT (V)
1.6
2.0
Choose calibration points to suit the specific application, but
usually they should be in the linear range of the log amp.
Figure 31. Typical Output Voltage vs. Input Signal
The equation for output voltage can be written as
VOUT = Slope × (PIN − Intercept)
where:
Slope is the change in output voltage divided by the change in
input power, PIN. Slope is expressed in volts per decibel (V/dB).
Intercept is the calculated power in decibels (dB) at which the
output voltage is 0 V. Note that VOUT = 0 V can never be achieved.
Calibration is performed by applying two known signal levels to
the ADL 5513 and measuring the corresponding voltage outputs.
The calibration points are in general chosen to be within the
linear-in-dB range of the device.
Calculation of the slope and intercept are accomplished by
using the following equations:
In some applications, very high accuracy is required at a reduced
input range; in other applications, good linearity is necessary over
the full power input range. The linearity of the transfer function
can be adjusted by choice of calibration points. Figure 32 and
Figure 33 show plots for a typical device at 3600 MHz as an example of adjusting accuracy through choice of calibration points.
2.0
2.00
1.5
1.75
1.0
1.50
0.5
1.25
0
1.00
–0.5
0.50
+25°C
–40°C
+85°C
+125°C
0.25
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
PIN (dBm)
VOUT ( MEASURED )
Slope
Once the slope and intercept are calculated, VOUT(IDEAL) can be
calculated, and the error is determined using the following
equation:
Error 
2.5
2.25
0.75
VOUT ( MEASURED )1  VOUT ( MEASURED ) 2
Slope 
PIN1  PIN2
Intercept  PIN1 
2.50
ERROR (dB)
1.8
2.5
ERROR (dB)
2.0
–1.0
–1.5
–2.0
0
–2.5
5 10
07514-032
IDEAL LINE
VOUT AND ERROR @ +25°C
VOUT AND ERROR @ –40°C
VOUT AND ERROR @ +85°C
2.2
Figure 31 also shows error plots for output voltages measured at
−40°C and 85°C. These error plots are calculated using slope
and intercept at 25°C, which is consistent in a mass-production
environment, where calibration over temperature is not practical.
This is a measure of the linearity of the device. Error from the
linear response to the CW waveform is not a measure of absolute
accuracy because it is calculated using the slope and intercept of
each device. However, error verifies the linearity of the devices.
Similarly, at temperature extremes, error represents the output
voltage variations from the 25°C ideal line performance. Data
presented in the graphs are the typical error distributions observed
during characterization of the ADL5513. Device performance
was optimized for operation at 85°C; this can be changed by
changing the voltage at TADJ.
VOUT (V)
2.4
Figure 31 shows a plot of the error at 25°C, the temperature at
which the device is calibrated. Error is not 0 dB over the full
dynamic range. This is because the log amp does not perfectly
follow the ideal VOUT vs. PIN equation, even within its operating
range. The error at the calibrating points of −20 dBm and −40 dBm
is equal to 0 dB by definition.
Figure 32. Typical Device at 3600 MHz, Calibration Points at PIN = −20 dBm
and −40 dBm
(VOUT ( MEASURED )  VOUT ( IDEAL))
Slope
Rev. 0 | Page 16 of 28
2.25
2.0
2.00
1.5
1.75
1.0
1.50
0.5
1.25
0
1.00
–0.5
improve linearity and extend the dynamic range, unless enough
calibration points are used to remove error.
–1.0
0.75
+25°C
–40°C
+85°C
+125°C
0.50
0.25
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
PIN (dBm)
0
–1.5
–2.0
–2.5
5 10
Figure 33. Typical Device at 3600 MHz, Calibration Points at PIN = −12 dBm
and −40 dBm
In Figure 32, calibration points are chosen so that linearity is
improved over the full dynamic range, but error at the higher
power level at PIN = −10 dBm is 0.5 dB at 25°C. In Figure 33,
calibration points are chosen so that error is smaller at higher
power input ,but with loss of linearity over the full dynamic range.
Figure 34 shows another way of presenting the error of a log
amp detector. The same typical device from Figure 32 and
Figure 33 is presented where the error at −40°C, +85°C, and
+125°C are calculated with respect to the output voltage at
+25°C. This is the key difference in presenting the error of a log
amp compared with the plots in Figure 32 and Figure 33 where
the error is calculated with respect to the ideal line at 25°C.
2.5
2.50
2.0
1.5
1.75
1.0
1.50
0.5
1.25
0
1.00
–0.5
0.75
–1.0
0.50
–1.5
0.25
–2.0
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
PIN (dBm)
0
–2.5
5 10
ERROR (dB)
VOUT (V)
2.00
–40°C
+85°C
+125°C
07514-034
2.25
Figure 34. Error vs. Temperature with Respect to Output Voltage at 25°C,
3600 MHz
With this alternative technique, the error at ambient becomes
0 dB by definition. This would be valid if the device transfer
function perfectly followed the ideal equation or if there were
many calibration points used.
VOUT = Slope × (PIN − Intercept)
Figure 34 is a useful tool for estimating temperature drift at a
particular power level with respect to the (nonideal) output
voltage at ambient.
TEMPERATURE COMPENSATION OF OUTPUT
VOLTAGE
The primary component of the variation in VOUT vs. temperature as
the input signal amplitude is held constant is the drift of the
intercept. This drift is also a weak function of the input signal
frequency; therefore, a provision is made for the optimization of
the internal temperature compensation at a given frequency by
providing Pin TADJ with dual functionality. The first function
for this pin is temperature compensation and the second function
is to power down the device when VTADJ = VPOS − 0.3 V (see the
Power-Down Functionality section).
VINTERNAL
ICOMP
PWDN/TADJ
COMM
COMM
07514-035
2.5
ERROR (dB)
2.50
07514-033
VOUT (V)
ADL5513
Figure 35. TADJ Interface
VTADJ is a voltage forced between TADJ and ground. The value
of this voltage determines the magnitude of an analog correction
coefficient, which is used to reduce intercept drift.
The relationship between output temperature drift and frequency is not linear and cannot be easily modeled. As a result,
experimentation is required to select the optimum VTADJ voltage.
The VTADJ voltage applied to Pin TADJ can be supplied by a
DAC with sufficient resolution, or Resistor R8 and Resistor R9
on the evaluation board (see Figure 47) can be configured as a
voltage divider using VPOS as the voltage source.
Table 4 shows the recommended voltage values for some
commonly used frequencies in characterization to optimize
operation at 85°C. The TADJ pin has high input impedance.
Table 4. Recommended VTADJ Values
Frequency
100 MHz
900 MHz
1.9 GHz
2.14 GHz
2.6 GHz
3.6 GHz
Because the log amp never perfectly follows this equation, especially outside of its linear range, Figure 34 can be misleading as
a representation of log amp error. This plot tends to artificially
Rev. 0 | Page 17 of 28
Recommended VTADJ (V)
0.89
0.86
0.80
0.84
0.83
0.90
ADL5513
1.5
Compensating the device for temperature drift using TADJ allows
for great flexibility. If the user requires minimum temperature
drift at a given input power or subset of the dynamic range,
the TADJ voltage can be swept while monitoring VOUT over
temperature. Figure 36 shows how error changes on a typical
part over the full dynamic range when VTADJ is swept from 0.5 V
to 1.2 V in steps of 0.1 V.
3.0
2.2
2.5
2.0
2.0
0
0.5
1.2
0
1.0
–0.5
0.8
–1.0
0.4
–2.0
+25°C
+85°C
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
PIN (dBm)
0
0.7
0.8
0.9
TADJ (V)
1.0
1.1
1.2
Figure 37. Error vs. VTADJ, PIN = −30 dBm at 1900 MHz
POWER-DOWN FUNCTIONALITY
–2.5
–3.0
5 10
0.6
It is important that temperature adjustment be performed on
multiple devices.
–1.5
VTADJ = 1.2V
–1.0
0.5
07514-037
1.0
1.4
0.2
0.5
–0.5
ERROR (dB)
1.6
0.6
–20°C
+65°C
+125°C
1.5
VTADJ = 0.5V
07514-036
VOUT (V)
1.8
–40°C
+45°C
+105°C
1.0
ERROR (dB), PIN = –30dBm
2.4
+25°C
0°C
+85°C
Figure 36. VOUT vs. TADJ at 85°C, 1900 MHz
Power-down functionality of ADL5513 is achieved through externally applied voltage on the TADJ pin. If VTADJ = VPOS − 0.3 V,
the output voltage and supply current are close to 0.
1.8
1.2
1.0
0.8
0.6
0.4
0
4.0
4.1
4.2
4.3
4.4
4.5
4.6
TADJ (V)
4.7
4.8
5.0
Figure 38. VOUT vs. VTADJ at 100 MHz, VPOS = 5 V
100
+25°C
–40°C
+85°C
+125°C
10
1
0.1
4.0
4.1
4.2
4.3
4.4
4.5
4.6
TADJ (V)
4.7
4.8
Figure 39. Sleep Current vs. VTADJ, VPOS = 5 V
Rev. 0 | Page 18 of 28
4.9
07514-038
0.2
4.9
5.0
07514-039
VTADJ voltages in Table 4 are chosen so that the error is at its
minimum at 85°C. Criteria for the choice of VTADJ is unique for
a given application. Figure 37 shows how error on a typical device
changes at INHI = −30 dBm when VTADJ is swept at different
temperatures. If the ADL5513 must have minimum error at a
certain temperature, then VTADJ should be chosen such that the
line for that temperature intersects the 25°C line. At this VTADJ
setting, the error at all other temperatures is not the minimum.
If the deviation of error over temperature is more important
than the error at a single temperature, VTADJ should be determined
by the intersection of the lines for the temperatures of interest.
For the characterization data presented, VTADJ values were chosen
so that ADL5513 has a minimum error at 85°C, which is at the
intersection of the lines for 85°C and 25°C. For example, at
1900 MHz, VTADJ = 0.8 V. If a given application requires error
deviation to be at a minimum when the temperature changes
from −40°C to 85°C, VTADJ is determined by the intersection of
the error line for those temperatures.
1.4
VOUT @ –10dBm (V)
DEVICE CALIBRATION
+25°C
–40°C
+85°C
+125°C
1.6
SLEEP CURRENT (mA)
Figure 37 shows the results of sweeping VTADJ over multiple
temperatures while holding PIN constant. The same VTADJ should
be used for the full dynamic range for a specified supply
operation.
ADL5513
MEASUREMENT MODE
When the VOUT voltage or a portion of the VOUT voltage is fed
back to the VSET pin, the device operates in measurement
mode. As shown in Figure 40, the ADL5513 has an offset
voltage, a positive slope, and a VOUT measurement intercept at
the low end of its input signal range.
2.4
3.0
2.2
2.5
2.0
2.0
1.8
1.5
0
VOUT2
1.0
–0.5
0.8
–1.0
VOUT 0.6
IDEAL 0.4
–1.5
–2.0
VOUT 25°C
–2.5
–3.0
5
10
–5
0
–10
–20
–15
PIN1
–40
–35
–30
–25
–50
–45
PIN2
–60
–55
0
–80
–75
–70
–65
–90
–85
0.2
PIN (dBm)
Further information on the intercept variation dependence upon
waveform can be found in the AD8313 and AD8307 data sheets.
Figure 40. Typical Output Voltage vs. Input Signal
The output voltage vs. input signal voltage of the ADL5513 is
linear-in-dB over a multidecade range. The equation for this
function is
ADL5513
40mV/dB
VOUT
10kΩ
VOUT = X × VSLOPE/DEC × log10(VIN/VINTERCEPT) =
VSET
10kΩ
X × VSLOPE/dB × 20 × log10(VIN/VINTERCEPT)
(3)
Figure 41. Increasing the Slope
where:
X is the feedback factor in VSET = VOUT/X.
VSLOPE/DEC is nominally 400 mV/decade or 20 mV/dB.
VINTERCEPT is the x-axis intercept of the linear-in-dB portion of
the VOUT vs. PIN curve (see Figure 40).
VINTERCEPT is −100 dBV for a sinusoidal input signal.
The required resistor values needed to increase the slope are
calculated from the following equation.
Slope2
R1
+1 =
R2
Slope1
An offset voltage, VOFFSET, of 0.47 V is internally added to
the detector signal, so that the minimum value for VOUT is
X × VOFFSET; therefore, for X = 1, the minimum VOUT is 0.47 V.
The slope is very stable vs. process and temperature variation.
When Base 10 logarithms are used, VSLOPE/DEC represents the
volts per decade. A decade corresponds to 20 dB; VSLOPE/DEC/20 =
VSLOPE/dB represents the slope in volts per decibel (V/dB).
As shown in Figure 40, VOUT voltage has a positive slope.
Although demodulating log amps respond to input signal
voltage, not input signal power, it is customary to discuss the
amplitude of high frequency signals in terms of power. In this
case, the characteristic impedance of the system, Z0, must be
known to convert voltages to their corresponding power levels.
The following equations are used to perform this conversion:
P(dBm) = 10 × log10(Vrms2/(Z0 × 1 mW))
It is important to remember when increasing the slope of the
ADL5513 that R1 and R2 must be properly sized so the output
current drive capability is not exceeded. The dynamic range of
the ADL5513 may be limited if the maximum output voltage is
achieved before the maximum input power is reached. In cases
where VPOS is 5 V, the maximum output voltage is 4.7 V.
The slope of the ADL5513 can be reduced by connecting VSET
to VOUT and adding a voltage divider on the output.
(5)
2
P(dBm) = P(dBV) − 10 × log10(Z0 × 1 mW/1 Vrms )
(8)
where:
R1 is the resistor from VOUT to VSET.
R2 is the resistor from VSET to ground.
Slope1 is the nominal slope of the ADL5513.
Slope2 is the new slope.
(4)
P(dBV) = 20 × log10(Vrms/1 Vrms)
07514-041
1.2
0.5
(7)
To operate in measurement mode, VOUT is connected to VSET.
Connecting VOUT directly to VSET yields the nominal
logarithmic slope of approximately 20 mV/dB. The output swing
corresponding to the specified input range is then approximately
0.47 V to 2.0 V. The slope and output swing can be increased by
placing a resistor divider between VOUT and VSET (that is, one
resistor from VOUT to VSET and one resistor from VSET to
ground). The input impedance of VSET is approximately 40 kΩ.
Slope-setting resistors should be kept below 20 kΩ to prevent
this input impedance from affecting the resulting slope. If two
equal resistors are used (for example, 10 k Ω/10 kΩ), the slope
doubles to approximately 40 mV/dB.
1.0
ERROR 25°C
ERROR (dB)
VOUT1
1.4
PINTERCEPT(dBm) =
PINTERCEPT(dBV) – 10 × log10(Z0 × 1 mW/1 Vrms2) =
−100 dBV − 10 × log10(50 × 10−3) = −87 dBm
SETTING THE OUTPUT SLOPE IN MEASUREMENT
MODE
07514-040
VOUT (V)
1.6
For example, PINTERCEPT for a sinusoidal input signal expressed in
terms of decibels referred to 1 mW (dBm) in a 50 Ω system is
(6)
Rev. 0 | Page 19 of 28
ADL5513
CONTROLLER MODE
CONSTANT POWER OPERATION
The ADL5513 provides a controller mode feature at Pin VOUT.
Using VSET for the setpoint voltage, it is possible for the ADL5513
to control subsystems, such as power amplifiers (PAs), variable
gain amplifiers (VGAs), or variable voltage attenuators (VVAs),
which have output power that increases monotonically with
respect to their gain control signal.
In controller mode, the ADL5513 can be used to hold the output
power stable over a broad temperature/input power range. This
can be useful in topologies where a transmit card is driving an
HPA or when connecting power-sensitive modules together.
Figure 44 shows a schematic of a circuit setup that holds the
output power to approximately −39 dBm at 900 MHz when the
input power is varied over a 62 dB dynamic range. Figure 43
shows the performance results. A portion of the output power is
coupled to the input of ADL5513 using a 20 dB coupler. The
VSET voltage is set to 0.65 V, which forces the ADL5513 output
voltage to control the ADL5330 to deliver −59 dBm. (If the
ADL5513 is in measurement mode and a −59 dBm input power
is applied, the output voltage is 0.65 V). A generic op amp is used
(AD8062) to invert the slope of the ADL5513 so that the gain of
the ADL5330 decreases as the ADL5513 control voltage
increases. The high end power is limited by the maximum gain
of the ADL5330 and can increase if VSET is moved so that the
ADL5513 has a higher power on its input and a VGA with
higher linearity is used. The low power is limited by the
sensitivity of the ADL5513 and can be increased with a reduction
in the coupling value of the coupler.
To operate in controller mode, the link between VSET and VOUT
is broken. A setpoint voltage is applied to the VSET input, VOUT
is connected to the gain control terminal of the VGA, and the
RF input of the detector is connected to the output of the VGA
(usually using a directional coupler and some additional attenuation). Based on the defined relationship between VOUT and the
RF input signal when the device is in measurement mode, the
ADL5513 adjusts the voltage on VOUT (VOUT is now an error
amplifier output) until the level at the RF input corresponds to
the applied VSET. When the ADL5513 operates in controller
mode, there is no defined relationship between the VSET and the
VOUT voltage; VOUT settles to a value that results in the correct input
signal level appearing at INHI/INLO.
VGA/VVA
DIRECTIONAL
COUPLER
RFIN
GAIN
CONTROL
VOLTAGE
47nF
–35
–36
–37
–38
POUT (dBm)
For this output power control loop to be stable, a groundreferenced capacitor must be connected to the CLPF pin.
This capacitor, CFLT, integrates the error signal (in the form of
a current) to set the loop bandwidth and ensure loop stability.
Further details on control loop dynamics can be found in the
AD8315 data sheet.
–39
–40
–41
–42
–43
VOUT
–44
+25°C
–40°C
+85°C
52.3Ω
47nF
–45
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
PIN (dBm)
ADL5513
INLO
VSET
DAC
Figure 43. Performance of ADL5330/ADL5513
Constant Power Circuit
CFLT
07514-042
CLPF
Figure 42. Controller Mode
Rev. 0 | Page 20 of 28
0
5
07514-044
INHI
ADL5513
GND
5V
VPOS
20kΩ
0.1µF
5V
C7
1000pF
0.1uF
10kΩ
VPOS
1
47nF
2 INHI
0Ω
52.3Ω
10kΩ
VPOS
OPLO
COM1
COM2
VPS1
VPS2
9
5 NC
4
5V
10kΩ
VSET = 0.65V
10kΩ
5V
AD8062
10kΩ
TADJ
VTADJ
100pF
Z1
T2
0.1uF
RFOUT
5V
100pF
100pF
0Ω
1nF
1nF
0.1µF
VPOS
Figure 44. Schematic of the ADL5513 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5330
Rev. 0 | Page 21 of 28
07514-043
100pF
100pF
COM2
0.1µF
ADL5330
INLO
COMM 10
VOUT 1kΩ
120nH
OPHI
GNLO
0Ω
DIRECTIONAL
COUPLER
20dB
VPS2
COM2
COM1
5V
VPS2
COM1
INHI
100pF
VPS2
VPS2
OPBS
100pF
VPS1
VREF
T1
VPS2
GAIN
100pF
ENBL
0.1µF
IPBS
0Ω
INPUT
47nF
100pF
VPOS
ADL5513
3 INLO
7 NC
120nH
10kΩ
12
VSET 11
6 NC
100pF
0Ω
NC 13
GAIN
CLPF 14
VPOS
8 NC
0.1µF
NC 15
0Ω
SW1
SMA
NC 16
100pF
ADL5513
Due to the amplification of out-of-band noise by AD8368, a
band-pass filter was inserted between the AD8368 and ADL5513
to increase the low end sensitivity. The VGA amplifies low power
signals and attenuates high power signals to fit them in the
detectable range of the ADL5513. If an amplifier with higher
gain and lower noise figure is used, better than 90 dB sensitivity
can be achieved for use in an RSSI application.
INCREASING THE DYNAMIC RANGE OF THE
ADL5513
The ADL5513 dynamic range can be extended by adding a standalone VGA, whose gain control input is derived directly from
VOUT. This extends the dynamic range by the gain control range
of the VGA. In order for the overall measurement to remain
linear in dB, the VGA must provide a linear-in-dB (exponential)
gain control function. The VGA gain must decrease with an
increase in its gain bias in the same way as the ADL5513. Alternatively, an inverting op amp with suitable level shifting can be
used. It is convenient to select a VGA that needs only a single
5.0 V supply and is capable of generating a single-ended output.
All of these conditions are met by the AD8368. Figure 46 shows
the schematic. Using the inverse gain mode (MODE pin low)
of the AD8368, its gain decreases on a slope of 37.5 mV/dB to a
minimum value of −12 dB for a gain voltage (VGAIN) of 1.0 V.
The voltage, VGAIN, that is required by the AD8368 is 50% of the
output of the ADL5513. To scale this voltage, it is necessary to
install a voltage divider at the output of the ADL5513. Over the
1.5 V range from the output of the ADL5513, the gain of the
AD8368 varies by (0.5 × 1.5 V)/(37.5 mV/dB), or 20 dB. Combined with the 75 dB gain span (at 120 MHz) of the ADL5513,
this results in a 95 dB variation for a 1.5 V change in VOUT.
3.0
1.625
2.5
1.500
2.0
1.375
1.5
1.250
1.0
1.125
0.5
1.000
0
–0.5
0.875
0.750
–1.0
VOUT +25°C
VOUT –40°C
VOUT +85°C
0.625
0.500
–1.5
–2.0
ERR0R +25°C
ERR0R –40°C
ERR0R +85°C
0.375
0.250
–90
–80
–70
–60
–50
–40 –30 –20
PIN (dBm)
ERROR (dB)
1.750
–2.5
–10
0
10
–3.0
20
07514-045
VOUT (V)
Figure 45 shows data results of the extended dynamic range at
120 MHz with error in VOUT.
Figure 45. Output and Conformance for the AD8368/ADL5513
Extended Dynamic Range Circuit
VPOS
VPOS
47nF
2 INHI
52.3Ω
BAND-PASS
120MHz
VPOS
VOUT 1kΩ
VSET 11
COMM 10
9
4
TADJ
VTADJ = 0.89V
100pF
VOUT
1kΩ
Z1
0.1uF
VPOS
1kΩ
Figure 46. ADL5513 with 95 dB Dynamic Range
Rev. 0 | Page 22 of 28
07514-046
1nF
12
ADL5513
3 INLO
5 NC
10nF
1
8 NC
VPOS
NC 13
100pF
NC 15
0Ω C15
0.1µF
CLPF 14
OCOM
C12
1nF
7 NC
ENBL
10nF
C7
1000pF
0.1uF
VPOS3
6 NC
OUTP
GND
VPOS
NC 16
VPSI
DECL
ICOM
VPSO
VPSI
DETI
C10
1nF
C15
0.1µF
OCOM
0.1µF
C12
1nF
VPSO
AD8368
VPSI
GAIN
0Ω
DECL
ICOM
VPSI
MODE
VPOS1
0Ω
ICOM
HPFL
10kΩ
VPOS
VPOS2
VPSI
DECL
10nH
5.6pF
INPT
DETO
INPUT 10nF
215Ω
ICOM
1nF
VPOS1 VPOS2 VPOS3
ADL5513
EVALUATION BOARD
GND
VPOS
C3
0.1µF
VPOS
VOUT_ALT
C7
1000pF
R11
0Ω
R2
OPEN
2 INHI
NC 13
CLPF 14
3 INLO
VPOS
R3
1kΩ
VOUT
RL
OPEN
COMM 10
9
4
TADJ
R5
OPEN
Z1
C5
100pF
VOUT
CL
OPEN
R4
0Ω
VSET 11
8 NC
C2
47nF
12
ADL5513
5 NC
R1
52.3Ω
NC 15
1
7 NC
RFIN
VPOS
6 NC
C1
47nF
NC 16
C4
100pF
VSET
VPOS
R12
0Ω
R6
OPEN
R7
0Ω
C6
0.1µF
R10
0Ω
TADJ
R8
OPEN
TADJ
R9
OPEN
EXT_PWDN_TADJ
07514-047
VPOS
07514-048
07514-049
Figure 47. Evaluation Board Schematic
Figure 49. Component Side Silkscreen
Figure 48. Component Side Layout
Rev. 0 | Page 23 of 28
ADL5513
Table 5. Evaluation Board Configuration Options
Component
C1, C2, R1
C3, C4, C5, C6,
R11, R12
C7
R2, R3 R4, R5, R10, RL, CL
R6, R7, R8, R9
Function
Input interface.
The 52.3 Ω resistor in Position R1 combines with the internal input impedance of
the ADL5513 to give a broadband input impedance of about 50 Ω. C1 and C2 are
dc-blocking capacitors. A reactive impedance match can be implemented by
replacing R1 with an inductor and C1 and C2 with appropriately valued capacitors.
Power supply decoupling.
The nominal supply decoupling consists of a 100 pF filter capacitor placed
physically close to the ADL5513 and a 0.1 µF capacitor placed nearer to the power
supply input pin. If additional isolation from the power supply is required, a small
resistance (R11 or R12) can be installed between the power supply and the
ADL5513.
Filter capacitor.
The low-pass corner frequency of the circuit that drives the VOUT pin can be
lowered by placing a capacitor between CLPF and ground. Increasing this
capacitor increases the overall rise/fall time of the ADL5513 for pulsed input
signals.
Output interface—measurement mode.
In measurement mode, a portion of the output voltage is fed back to the VSET pin via
R4. The magnitude of the slope of the VOUT output voltage response can be
increased by reducing the portion of VOUT that is fed back to VSET. R3 can be used
as a back-terminating resistor or as part of a single-pole, low-pass filter. If a
reduction in slope is desired, a voltage divider can be installed at the output using
R3 and RL.
Output interface—controller mode.
In controller mode, the ADL5513 can control the gain of an external component.
To allow for this, remove the R4 resistor. A setpoint voltage is applied to Pin VSET.
The value of this setpoint voltage corresponds to the desired RF input signal level
applied to the ADL5513 RF input. A sample of the RF output signal from this variable
gain component is applied to the ADL5513 input by a directional coupler. The
voltage at the VOUT pin is applied to the gain control of the variable gain element.
The magnitude of the control voltage can optionally be reduced via a voltage
divider comprising R3 and RL, or a low-pass filter can be installed using R3 and CL.
Temperature compensation interface.
A voltage source can be used to optimize the temperature performance for various
input frequencies. The pads for R8 and R9 can be used for a voltage divider from
the VPOS node to set the TADJ voltage at different frequencies. The ADL5513 can be
disabled by applying a voltage of VPOS − 0.3 V to this node.
Rev. 0 | Page 24 of 28
Default Value
R1 = 52.3 Ω (Size 0402)
C1 = 47 nF (Size 0402)
C2 = 47 nF (Size 0402)
C3 = 0.1 µF (Size 0402)
C4 = 100 pF (Size 0402)
C5 = 100 pF (Size 0402)
C6 = 0.1 µF (Size 0402)
R11 = 0 Ω (Size 0402)
R12 = 0 Ω (Size 0402)
C7 = 1000 pF (Size 0402)
R2 = open (Size 0402)
R3 = 1 kΩ (Size 0402)
R4 = 0 Ω (Size 0402)
R5 = open (Size 0402)
R10 = open (Size 0402)
RL = CL = open (Size 0402)
R2 = open (Size 0402)
R3 = 1 kΩ (Size 0402)
R4 = open (Size 0402)
R5 = open (Size 0402)
R10 = 0 Ω (Size 0402)
RL = CL = open (Size 0402)
R6 = open (Size 0402)
R7 = 0 Ω (Size 0402)
R8 = open (Size 0402)
R9 = open Ω (Size 0402)
ADL5513
OUTLINE DIMENSIONS
0.60 MAX
3.00
BSC SQ
BOTTOM VIEW
13
12
0.45
TOP
VIEW
2.75
BSC SQ
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
0.05 MAX
0.02 NOM
0.30
0.23
0.18
1
1.50 SQ
1.35
EXPOSED
PAD
0.50
BSC
0.90
0.85
0.80
16
PIN 1
INDICATOR
*1.65
9
4
8
5
0.25 MIN
1.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
071708-A
PIN 1
INDICATOR
0.50
0.40
0.30
Figure 50. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5513ACPZ-R71
ADL5513ACPZ-R21
ADL5513ACPZ-WP1
ADL5513-EVALZ1
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
Package Option
CP-16-3
CP-16-3
CP-16-3
Branding
Q1L
Q1L
Q1L
ADL5513
NOTES
Rev. 0 | Page 26 of 28
ADL5513
NOTES
Rev. 0 | Page 27 of 28
ADL5513
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07514-0-10/08(0)
Rev. 0 | Page 28 of 28