SSRAM AS5SP512K18 A A CE1\ CE2 NC NC BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A Plastic Encapsulated Microcircuit 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 81 82 84 83 87 85 86 89 88 91 90 92 3 78 4 77 5 76 NC NC 6 75 7 74 DQb DQb 8 73 9 72 VSSQ VDDQ 10 71 11 70 DQb 12 69 DQb NC VDD 13 68 NC VSS DQb 16 65 17 64 18 63 DQb 19 62 VDDQ VSSQ 20 61 21 60 DQb 22 59 DQb DQPb 23 58 24 57 VSSQ DQa DQa NC NC 25 56 NC VSSQ VDDQ 26 55 27 54 NC NC NC 28 53 29 52 VSSQ VDDQ NC NC 30 51 NC 14 67 DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ 50 49 48 47 46 45 44 43 42 41 66 VDDQ VSSQ NC DQPa VDD NC* A A A A A A A A 40 39 38 NC* NC* VSS 37 35 34 36 SSRAM [SPB] 15 A NC NC GENERAL DESCRIPTION FAST ACCESS TIMES Parameter Symbol Cycle Time tCYC Clock Access Time tCD Output Enable Access tOE 93 95 94 96 97 79 MODE A A A A A1 A0 80 2 33 Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support Global Write support On-Chip low power mode [powerdown] via ZZ pin Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention. Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package Available in Industrial (-40oC to +85oC), Enhanced (-40oC to +105oC), and Mil-Temperature (-55oC to +125oC) Operating Ranges RoHS compliant options 1 NC NC VDDQ VSSQ 31 NC 32 FEATURES 98 100 Pipeline Burst, Single Cycle Deselect 99 9Mb, 512K x 18, Synchronous SRAM 133Mhz 7.5 4.0 4.0 Units ns ns ns Micross Components AS5SP512K18 is a 9.0Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 512K x 18. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. BLOCK DIAGRAM OE\ ZZ CLK CE1\ CE2 I/O Gating and Control CE3\ BWE\ BWx\ CONTROL BLOCK GW\ ADV\ ADSC\ ADSP\ MODE A0-Ax AS5SP512K18 Rev. 2.4 10/13 BURST CNTL. Address Registers Row Decode Memory Array x18 SBP T Synchronous Pipeline Burst N Two (2) cycle load N One (1) cycle de-select N One (1) cycle latency on Mode change Output Register Output Driver DQx, DQPx Input Register Column Decode The AS5SP512K18 includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV\, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status Cache controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system’s burst sequence control block and are controlled by Address Advance (ADV\) control input. Micross Components reserves the right to change products or specifications without notice. 1 SSRAM AS5SP512K18 PIN DESCRIPTION/ASSIGNMENT TABLE Signal Name Clock Symbol CLK Type Input Pin Address A0, A1 Address A Chip Enable Chip Enable Global Write Enable Byte Enables CE1\, CE3\ CE2 GW\ BWa\, BWb\ Description This input registers the address, data, enables, Global and Byte writes as well as the burst control functions Input 37, 36 Low order, Synchronous Address Inputs and Burst counter address inputs Input(s) 35, 34, 33, 32, 31, 100, Synchronous Address Inputs 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43,83 Input 98, 92 Active Low True Chip Enables Input 97 Active High True Chip Enable Input 88 Active Low True Global Write enable. Write to all bits Input 93, 94 Active Low True Byte Write enables. Write to byte segments Byte Write Enable Output Enable Address Strobe Controller BWE\ OE\ ADSC\ Input Input Input Address Strobe from Processor ADSP\ Input Address Advance ADV\ Input Power-Down ZZ Input Data Parity Input/Outputs DQPa, DQPb Input/ Output Data Input/Outputs DQa, DQb Input/ Output Burst Mode Power Supply [Core] Ground [Core] Power Supply I/O MODE VDD VSS VDDQ Input Supply Supply Supply I/O Ground VSSQ Supply No Connection(s) NC NA 89 87 86 85 Active Low True Byte Write Function enable Active Low True Asynchronous Output enable Address Strobe from Controller. When asserted LOW, Address is captured in the address registers and A0-A1 are loaded into the Burst When ADSP\ and ADSC are both asserted, only ADSP is recognized 84 Synchronous Address Strobe from Processor. When asserted LOW, Address is captured in the Address registers, A0-A1 is registered in the burst counter. When both ADSP\ and ADSC\ or both asserted, only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH 83 Advance input Address. When asserted HIGH, address in burst counter is incremented. 64 Asynchronous, non-time critical Power-down Input control. Places the chip into an ultra low power mode, with data preserved. 74,24 Bidirectional I/O Parity lines. As inputs they reach the memory array via an input register, the address stored in the register on the rising edge of clock. As outputs, the line delivers the valid data stored in the array via an output register and output driver. The data delieverd is from the previous clock period of the READ cycle. 58, 59, 62, 63, 68, 69, Bidirectional I/O Data lines. As inputs they reach the memory 72, 73, 8, 9, 12, 13, 18, array via an input register, the address stored in the register on the 19, 22, 23 rising edge of clock. As outputs, the line delivers the valid data stored in the array via an output register and output driver. The data delieverd is from the previous clock period of the READ cycle. 31 Interleaved or Linear Burst mode control 91, 15, 41, 65 Core Power Supply 90, 17, 40, 67 Core Power Supply Ground 4, 11, 20, 27, 54, 61, Isolated Input/Output Buffer Supply 70, 77 5, 10, 21, 26, 55, 60, Isolated Input/Output Buffer Ground 71, 76 1, 2, 3, 6, 7, 14, 16, 25, No connections to internal silicon 28, 29, 30, 38, 39, 42 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 LOGIC BLOCK DIAGRAM A0, A1, Ax ADDRESS REGISTER MODE 2 A0, A1 ADV\ CLK Burst CounterQ1 and CLR Logic Q0 ADSC\ ADSP\ BWb\ Byte Write Register DQb, DQPb Byte Write Driver DQb, DQPb Memory Array Sense Amps Output Registers BWa\ BWE\ GW\ CE1\ CE2 CE3\ OE\ Byte Write Register DQa, DQPa Enable Register DQx, DQPx Byte Write Driver DQa, DQPa Input Registers Pipeline Enable Sleep Control ZZ AS5SP512K18 Rev. 2.4 10/13 Output Buffers Micross Components reserves the right to change products or specifications without notice. 2 SSRAM AS5SP512K18 FUNCTIONAL DESCRIPTION Micross Components’s AS5SP512K18 Synchronous SRAM is manufactured to support today’s High Performance platforms utilizing the Industries leading Processor elements including those of Intel and Motorola. The AS5SP512K18 supports Synchronous SRAM READ and WRITE operations as well as Synchronous Burst READ/WRITE operations. All inputs with the exception of OE\, MODE and ZZ are synchronous in nature and sampled and registered on the rising edge of the devices input clock (CLK). The type, start and the duration of Burst Mode operations is controlled by MODE, ADSC\, ADSP\ and ADV\ as well as the Chip Enable pins CE1\, CE2, and CE3\. All synchronous accesses including the Burst accesses are enabled via the use of the multiple enable pins and wait state insertion is supported and controlled via the use of the Advance control (ADV\). The only exception occurs when the device is recovering from a deselected to select state where its outputs are tristated in the first machine cycle and controlled by its Output Enable (OE\) on following cycle. Consecutive single cycle READS are supported. Once the READ operation has been completed and deselected by use of the Chip Enable(s) and either ADSP\ or ADSC\, its outputs will tri-state immediately. A Single ADSP\ controlled WRITE operation is initiated when both of the following conditions are satisfied at the time of Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip Enable(s) are asserted ACTIVE. The address presented to the address bus is registered and loaded on CLK HIGH, then presented to the core array. The WRITE controls Global Write, and Byte Write Enable (GW\, BWE\) as well as the individual Byte Writes (BWa\ and BWb\) and ADV\ are ignored on the first machine cycle. ADSP\ triggered WRITE accesses require two (2) machine cycles to complete. If Global Write is asserted LOW on the second Clock (CLK) rise, the data presented to the array via the Data bus will be written into the array at the corresponding address location specified by the Address bus. If GW\ is HIGH (inactive) then BWE\ and one or more of the Byte Write controls (BWa\ and BWb\) controls the write operation. All WRITES that are initiated in this device are internally self timed. The AS5SP512K18 supports both Interleaved as well as Linear Burst modes therefore making it an architectural fit for either the Intel or Motorola CISC processor elements available on the Market today. The AS5SP512K18 supports Byte WRITE operations and enters this functional mode with the Byte Write Enable (BWE\) and the Byte Write Select pin(s) (BWa\ and BWb\). Global Writes are supported via the Global Write Enable (GW\) and Global Write Enable will override the Byte Write inputs and will perform a Write to all Data I/Os. A Single ADSC\ controlled WRITE operation is initiated when the following conditions are satisfied: [1] ADSC\ is asserted LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are asserted (TRUE or Active), and [4] the appropriate combination of the WRITE inputs (GW\, BWE\, BWx\) are asserted (ACTIVE). Thus completing the WRITE to the desired Byte(s) or the complete data-path. ADSC\ triggered WRITE accesses require a single clock (CLK) machine cycle to complete. The address presented to the input Address bus pins at time of clock HIGH will be the location that the WRITE occurs. The ADV\ pin is ignored during this cycle, and the data WRITTEN to the array will either be a BYTE WRITE or a GLOBAL WRITE depending on the use of the WRITE control functions GW\ and BWE\ as well as the individual BYTE CONTOLS (BWx\). The AS5SP512K18 provides ease of producing very dense arrays via the multiple Chip Enable input pins and Tri-state outputs. Single Cycle Access Operations A Single READ operation is initiated when all of the following conditions are satisfied at the time of Clock (CLK) HIGH: [1] ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all asserted active, and [3] the WRITE signals (GW\, BWE\) are in their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. The address presented to the Address inputs is stored within the Address Registers and Address Counter/Advancement Logic and then passed or presented to the array core. The corresponding data of the addressed location is propagated to the Output Registers and passed to the data bus on the next rising clock via the Output Buffers. The time at which the data is presented to the Data bus is as specified by either the Clock to Data valid specification or the Output Enable to Data Valid spec for the device speed grade chosen. AS5SP512K18 Rev. 2.4 10/13 Micross Components reserves the right to change products or specifications without notice. 3 SSRAM AS5SP512K18 DEEP POWER-DOWN MODE (SLEEP) The AS5SP512K18 has a Deep Power-Down mode and is controlled by the ZZ pin. The ZZ pin is an Asynchronous input and asserting this pin places the SSRAM in a deep power-down mode (SLEEP). While in this mode, Data integrity is guaranteed. For the device to be placed successfully into this operational mode the device must be deselected and the Chip Enables, ADSP\ and ADSC\ remain inactive for the duration of tZZREC after the ZZ input returns LOW. Use of this deep power-down mode conserves power and is very useful in multiple memory page designs where the mode recovery time can be hidden. Accesses pending when entering sleep mode are not considered valid and completion of the operation is not guaranteed. SYNCHRONOUS TRUTH TABLES CE1\ H L L L L L L L X H X H X H X H CE2 X L X L X H H H X X X X X X X X CE3\ X X H X H L L L X X X X X X X X ADSP\ X L L H H L H H H X H X H X H X ADSC\ L X X L L X L L H H H H H H H H ADV\ X X X X X X X X L L L L H H H H WT / RD X X X X X X WT RD RD RD WT WT RD RD WT WT CLK Address Accessed NA NA NA NA NA External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address Operation Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst, READ Begin Burst, WRITE Begin Burst, READ Continue Burst, READ Continue Burst, READ Continue Burst, WRITE Continue Burst, WRITE Suspend Burst, READ Suspend Burst, READ Suspend Burst, WRITE Suspend Burst, WRITE Notes: 1. X = Don’t Care 2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE CAPACITANCE BURST SEQUENCE TABLES Burst Control Pin [MODE] First Address State HIGH Fourth Address Burst Control Pin [MODE] First Address Fourth Address State LOW Interleaved Burst Case 1 Case 2 A1 A0 A1 A0 0 0 0 0 1 0 1 0 1 1 1 1 Case 1 A1 A0 0 0 1 1 Linear Burst Case 2 A1 A0 0 0 1 1 0 1 1 0 1 0 1 0 Case 3 A1 A0 1 1 0 0 1 0 1 0 Case 3 A1 A0 1 1 0 0 0 1 0 1 Case 4 A1 A0 1 1 0 0 1 0 1 0 0 1 0 1 Case 4 A1 A0 1 0 0 1 1 0 1 0 WRITE TABLE GW\ H H H H H L BW\ H L L L L X AS5SP512K18 Rev. 2.4 10/13 BWa\ X H L H L X BWb\ X H H L L X Parameter Input Capacitance Input/Output Capacitance Clock Input Capacitance Symbol CI CIO CCLK Max. 6 8 6 Units pF pF pF ASYNCHRONOUS TRUTH TABLE Operation Power-Down (SLEEP) READ Operation READ READ WRITE Byte [A] WRITE Byte [B] WRITE ALL Bytes WRITE ALL Bytes WRITE De-Selected ZZ H L L L L OE\ X L H X X I/O Status High-Z DQ High-Z Din, High-Z High-Z Micross Components reserves the right to change products or specifications without notice. 4 SSRAM AS5SP512K18 AC TEST LOADS ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on VDD Pin Voltage on VDDQ Pins Voltage on Input Pins Voltage on I/O Pins Power Dissipation Storage Temperature Operating Temperatures [Screening Levels] Symbol VDD VDDQ VIN VIO PD tSTG /IT /ET /XT Min. Max. -0.3 4.6 Units Output V VDD -0.3 VDD+0.3 -0.3 VDDQ+0.3 V 1.6 W R C -65 150 -40 85 -40 105 -55 125 Rt = 50 ohm Zo=50 ohm V V R C R C R C Diagram [A] Vt= Termination Voltage Rt= Termination Resistor 30 pF Vt= 1.50v for 3.3v VDDQ Vt= 1.25v for 2.5v VDDQ R= 317 [email protected] R= 1667 [email protected] Output 3.3/2.5v 5 pF *Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. R= 351 [email protected] R= 1538 [email protected] Diagram [B] DC ELECTRICAL CHARACTERISTICS (VDD=3.3v +10%/-5%, TA= Min. and Max temperatures of Screening level chosen) Symbol VDD VDDQ VoH Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage Test Conditions 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA VoL Output Low Voltage VIH Input High Voltage VIL Input Low Voltage IIL IZZL IOL IDD Input Leakage (except ZZ) & Mode Input Leakage, ZZ pin & Mode Output Leakage Operating Current VDD=Min., IOL=8mA VDD=Min., IOL=1mA VDD=Max., VIN=VSS to VDD Output Disabled, VOUT=VSSQ to VDDQ 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz VDD=Max., f=Max., IOH=0mA ISB1 Automatic CE. Power-down Current -TTL inputs AS5SP512K18 Rev. 2.4 10/13 Automatic CE. Power-down Current - CMOS Inputs 2 1.7 -0.3 -0.3 -5 -30 -5 Max 3.63 VDD Units Notes V 1 V 1,5 V 1,4 V 1,4 0.4 V 1,4 0.4 V 1,4 VDD+0.3 V 1,2 VDD+0.3 V 1,2 0.8 V 1,2 0.7 V 1,2 5 uA 3 30 uA 3 5 uA 290 mA 270 mA 240 mA Max. VDD, Device De-Selected, VIN>/=VIH or VIN</=VIL f=fMAX=1/tCYC ISB2 Min 3.135 2.375 2.4 2 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v 200 180 160 130 mA mA mA mA f=0 Micross Components reserves the right to change products or specifications without notice. 5 SSRAM AS5SP512K18 THERMAL RESISTANCE Parameter ȺJA ȺJC Description ThermalResistance (JunctiontoAmbient) ThermalResistance (JunctiontoCase) TestConditions Testconditionsfollowstandardtest methodsandproceduresfor measuringthermalimpedance,per EIA/JESD51 DQ DQC Package Package Unit 29.41 30.2 o 6.13 6.5 o C/W C/W Notes: [1] AllVoltagesreferencedtoVSS(LogicGround) [2] Overshoot:VIH<+4.6Vfort<tKC/2forI<20mA Undershoot:VIL>Ͳ0.7Vfort<tKC/2forI<20mA PowerͲup:VIH<+3.6VandVDD<3.135Vfort<200ms [[3]] MODEandZZpinshaveinternalpullͲupresistors,andinputleakage+/>+10uA p p p , p g / [4] TheloadusedforVOH,VOLtestingisshowninFigureͲ2for3.3vand2.5Vsupplies. ACloadcurrentishigherthanstatedvalues,ACI/Ocurvescanbemadeavailableuponrequest [5] VDDQshouldneverexceedVDD,VDDandVDDQcanbeconnectedtogether [6] Thisparameterismeasuredforinitialdesignonly AC SWITCHING CHARACTERISTICS (VDD=3.3v -5%/+10%, TA= Min. and Max temperatures of Screening level chosen) Parameter Clock (CLK) Cycle Time Clock (CLK) High Time Clock (CLK) Low Time Clock Access Time Clock (CLK) High to Output Low-Z Clock High to Output High-Z Output Enable to Data Valid Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Address Set-up to CLK High Address Hold from CLK High Address Status Set-up to CLK High Address Status Hold from CLK High Address Advance Set-up to CLK High Address Advance Hold from CLK High Chip Enable Set-up to CLK High (CEx\, CE2) Chip Enable Hold from CLK High (CEx\, CE2) Data Set-up to CLK High Data Hold from CLK High Write Set-up to CLK High (GW\, BWE\, BWx\) Write Hold from CLK High (GW\, BWE\, BWX\) ZZ High to Power Down ZZ Low to Power Up Symbol tCYC tCH tCL tCD tCLZ tCHZ tOE tOH tOELZ tOEHZ tAS tAH tASS tASH tADVS tADVH tCES tCEH tDS tDH tWES tWEH tPD tPU -30 [200Mhz] Min. Max. 5.00 2.00 2.00 3.00 1.25 1.25 3.00 3.00 1.25 0.00 3.00 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 -35 [166Mhz] Min. Max. 6.00 2.40 2.40 3.50 1.25 1.25 3.50 3.50 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 -40 [133Mhz] Min. Max. 7.50 2.50 2.50 4.00 1.25 1.25 3.50 4.00 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles cycles Notes 1 1 2 2,3,4,5 2,3,4,5 6 2,3,4,5 2,3,4,5 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 Notes to Switching Specifications: 1. 2. 3. 4. 5. 6. 7. 8. AS5SP512K18 Rev. 2.4 10/13 Measured as HIGH when above VIH and Low when below VIL This parameter is measured with the output loading shown in AC Test Loads This parameter is sampled Transition is measured +500mV from steady state voltage Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention OE\ is a Don't Care when a Byte or Global Write is sampled LOW A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required SET-UP and HOLD times This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising edges of CLK when either ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous inputs must meet the SET-UP and HOLD times with stable logic levels for all rising edges of clock (CLK) during device operation (enabled). Chip Enable (Cex\, CE2) must be valid at each rising edge of clock (CLK) when either ADSP\ or ADSC\ is LOW to remain enabled. Micross Components reserves the right to change products or specifications without notice. 6 SSRAM AS5SP512K18 AC SWITCHING WAVEFORMS Write Cycle Timing Single Write Burst Write tCYC Pipelined Write tCH CLK tASS tASH tCL ADSP\ ADSP\ Ignored with CE1\ inactive ADSC\ tASS tASH ADV\ tADVS Ax tADVH A1 ADV\ Must be Inactive for ADSP\ Write A3 A2 tAS tAH GW\ tWES tWEH tWEH tWES BWE\, BWx\ tCES tCEH CE1\ Masks ADSP\ CE1\ CE2 CE3\ OE\ tDS tDH DQx,DQPx W1 W2a W2b W2c W2d W3 DON'T CARE UNDEFINED AS5SP512K18 Rev. 2.4 10/13 Micross Components reserves the right to change products or specifications without notice. 7 SSRAM AS5SP512K18 AC SWITCHING WAVEFORMS Read Cycle Timing Single Read Burst Read tCYC tCH Pipelined Read tCL CLK tASS tASH ADSP\ Ignored with CE1\ Inactive ADSP\ ADSC\ Initiated Read ADSC\ Suspend Burst ADV\ tADVS tADVH Ax A2 A1 tAS A3 tAH GW\ tWES tWEH BWE\, BWx\ tCES CE1\ Masks ADSP\ tCEH CE1\ Unselected with CE2 CE2 CE3\ OE\ tOEHZ tOE tCD DQx,DQPx R1 tOH R2a R2b R2c R2d R3a DON'T CARE UNDEFINED AS5SP512K18 Rev. 2.4 10/13 Micross Components reserves the right to change products or specifications without notice. 8 SSRAM AS5SP512K18 AC SWITCHING WAVEFORMS Read/Write Cycle Timing Pipelined Read Burst Read tCYC tCH tCL CLK tASS tASH ADSP\ ADSC\ ADV\ tADVS tADVH tAS Ax A1R A2W A3W A4R A5R tAH GW\ tWES tWEH BWE\, BWx\ tCES tCEH tCES tCEH CE1\ CE2 CE3\ OE\ tOEHZ tOE DQx,DQPx DON'T CARE A1O tOH A2I A4O [a] A3I A4O [b] A4O [c] A4O [d] tOELZ tCD UNDEFINED AS5SP512K18 Rev. 2.4 10/13 Micross Components reserves the right to change products or specifications without notice. 9 SSRAM AS5SP512K18 POWER DOWN (SNOOZE MODE) Power Down or Snooze is a Power conservation mode which when building large/very dense arrays, using multiple devices in a multi-banked or paged array, can greatly reduce the Operating current requirements of your total memory array solution. The device is placed in this mode via the use of the ZZ pin, an asynchronous control pin which when asserted, places the array into the lower power or Power Down mode. Awakening the array or leaving the Power Down (SNOOZE) mode is done so by de-asserting the ZZ pin . While in the Power Down or Snooze mode, Data integrity is guaranteed. Accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. The device must be de-selected prior to entering the Power Down mode, all Chip Enables, ADSP\ and ADSC\ must remain inactive for the duration of ZZ recovery time (tZZREC). ZZ MODE ELECTRICAL CHARACTERISTICS Parameter Symbol Test Conditon Min. Max. Units 3RZHU'RZQ 6122=( 0RGH IDDzz ==!9''9P$ ==$FWLYH 6LJQDO+,*+ WR3RZHU'RZQ tZZS ==!9''9 W&<& QV ==,QDFWLYH 6LJQDO/RZ WR3RZHU8S tZZR ==9 W&<& QV ZZ MODE TIMING DIAGRAM CLK ADSP\ ADSC\ CEx\ CE2 ZZ tZZS IDD AS5SP512K18 Rev. 2.4 10/13 tZZREC IDDzz Micross Components reserves the right to change products or specifications without notice. 10 SSRAM AS5SP512K18 MECHANICAL DIAGRAM 100-Pin TQFP (Package Designator DQ) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH R 0.08 MIN. 0.20 MAX. 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL AS5SP512K18 Rev. 2.4 10/13 A Micross Components reserves the right to change products or specifications without notice. 11 SSRAM AS5SP512K18 ORDERING INFORMATION Part Number TQFP AS5SP512K18DQ-30IT AS5SP512K18DQ-35IT AS5SP512K18DQ-40IT AS5SP512K18DQ-30ET AS5SP512K18DQ-35ET AS5SP512K18DQ-40ET AS5SP512K18DQ-35XT AS5SP512K18DQ-40XT Configuration Clock (Mhz) 3.0 3.5 4.0 3.0 3.5 4.0 3.5 4.0 200 166 133 200 166 133 166 133 512Kx18, 3.3vCore/3.3,2.5v IO 512Kx18, 3.3vCore/3.3,2.5v IO 512Kx18, 3.3vCore/3.3,2.5v IO 512Kx18, 3.3vCore/3.3,2.5v IO 512Kx18, 3.3vCore/3.3,2.5v IO 512Kx18, 3.3vCore/3.3,2.5v IO 512Kx18, 3.3vCore/3.3,2.5v IO 512Kx18, 3.3vCore/3.3,2.5v IO AVAILABLE PROCESSES IT = Industrial Temperature Range ET = Enhanced Temperature Range XT = Military Temperature Range AS5SP512K18 Rev. 2.4 10/13 tCD (ns) -40oC to +85oC -40oC to +105oC -55oC to +125oC Micross Components reserves the right to change products or specifications without notice. 12 SSRAM AS5SP512K18 DOCUMENT TITLE 9Mb, 512K x 18, Synchronous SRAM REVISION HISTORY Rev # 2.1 History Updated Micross information 2.2 Added copper lead frame & RoHS June 2011 options. Deleted ISB3 and ISB4. Changed: From To CCLK &CI 5pF 6pF CIO 5pF 8pF IDDzz 35mA 75mA IDD (200 MHz) 250mA 290mA IDD (166 MHz) 220mA 270mA IDD (133 MHz) 185mA 240mA ISB1 (200 MHz) 120mA 200mA ISB1 (166 MHz) 110mA 180mA ISB1 (133 MHz) 100mA 160mA ISB2 30mA 130mA Release 2.3 Added Thermal Resistance for DQC package, page 6. September 2011 Release 2.4 Removed Cu-lead frame option October 2013 Release AS5SP512K18 Rev. 2.4 10/13 Release Date October 2010 Status Release Micross Components reserves the right to change products or specifications without notice. 13