ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 12-Bit, 1-MSPS, MICRO-POWER, MINIATURE SAR ANALOG-TO-DIGITAL CONVERTERS Check for Samples: ADS7886 FEATURES APPLICATIONS • • • • • • • 1 • • • • • • • 1-MHz Sample Rate Serial Device 12-Bit Resolution Zero Latency 20-MHz Serial Interface Supply Range: 2.35 V to 5.25 V Typical Power Dissipation at 1 MSPS: – 3.9 mW at 3-V VDD – 7.5 mW at 5-V VDD INL ±1.25 LSB Maximum, ±0.65 LSB (Typical) DNL ±1 LSB Maximum, +0.4 / -0.65 LSB (Typical) Typical AC Performance: 72.25 dB SINAD, -84 dB THD Unipolar Input Range: 0 V to VDD Power Down Current: 1 µA Wide Input Bandwidth: 15 MHz at 3 dB 6-Pin SOT23 and SC70 Packages • • • • • • • Base Band Converters in Radio Communication Motor Current/Bus Voltage Sensors in Digital Drives Optical Networking (DWDM, MEMS Based Switching) Optical Sensors Battery Powered Systems Medical Instrumentations High-Speed Data Acquisition Systems High-Speed Closed-Loop Systems DESCRIPTION The ADS7886 is a 12-bit, 1-MSPS analog-to-digital converter (ADC). The device includes a capacitor based SAR A/D converter with inherent sample and hold. The serial interface in each device is controlled by the CS and SCLK signals for glueless connections with microprocessors and DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial data output. The device operates from a wide supply range from 2.35 V to 5.25 V. The low power consumption of the device makes it suitable for battery-powered applications. The device also includes a powerdown feature for power saving at lower conversion speeds. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when device supply is 2.35 V. This feature is useful when digital signals are coming from other circuit with different supply levels. Also this relaxes restriction on power up sequencing. The ADS7886 is available in 6-pin SOT23 and SC70 packages and is specified for operation from -40°C to 125°C. Table 1. Micro-Power Miniature SAR Converter Family BIT < 300 KSPS 300 KSPS – 1.25 MSPS 12-Bit ADS7866 (1.2 VDD to 3.6 VDD) ADS7886 (2.35 VDD to 5.25 VDD) 10-Bit ADS7867 (1.2 VDD to 3.6 VDD) ADS7887 (2.35 VDD to 5.25 VDD) 8-Bit ADS7868 (1.2 VDD to 3.6 VDD) ADS7888 (2.35 VDD to 5.25 VDD) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2009, Texas Instruments Incorporated ADS7886 SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SAR +IN OUTPUT LATCHES and 3−STATE DRIVERS CDAC SDO COMPARATOR VDD CONVERSION and CONTROL LOGIC SCLK CS PACKAGE/ORDERING INFORMATION (1) DEVICE MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES AT RESOLUTION (BIT) PACKAGE TYPE 6-Pin SOT23 ADS7886SB ±1.25 ±1 ±2 2 ORDERING INFORMATION TRANSPORT MEDIA QUANTITY ADS7886SBDBVT Tape and reel 250 ADS7886SBDBVR Tape and reel 3000 ADS7886SBDCKT Tape and reel 250 ADS7886SBDCKR Tape and reel 3000 ADS7886SDBVT Tape and reel 250 ADS7886SDBVR Tape and reel 3000 ADS7886SDCKT Tape and reel 250 ADS7886SDCKR Tape and reel 3000 BBAQ DCK BNL DBV 11 BBAQ –40°C to 125°C 6-Pin SC70 (1) PACKAGE MARKING –40°C to 125°C 6-Pin SOT23 ±2 TEMPERATURE RANGE DBV 12 6-Pin SC70 ADS7886S PACKAGE DESIGNATOR DCK BNL For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) UNIT +IN to AGND –0.3 V to +VDD +0.3 V +VDD to AGND –0.3 V to 7 V Digital input voltage to GND –0.3 V to (7 V) Digital output to GND –0.3 V to (+VDD + 0.3 V) Operating temperature range –40°C to 125°C Storage temperature range –65°C to 150°C Junction temperature (TJ Max) 150°C Power dissipation, SOT23 and SC70 packages θJA Thermal impedance Lead temperature, soldering (1) (TJ Max–TA)/θJA SOT23 295.2°C/W SC70 351.3°C/W Vapor phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS +VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, f(sample) = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD V ANALOG INPUT Full-scale input voltage span (1) Absolute input voltage range CI Input capacitance (2) Ilkg Input leakage current 0 +IN –0.2 TA = 125°C VDD+0.2 V 21 pF 40 nA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes INL Integral nonlinearity DNL Differential nonlinearity EO Offset error (4) EG Gain error ADS7886SB 12 ADS7886S 11 ADS7886SB ADS7886S –1.25 –1 ADS7886S -2 VDD = 4.75 V to 5.25 V ±0.65 2 ADS7886SB VDD = 2.35 V to 3.6 V Bits 1.25 2 +0.4/-0.65 1 2 –2.5 ±0.5 2.5 -2 ±0.5 2 –1.75 ±0.5 1.75 760 800 LSB (3) LSB LSB LSB SAMPLING DYNAMICS Conversion time 20-MHz SCLK Acquisition time Maximum throughput rate ns 325 ns 20-MHz SCLK 1 Aperture delay MHz 5 ns Step Response 160 ns Overvoltage recovery 160 ns DYNAMIC CHARACTERISTICS SNR (1) (2) (3) (4) Signal-to-noise ratio VDD = 2.35 V to 3.6 V, fI = 100 kHz 69 71.25 VDD = 4.75 V to 5.25 V, fI = 100 kHz 70 72.25 dB Ideal input span; does not include gain or offset error. See Figure 28 for details on the sampling circuit. LSB means least significant bit. Measured relative to an ideal full-scale input. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 3 ADS7886 SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) +VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, f(sample) = 1 MHz (unless otherwise noted) PARAMETER MIN TYP VDD = 2.35 V to 3.6 V, fI = 100 kHz TEST CONDITIONS 69 71.25 VDD = 4.75 V to 5.25 V, fI = 100 kHz 70 72.25 SINAD Signal-to-noise and distortion THD Total harmonic distortion (5) fI = 100 kHz –84 SFDR Spurious free dynamic range fI = 100 kHz 85.5 Full power bandwidth At –3 dB MAX UNIT dB dB dB 15 MHz DIGITAL INPUT/OUTPUT Logic family — CMOS VDD = 2.35 V to 3.6 V 1.8 5.25 VDD = 3.6 V to 5.25 V 2.4 5.25 VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage I(source) = 200 µA VOL Low-level output voltage I(sink) = 200 µA VDD = 5 V 0.8 VDD = 3 V 0.4 VDD–0.2 0.4 V V V POWER SUPPLY REQUIREMENTS +VDD Supply voltage 2.35 VDD = 2.35 V to 3.6 V, 1-MHz throughput Supply current (normal mode) Power down state supply current Power dissipation at 1-MHz throughput Power dissipation in static state VDD = 4.75 V to 5.25 V, 1-MHz throughput 1.3 1.5 1.5 2 1.1 VDD = 4.75 V to 5.25 V, static state 1.5 SCLK off 1 SCLK on (20 MHz) 200 VDD = 3 V 3.9 4.5 VDD = 5 V 7.5 10 VDD = 3 V 3.3 VDD = 5 V 7.5 0.1 Invalid conversions after power up or reset 4 5.25 VDD = 2.35 V to 3.6 V, static state Power up time (5) 3.3 V mA µA mW mW µs 1 Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 TIMING REQUIREMENTS (see Figure 1 and Figure 2) All specifications typical at TA = –40°C to 125°C, VDD = 2.35 V to 5.25 V (unless otherwise specified). TEST CONDITIONS (1) PARAMETER tconv Conversion time ADS7866 tq Minimum quiet time needed from bus 3-state to start of next conversion td1 Delay time, CS low to first data (0) out tsu1 Setup time, CS low to SCLK low td2 Delay time, SCLK falling to SDO th1 Hold time, SCLK falling to data valid (2) td3 Delay time, 16th SCLK falling edge to SDO 3-state tw1 Pulse duration, CS td4 Delay time, CS high to SDO 3-state twH Pulse duration, SCLK high twL Pulse duration, SCLK low Frequency, SCLK MIN TYP MAX VDD = 3 V 16 × tSCLK VDD = 5 V 16 × tSCLK VDD = 3 V 40 VDD = 5 V 40 15 25 VDD = 5 V 13 25 10 VDD = 5 V 10 15 25 VDD = 5 V 13 25 7 VDD > 5 V 5.5 ns ns VDD = 3 V 10 25 VDD = 5 V 8 20 VDD = 3 V 25 40 VDD = 5 V 25 40 VDD = 3 V 17 30 VDD = 5 V 15 25 VDD = 3 V 0.4 × tSCLK VDD = 5 V 0.4 × tSCLK VDD = 3 V 0.4 × tSCLK VDD = 5 V 0.4 × tSCLK ns ns ns ns ns VDD = 3 V 20 VDD = 5 V 20 Delay time, second falling edge of clock and CS to enter in powerdown (use min spec not to accidently enter in powerdown) Figure 2 VDD = 3 V -2 5 td5 VDD = 5 V -2 5 Delay time, CS and 10th falling edge of clock to enter in powerdown (use max spec not to accidently enter in powerdown) Figure 2 VDD = 3 V 2 -5 td6 VDD = 5 V 2 -5 (1) (2) ns ns VDD = 3 V VDD < 3 V ns ns VDD = 3 V VDD = 3 V UNIT MHz ns ns 3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V. With 50-pf load. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 5 ADS7886 SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 www.ti.com DEVICE INFORMATION SOT23/SC70 PACKAGE (TOP VIEW) VDD 1 6 CS GND 2 5 SDO VIN 3 4 SCLK TERMINAL FUNCTIONS TERMINAL NAME I/O NO. DESCRIPTION VDD 1 – Power supply input also acts like a reference voltage to ADC. GND 2 – Ground for power supply, all analog and digital signals are referred with respect to this pin. VIN 3 I Analog signal input SCLK 4 I Serial clock SDO 5 O Serial data out CS 6 I Chip select signal, active low NORMAL OPERATION The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 12-bit data in MSB first format. The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 13th falling edge. This point is indicated by b in Figure 1. CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in the Electrical Characteristics table. a tconv t w1 b CS t su1 1 SCLK 4 0 13 6 5 15 14 16 th1 t d2 t d1 SDO 2 0 0 D11 t d3 D10 D3 D2 D1 D0 tq 1/throughput Figure 1. Interface Timing Diagram 6 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 POWER DOWN MODE The device enters power down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power down condition as shown in Figure 2. td6 td5 CS 1 2 3 4 5 9 10 16 SCLK SDO Figure 2. Entering Power Down Mode A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power down mode. For the device to come to the fully powered up condition it takes 1 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 3. It is not necessary to continue until the 16th clock if the next conversion starts 1 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met. Device Starts Powering Up Device Fully Powered-Up CS SCLK 1 SDO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 Invalid Data 7 8 9 10 11 12 13 14 15 16 Valid Data Figure 3. Exiting Power Down Mode Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 7 ADS7886 SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SCLK FREQUENCY 1.6 1.6 fs = 1 MSPS, fSCLK = 20 MHz fSCLK = 20 MHz, o TA = 25 C, Power Down Wih SCLK = Free Running 1.4 o 125 C 1.2 o 25 C 1.3 1.2 o −40 C 1.2 IDD − Supply Current − mA IDD − Supply Current − mA IDD − Supply Current − mA 1.4 o TA = 25 C 1.5 1.4 SUPPLY CURRENT vs SAMPLE RATE 5V 1 2.35 V 0.8 0.6 0.4 1 0.8 5V 0.6 0.4 2.35 V 1.1 0.2 0.2 1 2.35 3.075 3.8 4.525 0 0 5.25 0 VDD − Supply Voltage − V 5 10 15 20 Figure 4. 0 50 100 150 200 250 300 350 fs − Sample Rate − KSPS f − SCLK Frequency − MHz Figure 5. Figure 6. ANALOG INPUT LEAKAGE CURRENT vs FREE-AIR TEMPERATURE 40 Leakage Current − nA 30 20 10 5 V Input 0 −10 0 V Input −20 −30 −40 −40 15 70 125 o TA − Free-Air Temperature − C Figure 7. 8 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE 73 73 72.5 72.5 72 71.5 71 70.5 fs = 1 MSPS, VDD = 5 V, 70 o TA = 25 C SNR − Signal-to-Noise Ratio − dB 73 72 71.5 71 70.5 fs = 1 MSPS, fI = 100 kHz, 70 o TA = 25 C 69.5 69.5 69 10 100 fI − Input Frequency − kHz 2.35 1000 5V 72 71.5 2.35 V 71 70.5 fs = 1 MSPS, 70 fI = 100 kHz 69.5 69 1 3.075 3.8 4.525 69 −40 5.25 VDD − Supply Voltage − V 15 70 125 o TA − Free-Air Temperature − C Figure 8. Figure 9. Figure 10. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs SUPPLY VOLTAGE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE −84 -80 -80 −87 −88 −89 −90 −91 −92 −93 fs = 1 MSPS, fI = 100 kHz, THD − Total Harmonic Distortion − dB −86 THD − Total Harmonic Distortion − dB fS = 1 MSPS, o TA 25 C, VDD = 5 V −85 THD − Total Harmonic Distortion − dB SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE 72.5 SNR − Signal-to-Noise Ratio − dB SNR − Signal-to-Noise Ratio − dB SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY TA = 25oC -82 -84 -86 -88 fs = 1 MSPS, -81 fI = 100 kHz -82 -83 2.35 V -84 -85 5V -86 -87 -88 -89 −94 1 10 -90 2.35 100 fi − Input Frequency − kHz 3.8 4.525 -90 5.25 15 −40 VDD − Supply Voltage − V 70 125 o TA − Free-Air Temperature − C Figure 11. Figure 12. Figure 13. SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY SPURIOUS FREE DYNAMIC RANGE vs SUPPLY VOLTAGE SPURIOUS FREE DYNAMIC RANGE vs SUPPLY VOLTAGE 87 86.5 86 85.5 fs = 1 MSPS, 85 VDD = 5 V, 84.5 o TA = 25 C 84 83.5 83 82.5 82 1 10 100 fi − Input Frequency − kHz Figure 14. 86.6 SFDR − Spurious Free Dynamic Range - dB SFDR − Spurious Free Dynamic Range − dB 87 SFDR − Spurious Free Dynamic Range − dB 3.075 86.5 86 85.5 85 84.5 84 83.5 83 fs = 1 MSPS, fI = 100 kHz, o TA = 25 C 82.5 82 2.35 3.075 3.8 4.525 VDD − Supply Voltage − V Figure 15. 5.25 86.4 5V 86.2 86 fs = 1 MSPS, fI = 100 kHz, o TA = 25 C 85.8 85.6 2.35 V 85.4 85.2 −40 15 70 125 o TA − Free-Air Temperature − C Figure 16. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 9 ADS7886 SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) OFFSET ERROR vs SUPPLY VOLTAGE OFFSET ERROR vs FREE-AIR TEMPERATURE 1 1 1.5 EO − Offset Error - LSBs 1 0.5 0 -0.5 fs = 1 MSPS, o TA = 25 C 0.8 fs = 1 MSPS, VDD = 5 V 0.75 0.6 0.5 EG − Gain Error - LSBs fs = 1 MSPS, o TA = 25 C EO − Offset Error - LSBs GAIN ERROR vs SUPPLY VOLTAGE 0.25 0 -0.25 0.4 0.2 0 −0.2 −0.4 -0.5 −0.6 -1 -0.75 -1.5 2.35 3.075 3.8 4.525 −0.8 -1 −40 5.25 −1 15 70 125 2.35 3.075 o TA − Free-Air Temperature − C VDD − Supply Voltage − V Figure 18. Figure 19. GAIN ERROR vs FREE-AIR TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 1 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 15 −40 70 125 Max 0.4 0.2 0 −0.2 −0.4 Min −0.6 −0.8 −1 2.35 o 3.075 3.8 4.525 5.25 0.6 Max 0.4 0.2 0 −0.2 −0.4 Min −0.6 −0.8 −1 −40 VDD − Supply Voltage − V Figure 20. 15 70 125 o TA − Free-Air Temperature − C Figure 21. Figure 22. INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 1.25 1.25 ffs == 11 MSPS, MSPS, s o oC TTA == 25 A 25 C fs = 1 MSPS, VDD = 5 V 0.75 INL − Integral Nonlinearity - LSBs INL − Integral Nonlinearity - LSBs fs = 1 MSPS, VDD = 5 V 0.8 0.6 TA − Free-Air Temperature − C Max 0.25 −0.25 Min −0.75 −1.25 2.35 3.075 3.8 4.525 5.25 0.75 Max 0.25 −0.25 Min −0.75 −1.25 −40 15 70 125 o VDD − Supply Voltage − V TA − Free-Air Temperature − C Figure 23. 10 5.25 1 fs = 1 MSPS, o TA = 25 C 0.8 DNL − Differential Nonlinearity - LSBs fs = 1 MSPS, VDD = 5 V DNL − Differential Linearity Error - LSBs EG − Gain Error - LSBs 0.6 4.525 Figure 17. 1 0.8 3.8 VDD − Supply Voltage − V Figure 24. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS (continued) DNL 1 0.8 VDD = 2.35 V, fs = 1 MSPS, o TA = 25 C DNL - LSBs 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 1024 2048 3072 4096 3072 4096 Output Code Figure 25. INL 1 0.8 INL - LSBs 0.6 0.4 0.2 0 −0.2 −0.4 VDD = 2.35 V, fs = 1 MSPS, TA = 25oC −0.6 −0.8 −1 0 1024 2048 Output Code Figure 26. FFT 0 VDD = 2.35 V, fs = 1 MSPS, TA = 25oC, Amplitude − dB −20 −40 −60 fI = 100 kHz, 8192 Points −80 −100 −120 −140 −160 0 100000 200000 300000 400000 500000 f − Frequency − Hz Figure 27. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 11 ADS7886 SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 www.ti.com APPLICATION INFORMATION VDD 20 W 60 W IN 16 pF 60 W 5 pF GND Figure 28. Typical Equivalent Sampling Circuit Driving the VIN and VDD Pins The VIN input should be driven with a low impedance source. In most cases additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifier buffer. The reference voltage for the A/D converter is derived from the supply voltage internally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters should be driven with a low impedance source and should be decoupled to the ground. A 1-µF storage capacitor and a 10-nF decoupling capacitor should be placed close to the device. Wide, low impedance traces should be used to connect the capacitor to the pins of the device. The ADS7886 draws very little current from the supply lines. The supply line can be driven by either: • Directly from the system supply. • A reference output from a low drift and low drop out reference voltage generator like REF3030 or REF3130. The ADS7886 operates from a wide range of supply voltages. The actual choice of the reference voltage generator would depend upon the system. Figure 30 shows one possible application circuit. • A low-pass filtered system supply followed by a buffer, like the zero-drift OPA735, can also be used in cases where the system power supply is noisy. Care should be taken to ensure that the voltage at the VDD input does not exceed 7 V to avoid damage to the converter. This can be done easily using single supply CMOS amplifiers like the OPA735. Figure 31 shows one possible application circuit. VDD 1 mF VDD CS VIN SDO GND SCLK 10 nF Figure 29. Supply/Reference Decoupling Capacitors 5V REF3030 IN 1 mF 3V OUT VDD CS VIN SDO GND SCLK GND 1 mF 10 nF Figure 30. Using the REF3030 Reference 12 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 ADS7886 www.ti.com SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 5V C1 R1 10 W 7V _ R2 VDD CS VIN SDO GND SCLK + 1 mF 1 mF 10 nF Figure 31. Buffering with the OPA735 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 13 ADS7886 SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009 www.ti.com REVISION HISTORY Changes from Original (SEPTEMBER 2005) to Revision A Page • Added VIH information ........................................................................................................................................................... 4 • Changed VIH information ....................................................................................................................................................... 4 14 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7886 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7886SBDBVR ACTIVE SOT-23 DBV 6 3000 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BBAQ ADS7886SBDBVT ACTIVE SOT-23 DBV 6 250 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BBAQ ADS7886SBDCKR ACTIVE SC70 DCK 6 3000 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNL ADS7886SBDCKT ACTIVE SC70 DCK 6 250 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNL ADS7886SDBVR ACTIVE SOT-23 DBV 6 3000 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BBAQ ADS7886SDBVT ACTIVE SOT-23 DBV 6 250 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BBAQ ADS7886SDCKR ACTIVE SC70 DCK 6 3000 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNL ADS7886SDCKT ACTIVE SC70 DCK 6 250 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNL (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ ADS7886SBDBVR SOT-23 3000 177.8 9.7 3.2 DBV 6 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.1 1.39 4.0 8.0 Q3 ADS7886SBDBVT SOT-23 DBV 6 250 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3 ADS7886SBDCKR SC70 DCK 6 3000 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3 ADS7886SBDCKT SC70 DCK 6 250 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3 ADS7886SDBVR SOT-23 DBV 6 3000 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3 ADS7886SDBVT SOT-23 DBV 6 250 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3 ADS7886SDCKR SC70 DCK 6 3000 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3 ADS7886SDCKT SC70 DCK 6 250 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7886SBDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0 ADS7886SBDBVT SOT-23 DBV 6 250 184.0 184.0 50.0 ADS7886SBDCKR SC70 DCK 6 3000 184.0 184.0 50.0 ADS7886SBDCKT SC70 DCK 6 250 184.0 184.0 50.0 ADS7886SDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0 ADS7886SDBVT SOT-23 DBV 6 250 184.0 184.0 50.0 ADS7886SDCKR SC70 DCK 6 3000 184.0 184.0 50.0 ADS7886SDCKT SC70 DCK 6 250 184.0 184.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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