Fairchild FDMA3023PZ Dual p-channel powertrenchâ® mosfet -30 v, -2.9 a, 90 mî© Datasheet

FDMA3023PZ
tm
Dual P-Channel PowerTrench® MOSFET
-30 V, -2.9 A, 90 mΩ
Features
General Description
This device is designed specifically as a single package solution
for the battery charge switch in cellular handset and other
ultra-portable applications. It features two independent
P-Channel MOSFETs with low on-state resistance for minimum
conduction losses. When connected in the typical common
source configuration, bi-directional current flow is possible.
„ Max rDS(on) = 90 mΩ at VGS = -4.5 V, ID = -2.9 A
„ Max rDS(on) = 130 mΩ at VGS = -2.5 V, ID = -2.6 A
„ Max rDS(on) = 170 mΩ at VGS = -1.8 V, ID = -1.7 A
„ Max rDS(on) = 240 mΩ at VGS = -1.5 V, ID = -1.0 A
„ Low profile - 0.8 mm maximum - in the new package MicroFET
2x2 mm
The MicroFET 2X2 package offers exceptional thermal
performance for its physical size and is well suited to linear mode
applications.
„ HBM ESD protection level > 2 kV (Note 3)
„ RoHS Compliant
„ Free from halogenated compounds and antimony
oxides
PIN 1
S1
G1
D1
D1
D2
S1
1
1
66
D1
G1
22
5
G2
D2
3
3
4
S2
D2
G2 S2
5
4
MicroFET 2x2
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current -Continuous
ID
(Note 1a)
-Pulsed
PD
TJ, TSTG
Ratings
-30
Units
V
±8
V
-2.9
-6
Power Dissipation
(Note 1a)
1.4
Power Dissipation
(Note 1b)
0.7
Operating and Storage Junction Temperature Range
-55 to +150
A
W
°C
Thermal Characteristics
RθJA
Thermal Resistance for Single Operation, Junction to Ambient
(Note 1a)
86
RθJA
Thermal Resistance for Single Operation, Junction to Ambient
(Note 1b)
173
RθJA
Thermal Resistance for Dual Operation, Junction to Ambient
(Note 1c)
69
RθJA
Thermal Resistance for Dual Operation, Junction to Ambient
(Note 1d)
151
°C/W
Package Marking and Ordering Information
Device Marking
323
Device
FDMA3023PZ
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
Package
MicroFET 2X2
1
Reel Size
7 ’’
Tape Width
8 mm
Quantity
3000 units
www.fairchildsemi.com
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
December 2008
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = -250 µA, VGS = 0 V
∆BVDSS
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 µA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = -24 V, VGS = 0 V
-1
µA
IGSS
Gate to Source Leakage Current
VGS = ±8 V, VDS = 0 V
±100
nA
-1.0
V
-30
V
-24
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = -250 µA
∆VGS(th)
∆TJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = -250 µA, referenced to 25 °C
3
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
-0.4
-0.6
mV/°C
VGS = -4.5 V, ID = -2.9 A
71
90
VGS = -2.5 V, ID = -2.6 A
97
130
VGS = -1.8 V, ID = -1.7 A
122
170
VGS = -1.5 V, ID = -1.0 A
151
240
VGS = -4.5 V, ID = -2.9 A, TJ = 125 °C
110
140
VDS = -5 V, ID = -2.9 A
10
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = -15 V, VGS = 0 V,
f = 1 MHz
400
530
pF
55
70
pF
45
65
pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
VDD = -15 V, ID = -1.0 A,
VGS = -4.5 V, RGEN = 6 Ω
5
10
ns
4
10
ns
ns
td(off)
Turn-Off Delay Time
62
100
tf
Fall Time
18
33
ns
Qg(TOT)
Total Gate Charge
7.9
11
nC
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
VDD = -15 V, ID = -2.9 A
VGS = -4.5 V
0.9
nC
1.9
nC
Drain-Source Diode Characteristics
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
VGS = 0 V, IS = -1.1 A
-1.1
(Note 2)
IF = -2.9 A, di/dt = 100 A/µs
2
A
-0.8
-1.2
V
18
33
ns
6.6
13
nC
www.fairchildsemi.com
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
1. RθJA is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the
user's board design.
(a) RθJA = 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation.
(b) RθJA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation.
(c) RθJA = 69 oC/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 ” x 1.5 ” x 0.062 ” thick PCB. For dual operation.
(d) RθJA = 151 oC/W when mounted on a minimum pad of 2 oz copper. For dual operation.
a)86 oC/W when
mounted on a 1
in2 pad of 2 oz
copper.
b)173 oC/W when
mounted on a
minimum pad of 2
oz copper.
c)69 oC/W when
mounted on a 1 in2
pad of 2 oz copper.
d)151 oC/W when
mounted on a
minimum pad of 2 oz
copper.
2. Pulse Test : Pulse Width < 300 us, Duty Cycle < 2.0%
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
3
www.fairchildsemi.com
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
Notes:
6
VGS = -4.5 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
-ID, DRAIN CURRENT (A)
6
VGS = -3.5 V
5
VGS = -2.5 V
4
VGS = -1.8 V
3
VGS = -1.5 V
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
2
1
0
0
0.5
1.0
1.5
2.0
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
5
VGS = -1.5 V
4
3
1
1
2
4
5
6
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
400
ID = -2.9 A
VGS = -4.5 V
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
SOURCE ON-RESISTANCE (mΩ)
ID = -1.45 A
300
rDS(on), DRAIN TO
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
3
-ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
1.2
1.0
200
TJ = 125 oC
100
0.8
0.6
-75
-50
TJ = 25 oC
0
1.0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure 4. On-Resistance vs Gate to
Source Voltage
10
6
-IS, REVERSE DRAIN CURRENT (A)
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
5
-ID, DRAIN CURRENT (A)
VGS = -4.5 V
VGS = -3.5 V
0
-VDS, DRAIN TO SOURCE VOLTAGE (V)
1.4
VGS = -1.8 V
VGS = -2.5 V
2
VDS = -5 V
4
3
TJ = 125 oC
2
TJ = 25 oC
1
TJ =
0
0.5
1.0
-55 oC
1.5
VGS = 0 V
1
TJ = 125 oC
0.1
TJ = 25 oC
0.01
TJ = -55 oC
0.001
0.2
2.0
0.4
0.6
0.8
1.0
-VGS, GATE TO SOURCE VOLTAGE (V)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
4
1.2
www.fairchildsemi.com
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
1000
ID = -2.9 A
4
VDD = -10 V
CAPACITANCE (pF)
-VGS, GATE TO SOURCE VOLTAGE (V)
5
VDD = -15 V
3
VDD = -20 V
2
1
Ciss
100
Coss
0
0
2
4
6
8
10
0.1
10
Qg, GATE CHARGE (nC)
1
30
Figure 8. Capacitance vs Drain
to Source Voltage
10
-2
10
THIS AREA IS
LIMITED BY rDS(on)
10
-ID, DRAIN CURRENT (A)
VGS = 0 V
-3
-4
10
-5
10
TJ = 125 oC
-6
10
TJ = 25 oC
-7
10
1 ms
1
10 ms
100 ms
0.1
1s
SINGLE PULSE
TJ = MAX RATED
10 s
RθJA = 173 oC/W
-8
10
o
DC
TA = 25 C
0.01
0.01
-9
10
10
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
-Ig, GATE LEAKAGE CURRENT (A)
Crss
f = 1 MHz
VGS = 0 V
0
3
6
9
12
15
0.1
1
10
100 200
-VDS, DRAIN to SOURCE VOLTAGE (V)
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 9. Gate Leakage vs Gate to Source Voltage
Figure 10. Forward Bias Safe Operating Area
200
P(PK), PEAK TRANSIENT POWER (W)
100
VGS = -4.5 V
SINGLE PULSE
RθJA = 173 oC/W
TA = 25 oC
10
1
0.5
-3
10
-2
10
-1
10
1
10
1000
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
5
www.fairchildsemi.com
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
2
IMPEDANCE, ZθJA
NORMALIZED THERMAL
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
o
0.01
0.005
-3
10
RθJA = 173 C/W
-2
10
-1
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
6
www.fairchildsemi.com
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
Dimensional Outline and Pad Layout
2.0
A
2X
(1.80)
B
(0.80)
(0.50)
(1.00)
2.0
(2.25)
(0.42)
PIN#1 QUADRANT
(0.42)
2X
TOP VIEW
(0.10)
0.65
RECOMMENDED LAND PATTERN
(0.20)
0.8 MAX
0.05
0.00
C
SIDE VIEW
PIN#1 IDENT
1.64? .10
0.35? .10
(0.185)
0.86? .10
(0.65)
0.20
0.35
D
0.25~0.35
0.65
1.30
BOTTOMVIEW
A. CONFORMS TOJEDEC REGISTRATION MO-229,
VARIATION VCCC EXCEPT AS NOTED.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. NON-JEDEC DUAL DAP
MLP06JrevB
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
7
www.fairchildsemi.com
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications may
change in any manner without notice.
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make changes at any time without notice to
improve design.
No Identification Needed
Full Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I37
©2008 Fairchild Semiconductor Corporation
FDMA3023PZ Rev.B1
8
www.fairchildsemi.com
FDMA3023PZ Dual P-Channel PowerTrench® MOSFET
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