APA0713 1.1W Mono Low-Voltage Audio Power Amplifier Features General Description • • • Operating Voltage : 2.6V-5.5V The APA0713 is a bridged-tied load (BTL) audio power APA0713 Compatible with TPA751 Supply Current – IDD=1.3mA at VDD=5V ,BTL mode – IDD=0.9mA at VDD=3.3V ,BTL mode Low Shutdown Current – IDD=0.1µA Low Distortion – 630mW, at VDD=5V, BTL, RL=8Ω THD+N=0.15% – 280mW, at VDD=3.3V, BTL, RL=8Ω THD+N=0.15% Output Power at 1% THD+N – 900mW, at VDD=5V, BTL, RL=8Ω – 400mW, at VDD=3.3V, BTL, RL=8Ω at 10% THD+N – 1.1W at VDD=5V, BTL, RL=8Ω – 480mW at VDD=3.3V, BTL, RL=8Ω Depop Circuitry Integrated Thermal Shutdown Protection and Over Current Protection Circuitry High supply voltage ripple rejection Surface-Mount Packaging – 8 pin SOP amplifier developed especially for low-voltage applications where internal speakers operation is required. • • • • • • • • Operating with a 5V supply, the APA0713 can deliver 1.1W of continuous power into a BTL 8Ω load at 10% THD+N throughout voice band frequencies. Although this device is characterized out to 20kHz, its operation is optimized for n a r r o w b an d ap p l i c a t i o n s s u c h as w i r e l e s s communications. The BTL configuration eliminates the need for external coupling capacitors on the output in most applications, which is particularly important for small battery-powered equipment. This device features a shutdown mode for power-sensitive applications with special depop circuitry to eliminate speaker noise when exiting shutdown mode. The APA0713 is available in8-pin SOP. Applications • Mobil Phones • PDAs • Digital Cameras • Portable Electronic Devices Lead Free Available (RoHS Compliant) Ordering and Marking Information Package Code K : SOP-8 Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA0713 Assembly Material Handling Code Temperature Range Package Code APA0713 K : APA0713 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr, 2012 1 www.anpec.com.tw APA0713 Pin Configuration 8 VO- Shutdown 1 Bypass 2 7 GND IN+ 3 6 VDD IN- 4 5 VO+ SOP-8 Absolute Maximum Ratings (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter Rating Unit -0.3 to 6 V V VDD Supply Voltage VIN Input Voltage Range, Shutdown, SE/BTL -0.3 to VDD+0.3 TA Operating Ambient Temperature Range -40 to 85 TJ Maximum Junction Temperature TSTG Storage Temperature Range TSDR Lead Soldering Temperature, 10 seconds PD °C Internally Limited* °C -65 to +150 °C 260 °C Internally Limited W 1 Power Dissipation Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2 : APA0713 starts its internal thermal shutdown protection when junction temperature ramps up to 170°C. Recommended Operating Conditions Symbol Parameter Test Conditions VDD Supply Voltage VIH High-Level Voltage Shutdown VIL Low-Level Voltage Shutdown Min. Max. Unit 2.6 5.5 V V 2.2 0.4 V Thermal Characteristics Symbol R THJA Parameter Value Thermal Resistance from Junction to Ambient in Free Air SOP-8 (Note 2) 200 Unit °C/W Note 2: 3.42in2 printed circuit board with 20z trace and copper. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 2 www.anpec.com.tw APA0713 Electrical Characteristics Electrical Characteristics at Specified Free - Air Temperature VDD = 3.3V, TA = 25°C (unless otherwise noted) Symbol VOS IDD IDD(SD) Parameter APA0713 Test Conditions Output Offset Voltage Min. Typ. Max. RL = 8Ω, RF = 10kΩ Unit 20 mV Supply Current BTL mode, RF = 10kΩ 0.9 1.8 mA Supply Current, Shutdown Mode RF = 10kΩ 0.1 2 µA |IH| Shutdown, VI = VDD 1 µA |IL| Shutdown, VI = 0V 1 µA Operating characteristic, VDD = 3.3V, TA = 25°C, RL = 8Ω PO THD+N Bom B1 PSRR THD+N = 1%, BTL mode, RL = 8Ω 400 THD+N = 1%, BTL mode, RL = 4Ω 600 (Note 1) PO = 280mW, BTL mode, RL = 8Ω 0.15 % Maximum Output Power Bandwidth Gain = 2, THD+N = 2% 20 KHz Open Loop 2 MHz CB = 1µF, BTL mode, RL = 8Ω 74 dB Gain = 1, CB = 0.1µF 28 µV(rms) CB = 1µF 380 ms Output Power (Note 3) Total Harmonic Distortion Plus Noise Unity-Gain Bandwidth Power Supply Rejection Ratio Vn Noise Output Voltage TWU Wake-up time (Note1) mW VDD= 5V, TA= 25°C (unless otherwise noted) Symbol Parameter APA0713 Test Conditions Min. VOS Output Offset Voltage IDD Supply Current IDD(SD) Typ. 20 RL = 8Ω, RF = 10KΩ Supply Current, Shutdown Mode Unit Max. mV BTL mode, RF = 10 KΩ 1.3 2.6 SE mode, RF = 10 KΩ 0.75 1.5 RF = 10 KΩ 0.1 2 µA mA |IH| Shutdown, VI = VDD 1 µA |IL| Shutdown, VI = 0V 1 µA Operating characteristic, VDD = 5V, TA = 25°C, RL = 8Ω PO THD+N Bom B1 PSRR Output Power THD+N = 1%, BTL mode, RL = 8Ω (Note 3) THD+N = 1%, BTL mode, RL = 4Ω Total Harmonic Distortion Plus Noise PO = 630mW, BTL mode, (Note 3) RL = 8Ω 900 mW 1.5 W 0.15 % Maximum Output Power Bandwidth Gain = 2, THD+N = 2% 20 KHz Unity-Gain Bandwidth Open Loop 2 MHz CB = 1µF, BTL mode, RL = 8Ω 74 dB Power Supply Rejection Ratio (Note 3) Vn Noise Output Voltage Gain = 1, CB = 0.1µF 28 µV(rms) Twu Wake-up time CB = 1µF 400 ms Note 3 : Output power is measured at the output terminals of device at f=1KHz. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 3 www.anpec.com.tw APA0713 Typical Operating Characteristics PSRR vs. Frequency Supply Current vs. Supply Voltage 1600 RL=8Ω CB=1µF BTL -20 -40 VDD=3.3V -60 RF=10KΩ 1400 Supply Cuuret (µA) Ripple Rejection Ration (dB) +0 T BTL 1200 1000 800 600 400 -80 VDD=5V 200 0 -100 20 100 1k 10k 20k Frequency (Hz) 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) Shutdown Current vs. 1200 RF=10KΩ Output Power (mW) Shutdown Cuuret (µA) Output Power vs. Supply Voltage Supply Voltage 0.12 0.11 0.1 1000 800 600 RL=8Ω RL=32Ω 400 0.09 THD+N=1% Fin=1KHz BTL 200 0.08 2.5 3 3.5 4 4.5 5 0 2.5 5.5 3 3.5 Supply Voltage (V) Output Power vs. Load Resistance THD+N (%) Ouput Power (mW) VDD=3.3V PO=250mW RL=8Ω BTL 700 600 500 5 5.5 10 THD+N=1% Fin=1KHz BTL 800 4.5 THD+N vs. Frequency 1000 900 4 Supply Voltage (V) VDD=5V 400 AV=-20V/V 1 AV=-10V/V 0.1 300 AV=-2V/V 200 VDD=3.3V 100 0.01 20 0 8 16 24 32 40 48 56 64 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 100 10k 20k 1k Frequency (Hz) Load Resistance (Ω) 4 www.anpec.com.tw APA0713 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Output Power 10 VDD=3.3V Fin=1KHz AV=-2V/V BTL VDD=3.3V RL=8Ω AV=-2V/V BTL PO=50mW 1 THD+N (%) THD+N (%) 10 PO=125mW PO=250mW 0.1 1 RL=8Ω 0.1 0.01 0.01 20 100 1k 0 10k 20k 0.1 0.2 Frequency (Hz) 0.3 THD+N vs. Output Power 0.6 10 Fin=10KHz AV=-20V/V 1 1 Fin=20KHz THD+N (%) THD+N (%) 0.5 THD+N vs. Frequency 10 Fin=1KHz 0.1 Fin=20Hz VDD=3.3V RL=8Ω CB=1µF AV=-2V/V BTL AV=-10V/V 0.1 AV=-2V/V VDD=5V PO=700mW RL=8Ω BTL 0.01 0.01 0.01 20 1 0.1 10k 20k Frequency (Hz) THD+N vs. Frequency THD+N vs. Output Power 10 10 VDD=5V Fin=1KHz AV=-2V/V BTL VDD=5V RL=8Ω AV=-2V/V BTL THD+N (%) PO=50mW 1 PO=700mW PO=350W 0.1 0.01 20 1k 100 Output Power (W) THD+N (%) 0.4 Output Power (W) 100 1k RL=8Ω 0.1 0.01 0.1 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 1 0.3 0.5 0.7 0.9 1.1 1.2 Output Power (W) 5 www.anpec.com.tw APA0713 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Output Power 10 R Fin=20KHz Fin=1KHz 0.1 PO=10mW 0.1 PO=15mW PO=30mW 0.01 0.001 0.1 1 20 100 Output Power (W) Close Loop Gain and Phase vs. Frequency +28 +28 Close Loop Gain (dB) +180 Phase +140 +12 +100 Gain +8 Phase(°) Close Loop Gain (dB) +16 +220 +24 +180 +20 Phase +140 +16 +12 +100 Gain VDD=5V RL=8Ω AV=-4V/V PO=700mW BTL +8 +60 +4 +4 +20 -0 -0 10 100 1k 10k 20k Frequency +24 VDD=3.3V RL=8Ω AV=-4V/V PO=250mW BTL 10k Close Loop Gain and Phase vs. +220 +20 1k Frequency (Hz) Phase(°) 0.01 0.01 Fin=20Hz VDD=5V RL=8Ω CB=1µF AV=2V/V BTL VDD=3.3V RL=32Ω AV=-1V/V BTL 1 Fin=10KHz 1 THD+N (%) THD+N (%) 10 100k 10 100 1k 10k +60 +20 100k Frequency (Hz) Noise Floor vs. Frquency Noise Floor vs. Frquency 100 RL=8Ω, BTL RL=8Ω, BTL Noise Floor (µVrms) Noise Floor (µVrms) 100 10 10 VDD=5V BW=22Hz to 22KHz AV=-1V/V VDD=3.3V BW=22Hz to 22KHz AV=-1V/V 1 1 20 100 1k 10k 20k 20 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 6 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA0713 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power Power Dissipation vs. Output Power 350 800 700 RL=8Ω Power Dissipation (mW) Power Dissipation (mW) 300 250 200 150 100 RL=32Ω VDD=3.3V BTL 50 500 400 300 200 VDD=5V BTL RL=32Ω 100 0 0 0 10 200 400 600 0 200 400 600 800 Output Power (mW) Output Power (mW) THD+N vs. Output Power THD+N vs. Frequency RL=4Ω f=1kHz Gain=6dB BTL V=3.3V RL=4Ω Gain=6dB BTL THD+N (%) 1 2 THD+N (%) RL=8Ω 600 1 V=3.3V 1000 Po=600mW 0.3 Po=300mW V=5V Po=60mW 0.1 0.2 0.06 0.1 0 0.4 0.8 1.2 1.6 2 20 Output Power (W) 100 1k 10k 20k Frequency (Hz) THD+N vs. Frequency V=5V RL=4Ω Gain=6dB BTL THD+N (%) 1 Po=1.3W Po=0.6W 0.3 Po=0.15W 0.1 0.06 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 10k 20k 7 www.anpec.com.tw APA0713 Pin Descriptions Pin I/O Description 1 I Shutdown mode control signal input, place entire IC in shutdown mode when held high. Bypass 2 I Bypass pin IN+ 3 I IN+ is the non-inverting input. IN+ is typically tied to the Bypass terminal. IN- 4 I IN- is the inverting input. IN- is typically used as the audio input terminal. VO+ 5 O VO+ is the positive BTL output. VDD 6 Supply voltage input pin. GND 7 Ground connection for circuitry. VO- 8 Name No Shutdown O VO- is the negative BTL output. Block Diagram RF VDD Audio Input 6 VDD/2 RI 4 CI IN+ 2 Bypass CS _ IN- 3 VDD VO+ 5 VO- 8 + CB _ + From System Control 1 Shutdown 7 Bias Control GND APA0713 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 8 www.anpec.com.tw APA0713 Typical Application Circuits For Single-ended Input Application RF 10kΩ Audio Input RI 10kΩ VDD 6 CS 1µF VDD/2 4 CI 0.47µF IN- 3 IN+ 2 Bypass VDD _ VO+ 5 VO- 8 + CB 1µF _ + From System Control 1 7 Shutdown Bias Control GND For Differential Input Application RF 10kΩ Audio CI Input- 0.47µF CI 0.47µF 6 4 IN- 3 IN+ 2 Bypass VDD CS 1µF VDD/2 RI 10kΩ RI 10kΩ RF 10kΩ Audio Input+ VDD _ VO+ 5 VO- 8 + CB 1µF _ + From System Control 1 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 Shutdown Bias Control 9 7 GND www.anpec.com.tw APA0713 Application Information BTL Operation Input Capacitor, CI In the typical application, an input capacitor, C I, is required to allow the amplifier to bias the input signal to the VO+ proper DC level for optimum operation. In this case, CI and the minimum input impedance RI from a high-pass OP1 filter with the corner frequency are determined in the following equation : RL VOVbias FC(highpass ) = OP2 1 2πRICI (1) The value of CI is important to consider as it directly af- Figure 1: APA0713 power amplifier internal configuration fects the low frequency performance of the circuit. Consider the example where RI is 100KΩ and the specifi- The power amplifier OP1 gain is set by external gain cation calls for a flat bass response down to 40Hz. Equation is reconfigured as followed : setting, while the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 CI = shows that the output of OP1 is connected to the input to OP2, which results in the output signals of with both 1 2πRIFC (2) Consider input resistance variation, the CI is 0.04µF so one would likely choose a value in the range of 0.1µF amplifiers with identical in magnitude, but out of phase 180°. Consequently, the differential gain for each chan- to 1.0µF. nel is 2X (Gain of SE mode). A further consideration for this capacitor is the leakage path from the input source through the input network (RI+RF, By driving the load differentially through outputs VO+ and CI) to the load. VO-, an amplifier configuration commonly referred to as bridged mode is established. The BTL mode operation is This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, es- different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. pecially in high gain applications. For this reason, a lowleakage tantalum or ceramic capacitor is the best choice. The BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most to the load, thus doubling the output swing for a specified supply voltage. applications as the DC level there is held at VDD/2, which is likely higher than the source DC level. Please note that Four times the output power is possible as compared it is important to confirm the capacitor polarity in the application. with a SE amplifier under the same conditions. A BTL configuration, such as the one used in the APA0713, also Effective Bypass Capacitor, Cbypass creates a second advantage over SE amplifiers. Since the differential outputs, VO+ and VO-, are biased at half- As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor rejection. The capacitors located on the bypass and power supply pins should be as close to the device as possible. The which is required in a single supply, SE configuration. effect of a larger half supply bypass capacitor will improve Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 10 www.anpec.com.tw APA0713 Application Information (Cont.) Effective Bypass Capacitor, Cbypass (Cont.) Optimizing Depop Circuitry PSRR due to increased half-supply stability. Typical ap- Circuitry has been included in the APA0713 to mini- plication employs a 5V regulator with 1.0µF and a 0.1µF bypass as supply filtering. This does not eliminate the mize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs when- need for bypassing the supply nodes of the APA0713. The selection of bypass capacitors, especially Cbypass, thus ever a voltage step is applied to the speaker. In order to eliminate click-and-pop, all capacitors must be fully dis- depends upon desired PSRR requirements, click- andpop performance. charged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click-and- To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and pop circuitry. The value of CI will also affect turn-on pops (refer to Effective Bypass Capacitance). The bypass volt- the relationship shown in equation (4) should be maintained. age rise up should be slower than input bias voltage. 1 Cbypass × 80KΩ << 1 (RI + RF) × CI Although the bypass pin current source cannot be modified, the size of Cbypass can be changed to alter the (3) device turn-on time and the amount of click-and-pop. By increasing the value of Cbypass, turn-on pop can be reduced. The bypass capacitor is fed from a 80KΩ resistor inside the amplifier. Bypass capacitor, Cbypass, values of 0.1µF However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a to 2.2µF ceramic or tantalum low-ESR capacitors are recommended for the best THD+N and noise linear relationship between the size of Cbypass and the turnon time. performance. In the most cases, choosing a small value of CI in the range of 0.33µF to 1µF, Cbypass being equal to 1µF should The bypass capacitance also effects to the start up time. It is determined in the following equation : Tstartup = 5 × (Cbypass × 80KΩ) produce a virtually clickless and popless turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Hence, it is ad- (4) Power Supply Decoupling, CS vantageous to use low-gain configurations. The APA0713 is a high-performance CMOS audio ampliShutdown Function fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) In order to reduce power consumption while not in using, is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length be- the APA0713 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature tween the amplifier and the speaker. The optimum decoupling is achieved by using two different types of turns the amplifier off when a logic low on the Shutdown pin for APA0713. capacitors that target on different types of noise on the power supply leads. For higher frequency transients, The trigger point between a logic high and logic low level is typically 0.4VDD. It’s better to switch between ground and the supply voltage VDD to provide maximum device spikes, or digital hash on the line, a good low equivalentseries-resistance (ESR) ceramic capacitor, typically 0.1µF, performance. is placed as close as possible to the device’s VDD lead, which is for the best performance. For filtering lower-fre- By switching the Shutdown pin to high level, the amplifier quency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power enters a low-current state, IDD for APA0713. APA0713 is in shutdown mode. In normal operation, APA0713’s amplifier is recommended. Shutdown pin should be pulled to low level to keep the IC Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 11 www.anpec.com.tw APA0713 Application Information (Cont.) resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissi- Shutdown Function (Cont.) out of the shutdown mode. The Shutdown pin should be tied to a definite voltage to avoid unwanted state changes. pation at full output power is less than in the half power range. Calculating the efficiency for a specific system is BTL Amplifier Efficiency the key to proper power supply design. For a mono 900mW audio system with 8Ω loads and a 5V supply, the An easy-to-use equation to calculate efficiency starts out maximum draw on the power supply is almost 1.5W. as being equal to the ratio of power from the power supply to the power delivered to the load. The following equa- A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note tions are the basis for calculating amplifier efficiency. Efficiency = PO PSUP that in equation8, VDD is in the denominator. (5) This indicates that as VDD goes down, efficiency goes up. Where PO = In other words, the efficiency analysis is used to choose the correct supply voltage and speaker impedance for the Vorms × Vorms ( VP × VP ) = 2RL RL Vorms = application. VP (6) 2 PSUP = VDD × LDD, AVG = VDD × 2 VP πRL Power Dissipation (7) Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation9 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving Efficiency of a BTL configuration : VP × VP ( ) PO πVP 2RL = = PSUP ( VDD × 2 VP ) 4VDD πRL a specified load. (8) SE mod e : PD, MAX = Po (W) Efficiency (%) VP(V) PD (W) 0.125 33.6 1.41 0.26 VDD2 2π2RL (9) In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. 0.25 47.6 2.00 0.29 BTL mod e : PD, MAX = 0.375 58.3 2.45* 0.28 4 VDD2 2π2RL (10) Since the APA0713 is a mono channel power amplifier, *High peak voltages cause the THD+N to increase. the maximum internal power dissipation is equal to the both of equations depending on the mode of operation. Table 1. Efficiency vs. Output Power in 3.3V/8Ω BTL Systems. Table 1 employs equation 8 to calculate efficiencies for The power dissipation from equation10, assuming a 5Vpower supply and an 8Ω load, must not be greater than three different output power levels when load is 8Ω. the power dissipation that results from the equation11: The efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 PD, MAX = 12 TJ, MAX − TA θJA (11) www.anpec.com.tw APA0713 Application Information (Cont.) Power Dissipation (Cont.) For SOP-8 package, the thermal resistance (θJA) is equal to 200οC/W, respectively. Since the maximum junction temperature (TJ,MAX ) of APA0713 is 170οC and the ambient temperature (TA ) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation 11. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased, or the ambient temperature should be reduced. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 13 www.anpec.com.tw APA0713 Package Information SOP-8 D E E1 SEE VIEW A h X 45 ° 0.25 A2 c A b e NX GAUGE PLANE SEATING PLANE aaa C L VIEW A S Y M B O L SOP-8 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.75 0.069 0.010 0.004 0.25 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° aaa 0.10 8° 0.004 Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 14 www.anpec.com.tw APA0713 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 SOP-8 4.0±0.10 8.0±0.10 W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type Unit Quantity SOP-8 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 15 www.anpec.com.tw APA0713 Taping Direction Information SOP-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 16 www.anpec.com.tw APA0713 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 17 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA0713 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2012 18 www.anpec.com.tw