a Dual-Loop 50 Mbps–2.7 Gbps Laser Diode Driver ADN2841 FEATURES 50 Mbps to 2.7 Gbps Operation Typical Rise/Fall Time 80 ps Bias Current Range 2 to 100 mA Modulation Current Range 5 to 80 mA Monitor Photodiode Current 50 A to 1200 A Closed-Loop Control of Power and Extinction Ratio Laser Fail and Laser Degrade Alarms Automatic Laser Shutdown, ALS Dual MPD Functionality for DWDM Optional Clocked Data Full Current Parameter Monitoring 5 V Operation 48-Lead LFCSP Package 32-Lead LFCSP Package (Reduced Functionality) GENERAL DESCRIPTION The ADN2841 uses a unique control algorithm to control both average power and extinction ratio of the laser diode (LD) after initial factory set up. External component count and PCB area are low as both power and extinction ratio control are fully integrated. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail). The ADN2841 has circuitry for a second monitor photodiode which enables DWDM wavelength control. APPLICATIONS DWDM Dual MPD Wavelength Fixing SONET OC-1/3/12/48 SDH STM-1/4/16 Fiber Channel Gigabit Ethernet GND IMODN CLKSEL VCC VCC DEGRADE FAIL ALS IMPDMON2 IMPDMON IBMON IMMON FUNCTIONAL BLOCK DIAGRAM VCC LD VCC IMODP MPD IMPD DATAP DATAN IMOD CLKP IMPD2 CLKN CONTROL GND PSET IBIAS IBIAS ASET GND ERSET GND ADN2841 GND ERCAP GND PAVCAP IDTONE LBWSET GND REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 ADN2841–SPECIFICATIONS Parameter LASER BIAS (BIAS) Output Current IBIAS Compliance Voltage IBIAS during ALS ALS Response Time CCBIAS Compliance Voltage MODULATION CURRENT (IMODP, IMODN) Output Current IMOD Compliance Voltage IMOD during ALS Rise Time Fall Time Jitter Pulsewidth Distortion MONITOR PD (MPD, MPD2) Current Input Voltage (VCC = 5 V 10%. All specifications TMIN to TMAX unless otherwise noted1. Typical values as specified at 25C.) Min Typ 2 1.2 Max Unit 100 mA V mA µs V VCC 0.1 10 1.2 5 1.8 80 80 80 VCC 0.1 120 120 20 mA V mA ps ps ps p-p ps 1200 1.6 µA V Average Current pF µA V Average Current 18 50 POWER SET INPUT (PSET) Capacitance Input Current Voltage 50 1.15 1.23 80 1200 1.35 EXTINCTION RATIO SET INPUT (ERSET) Allowable Resistance Range Voltage 1.2 1.15 1.23 25 1.35 kΩ V 25 1.35 kΩ V % ALARM SET (ASET) Allowable Resistance Range Voltage Hysteresis 1.2 1.15 CONTROL LOOP Time Constant DATA INPUTS (DATAP, DATAN, CLKP, CLKN) AC-Coupled2 V p-p (Single-Ended peak-to-peak) Input Impedance tSETUP3 tHOLD3 1.23 5 0.22 2.25 100 150 0 LOGIC INPUTS (ALS, LBWSET, CLKSEL) VIH VIL 2.4 ALARM OUTPUTS (Internal 30 kΩ Pull-up) VOH VOL 2.4 IOUT I IN fIN4 RATIO sec sec 500 50 95 –70 IDTONE Compliance Voltage Conditions/Comments (LBWSET = GND) (LBWSET = VCC) mV Ω ps ps 0.8 V V 0.8 V V VCC – 1.5 V 1 MHz User to Supply Current Sink in the range 50 µA to 4 mA 2 0.01 –2– REV. 0 ADN2841 Parameter Min IBMON, IMMON, IMPDMON, IMPDMON2 IBMON, IMMON Division Ratio IMPDMON, IMPDMON2 IMPDMON to IMPDMON2 Matching Compliance Voltage 0 SUPPLY ICC5 VCC6 4.5 Typ Max Unit 1 VCC – 1.2 A/A A/A % V 5.5 A V 100 1 0.05 5.0 Conditions/Comments IMPD = 1200 µA IBIAS = IMOD = 0 NOTES 1 Temperature Range: –40°C to +85°C 2 When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin. 3 Guaranteed by design and characterization. Not production tested. 4 IDTONE may cause eye distortion. 5 ICC for power calculation is the typical I CC given. 6 All VCCS should be shorted together. Specifications subject to change without notice. SETUP HOLD tS tH DATAP/N CLKP Figure 1. Setup and Hold Time ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . 150°C 48-Lead LFCSP Package Power Dissipation . . . . . . . . . . . . . . .(TJ MAX – TA)/θJA mW θJA Thermal Impedance2 . . . . . . . . . . . . . . . . . . . . 25°C/W Lead Temperature (Soldering for 10 sec) . . . . . . . . 300°C 32-Lead LFCSP Package Power Dissipation . . . . . . . . . . . . . . . (TJ MAX – TA)/θJA mW θJA Thermal Impedance2 . . . . . . . . . . . . . . . . . . . . 32°C/W Lead Temperature (Soldering for 10 sec) . . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents of up to 100 mA will not cause SCR latch-up. 2 θJA is defined when the part is soldered onto a four-layer board. ORDERING GUIDE Model Temperature Range Package Description ADN2841ACP-32 ADN2841ACP-48 ADN2841ACP-32-RL ADN2841ACP-32-RL7 ADN2841ACP-48-RL –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 32-Lead LFCSP 48-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 48-Lead LFCSP CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2841 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE ADN2841 PIN CONFIGURATIONS 48-Lead LFCSP PIN 1 INDICATOR PIN 1 INDICATOR ADN2841 TOP VIEW (Not to Scale) 24 IBMON 23 IMMON 22 GND3 21 VCC3 20 ALS 19 FAIL 18 DEGRADE 17 CLKSEL ERCAP 9 PAVCAP 10 VCC1 11 DATAN 12 DATAP 13 GND1 14 CLKP 15 CLKN 16 ADN2841 TOP VIEW (Not to Scale) LBWSET 1 ASET 2 ERSET 3 PSET 4 IMPD 5 IMPDMON 6 GND4 7 VCC4 8 24 GND 23 GND 22 CLKN 21 CLKP 20 GND1 19 DATAP 18 DATAN 17 GND1 16 VCC1 15 GND 14 PAVCAP 13 ERCAP GND 1 LBWSET 2 ASET 3 ERSET 4 PSET 5 GND 6 IMPD 7 IMPDMON 8 IMPDMON2 9 IMPD2 10 GND4 11 VCC4 12 GND2 37 VCC2 38 IMODN 39 IMODN 40 GND2 41 IMODP 42 IMODP 43 GND2 44 GND2 45 IBIAS 46 IBIAS 47 CCBIAS 48 32 CCBIAS 31 IBIAS 30 GND2 29 GND2 28 IMODP 27 GND2 26 IMODN 25 VCC2 36 GND2 35 IDTONE 34 GND2 33 IBMON 32 IMMON 31 GND3 30 VCC3 29 ALS 28 FAIL 27 DEGRADE 26 CLKSEL 25 GND 32-Lead LFCSP PIN FUNCTION DESCRIPTIONS Pin No. 48-Lead 32-Lead Mnemonic Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GND LBWSET ASET ERSET PSET GND IMPD IMPDMON IMPDMON2 IMPD2 GND4 VCC4 ERCAP PAVCAP GND VCC1 GND1 DATAN DATAP GND1 CLKP CLKN GND GND GND CLKSEL DEGRADE FAIL ALS VCC3 GND3 IMMON IBMON GND2 IDTONE GND2 Supply Ground Select Low Loop Bandwidth (Active = VCC) Alarm Current Threshold Setting Pin Extinction Ratio Set Pin Average Optical Power Set Pin Ground Monitor Photodiode Input Mirrored Current from Monitor Photodiode Mirrored Current from Monitor Photodiode 2 (for use with two MPDs) Monitor Photodiode Input 2– (for use with two MPDs) Supply Ground Supply Voltage Extinction Ratio Loop Capacitor Average Power Loop Capacitor Ground Supply Voltage Supply Ground Data, Negative Differential Terminal Data, Positive Differential Terminal Supply Ground Data Clock Positive Differential Terminal, used if CLKSEL = VCC Data Clock Negative Differential Terminal, used if CLKSEL = VCC Ground Ground Ground Clock Select (Active = VCC), used if data is clocked into chip DEGRADE Alarm Output FAIL Alarm Output Automatic Laser Shutdown Supply Voltage Supply Ground Modulation Current Mirror Output Bias Current Mirror Output Supply Ground IDTONE (Requires external current sink to ground) Supply Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 –4– REV. 0 ADN2841 PIN FUNCTION DESCRIPTIONS (continued) Pin No. 48-Lead 32-Lead Mnemonic Function 37 38 39 40 41 42 43 44 45 46 47 48 GND2 VCC2 IMODN IMODN GND2 IMODP IMODP GND2 GND2 IBIAS IBIAS CCBIAS Supply Ground Supply Voltage Modulation Current Negative Output, connect to 25 Ω Modulation Current Negative Output, connect to 25 Ω Supply Ground Modulation Current Positive Output, connect to laser diode Modulation Current Positive Output, connect to laser diode Supply Ground Supply Ground Laser Diode Bias Current Laser Diode Bias Current Extra Laser Diode Bias when AC-Coupled REV. 0 25 26 27 28 29 30 31 32 –5– ADN2841 GENERAL LOOP BANDWIDTH SELECTION Laser diodes have current-in to light-out transfer functions as shown in Figure 2. Two key characteristics of this transfer function are the threshold current, ITH, and slope in the linear region beyond the threshold current, referred to as slope efficiency, LI. For anyrate operation the user should hardwire the LBWSET pin high and use 1 µF capacitors to set the actual loop bandwidth. These capacitors are placed between the PAVCAP and ERCAP pins and ground. It is important that these capacitors be low-leakage multilayer ceramics with an insulation resistance greater than 100 GΩ or a time constant of 1000 sec, whichever is less. The ADN2841 may be optimized for 2.7 Gbps operation by keeping the LBWSET pin low. This results in a much shorter loop time constant (a 10⫻ reduction). The value of PAVCAP and ERCAP capacitors required for 2.5 Gbps operation is 22 nF. OPTICAL POWER ER = P1 P0 P1 PAV = P1 + P0 2 P PAV I LI = P I ALARMS The ADN2841 alarms are designed to allow interface compliance to ITU-T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and section 10.3.1.1.3 (transmitter degrade). The ADN2841 has two active high alarms, DEGRADE and FAIL. A resistor between ground and the ASET pin is used to set the current at which these alarms are raised. The current through the ASET resistor is a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE alarm will be raised at 90% of this level. P0 ITH CURRENT Figure 2. Laser Transfer Function CONTROL A monitor photodiode (MPD) is required to control the LD. The MPD current is fed into the ADN2841 to control the optical power and extinction ratio, continuously adjusting the bias current and modulation current in response to the laser’s changing threshold current and light-to-current (LI) slope (slope efficiency). Example: IFAIL = 50 mA ∴ IDEGRADE = 45 mA The ADN2841 uses automatic power control (APC) to maintain a constant power over time and temperature. I ASET = I BIASTRIP 50 mA = = 500 µA 100 100 The ADN2841 uses closed-loop extinction ratio control to allow optimum setting of extinction ratio for every device. Hence SONET/SDH interface standards can be met over device variation, temperature, and time. Closed-loop modulation control eliminates the need to either overmodulate the LD or include external components for temperature compensation. This reduces research and development time and second-sourcing issues caused by characterizing LDs. RASET = 1.23V 1.23V = = 2.46 kΩ I ASET 500 µA NOTE: The smallest value for RASET is 1.2 kΩ, as this corresponds to the IBIAS maximum of 100 mA. The laser degrade alarm, DEGRADE, gives a warning of imminent laser failure if the laser diode degrades further or environmental conditions continue to stress the LD, e.g., increasing temperature. Average Power and Extinction Ratio are set using the PSET and ERSET pins, respectively. Potentiometers are connected between these pins and ground. The potentiometer, RPSET, is used to change the average power. The potentiometer, RERSET , is used to adjust the extinction ratio. Both PSET and ERSET are kept 1.23 V above GND. The laser fail alarm, FAIL, is activated when the transmitter can no longer be guaranteed to be SONET/SDH-compliant. This occurs when one of the following conditions arises: • The ASET threshold is reached. • The ALS pin is set high. This shuts off the modulation and bias currents to the LD, resulting in the MPD current dropping to zero. This gives closed-loop feedback to the system in which ALS has been enabled. RPSET and RERSET can be calculated using the following formulas: 1.23 V I AV where IAV is average MPD current. RPSET = DEGRADE will only be raised when the bias current exceeds 90% of ASET current. 1.23V I MPD _ CW ER − 1 × × 0.2 × PAV PCW ER + 1 where PCW is the dc optical power specified on the laser data sheet, IMPD_CW is MPD current at that specified PCW, and PAV is the required average power. MONITOR CURRENTS RERSET = IBMON, IMMON, and IMPDMON and IMPDMON2 are current controlled current sources from VCC. They mirror the bias, modulation, and MPD current for increased monitoring functionality. An external resistor to GND gives a voltage proportional to the current monitored. Note that IERSET and IPSET will change from device to device. However, the control loops will determine actual values. It is not required to know exact values for LI or MPD optical coupling. DUAL MPD DWDM FUNCTION (48-PIN LFCSP ONLY) The ADN2841 has circuitry for an optional second monitor photodiode, MPD2. –6– REV. 0 ADN2841 REF CLOCK 20MHz– 180MHz 10kHz–1MHz CLKIN IOUT 1.25mA–20mA AD9850/AD9851 AD8602 50 DDS RSET IDTONE LP FILTER (DC-COUPLED) 0.125mA–2mA BC550 1/2 IOUT ADN2841 50 500 AD8602 37.5A–600A 50A–800A IMMON 1/2 BC550 1000 CONTROLLER 1300 Figure 3. Circuitry to Allow Fiber Identification The second photodiode current is mirrored to IMPDMON2 for wavelength control purposes and is summed internally for the power control loop. For single MPD circuits the MPD2 pin is tied to GND. ADN2841 DATAP TO FLIP-FLOPS This enables the system designer to use the two currents to control the wavelength of the laser diode using various optical filtering techniques inside the laser module. DATAN 50 50 VREG If the monitor current functions IMPDMON and IMPDMON2 are not required, the IMPD and IMPD2 pins can be grounded and the monitor photodiode output can be connected directly to PSET. R R = 2.5k, DATA R = 3k, CLK 400A TYP IDTONE (48-PIN LFCSP ONLY) The IDTONE pin is supplied for fiber identification/supervisory channels or control purposes in WDM. This pin modulates the optical one level over a possible range of 2% of minimum IMOD to 10% of maximum IMOD. The level of modulation is set by connecting an external current sink between the IDTONE pin and ground. There is a gain of two from this pin to the IMOD current. Figure 4. AC Coupling of Data Inputs CCBIAS Figure 3 shows how an AD9850/AD9851 DDS may be used with the ADN2841 to allow fiber identification. CCBIAS should be connected to the BIAS pin if the laser diode is connected to the ADN2841 using a capacitor. CCBIAS is a current sink to GND. Note that using IDTONE during transmission may cause optical eye degradation. AUTOMATIC LASER SHUTDOWN DATA, CLOCK INPUTS The ADN2841 ALS allows compliance to ITU-T-G958 (11/94), section 9.7. Data and Clock inputs are ac-coupled (10 nF recommended) and terminated via a 100 Ω internal resistor between DATAP and DATAN, and also between CLKP and CLKN pins. There is a high-impedance circuit to set the common-mode voltage that is designed to change over temperature. It is recommended that ac coupling be used to eliminate the need for matching between common-mode voltages. REV. 0 When ALS is logic high, both bias and modulation currents are turned off. Correct operation of ALS can be confirmed by the fail alarm being raised when ALS is asserted. Note this is the only time that DEGRADE will be low while FAIL is high. –7– ADN2841 VCC ALARM INTERFACES A 30 kΩ internal pull-up resistor is employed to pull the digital high value of the alarm outputs to VCC. However, the ADN2841 has a feature that allows the user to externally wire resistors in parallel with the 30 kΩ pull-up resistors thus enabling the user to interface to non-VCC levels. Non-VCC alarm output levels must be below the VCC used for the ADN2841. VCC ADN2841 ADN2850 SDI RX SDO CLK CLK DAC1 PSET DAC2 ERSET DATAP IDTONE CS CS DATAN The ADN2841 die temperature must be kept below 125°C. The θJA for the 48-lead LFCSP is 25°C/W and the 32-lead LFCSP is 32°C/W when soldered in a four-layered board. Both LFCSP packages have an exposed paddle and as such need to be soldered to the PCB to achieve this thermal performance. IMODP IBIAS TX POWER CONSUMPTION DATAP DATAN IDTONE TDIE = T AMBIENT + θ JA × P I CC = I CCMIN + 0.3 I MOD ( VCC IMPD ) ( P = VCC × I CC + I BIAS × V BIAS _ PIN + I MOD × V MOD _ PIN Figure 5. Application Using Optical Supervisor ADN2850 as a Dual 10-Bit Digital Potentiometer Using Thin-Film Resistor Technology to Give Very Low Temperature Coefficients ) Hence the maximum combination of IBIAS + IMOD must be calculated. FAIL DEGRADE VCC ALS FAIL DEGRADE CLKSEL VCC2 GND3 VCC3 GND2 GND2 IBMON IMMON 37 IDTONE IMODN IMODN GND2 IMODP IMODP GND2 CCBIAS 48 VCC GND2 IBIAS IBIAS GND VCC ADN2841 IMPD IMPDMON IMPDMON2 IMPD2 VCC GND FU-445SDF-WM1 LBWSET ASET ERSET PSET 25 36 GND 24 GND GND CLKN CLKP GND1 CLKN DATAP DATAP DATAN GND1 DATAN VCC1 GND PAVCAP ERCAP GND4 1 25 VCC4 VCC GND GND2 VCC CLKP 12 13 1.5k VCC NOTE VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED. 100nF 100nF 100nF 100nF 10F GND Figure 6. 2.7 Gbps Test Circuit, DC-Coupled, Data Not Clocked, Fast Loop Time Constant Selected –8– REV. 0 ADN2841 FAIL VCC DEGRADE GND2 VCC2 VCC IMODN ALS FAIL DEGRADE CLKSEL 37 GND2 IBMON IMMON GND3 VCC3 IDTONE IMODN GND2 VCC IMODP IMODP GND2 VCC VCC ADN2841 IMPD IMPDMON IMPDMON2 IMPD2 CCBIAS 48 GND LBWSET ASET ERSET PSET GND2 IBIAS IBIAS 25 GND GND 24 GND CLKN CLKN CLKP CLKP GND1 GND 25 36 VCC DATAP DATAN VCC1 GND PAVCAP ERCAP GND4 1 DATAP DATAN GND1 VCC4 VCC GND GND2 VCC 12 13 1.5k VCC NOTE VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED. 100nF 100nF 100nF 100nF 10F GND Figure 7. Any Rate Test Circuit, Capacitively Coupled, Data Clocked, Slow Loop Time Constant Selected REV. 0 –9– ADN2841 VCC VCC VCC VCC 50 50 EA MODULATOR VCC NOTES 1. V CCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED. 2. THE OP293 HAS BEEN SELECTED BECAUSE OF ITS GAIN BANDWIDTH PRODUCT AND SHOULD BE USED IN THIS APPLICATION. VCC2 GND2 IMODN GND2 IMODN IMODP GND2 IMODP BIAS GND2 GND VCC BIAS 48 1 CCBIAS VCC ERSET IBMON PSET IMMON GND GND3 ADN2841 IMPD ALS FAIL IMPDMON2 DEGRADE GND GND CLKN CLKP GND1 DATAP DATAN GND1 VCC1 CLKSEL GND PAVCAP IMPD2 ERCAP VCC VCC3 IMPDMON VCC4 VCC GND2 ASET GND4 GND2 IDTONE LBWSET VCC 36 12 24 VCC VCC VCC VCC 8 2 1 3 1/2 OP293 1/2 OP293 7 DAC 1k 6 5 DAC 1k –VCC Figure 8. EA Modulator Application Figure 9. Unfiltered 2.5 Gbps Optical Eye. Average Power = –3 dBm, Extinction Ratio = 9.5 dB. Eye obtained using a Mitsubishi FU-445-SDF. Figure 10. Filtered 2.5 Gbps Optical Eye. Average Power = –3 dBm, Extinction Ratio = 9 dB. Eye obtained using a Mitsubishi FU-445-SDF. –10– REV. 0 ADN2841 OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches). 48-Lead (77) LFCSP (Exposed Paddle) (CP-48) 0.60 (0.024) 0.42 (0.017) 0.24 (0.009) 7.00 (0.276) BSC SQ 0.60 (0.024) 0.42 (0.017) 0.24 (0.009) PIN 1 INDICATOR 48 37 36 1 6.75 (0.266) BSC SQ TOP VIEW 12 MAX 0.50 (0.0197) BSC 0.20 (0.0079) REF 5.25 (0.207) 5.10 (0.201) SQ 4.95 (0.195) BOTTOM VIEW 0.50 (0.020) 0.40 (0.016) 0.30 (0.012) 0.70 (0.028) MAX 0.65 (0.026) NOM 0.90 (0.035) MAX 0.85 (0.033) NOM 0.30 (0.012) 0.23 (0.009) 0.18 (0.007) 12 25 24 13 5.50 (0.217) REF 0.05 (0.0020) 0.01 (0.0004) 0.00 (0.0000) NOTE EXPOSED PADDLE SHOULD BE SOLDERED TO THE MOST NEGATIVE SUPPLY OF THE ADN2841 32-Lead (55) LFCSP (Exposed Paddle) (CP-32) 0.60 (0.024) 0.42 (0.017) 0.24 (0.009) 5.00 (0.197) BSC SQ PIN 1 INDICATOR TOP VIEW 12 MAX 4.75 (0.187) BSC SQ 0.70 (0.028) MAX 0.65 (0.026) NOM 0.90 (0.035) MAX 0.85 (0.033) NOM 0.50 (0.0197) BSC 0.30 (0.0118) 0.23 (0.0091) 0.18 (0.0071) 0.20 (0.0079) REF 0.50 (0.020) 0.40 (0.016) 0.30 (0.012) 0.05 (0.0020) 0.01 (0.0004) 0.00 (0.0000) –11– 32 1 3.25 (0.128) 3.10 (0.122) 2.95 (0.116) REF SQ BOTTOM VIEW NOTES 1. DIMENSIONS MEET JEDEC MO-220-VHHD-2 2. EXPOSED PADDLE SHOULD BE SOLDERED TO THE MOST NEGATIVE SUPPLY OF THE ADN2841 REV. 0 25 24 17 16 9 8 5.60 (0.220 ) REF –12– PRINTED IN U.S.A. C02659–0–10/01(0)