Allegro A6276SA 16-bit serial input, constant-current latched led driver Datasheet

A6276
16-Bit Serial Input, Constant-Current
Latched LED Driver
Features and Benefits
Description
▪ Up to 90 mA constant-current outputs
▪ Undervoltage lockout
▪ Low-power CMOS logic and latches
▪ High data input rate
▪ Functional replacement for TB62706BN/BF
The A6276 is specifically designed for LED-display
applications. Each BiCMOS device includes a 16-bit CMOS
shift register, accompanying data latches, and 16 NPN constantcurrent sink drivers. Except for package style and allowable
package power dissipation, the device options are identical.
Packages
24-pin DIP
(A package)
24-pin TSSOP
with exposed thermal pad
(LP package)
24-pin SOICW
(LW package)
Not to scale
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 5 V logic supply,
typical serial data-input rates are up to 20 MHz. The LED drive
current is determined by the user selection of a single resistor.
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. For inter-digit
blanking, all output drivers can be disabled with an ENABLE
input high. Similar 8-bit devices are available as the A6275.
Three package styles are provided: through-hole DIP (suffix A),
surface-mount SOIC (suffix LW), and TSSOP with exposed
thermal pad (suffix LP). In normal applications, the copper
leadframe and low logic-power dissipation of the DIP allow it
to sink maximum rated current through all outputs continuously
over the operating temperature range (90 mA, 0.75 V drop,
85°C). All packages are lead (Pb) free, with 100% matte tin
leadframe plating.
Functional Block Diagram
26185.201H
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Selection Guide
Part Number
Package
Ambient
Temperature (°C)
Packing
A6276EA-T
24-pin DIP
15 per tube
–40 to 85
A6276ELPTR-T*
24-pin TSSOP
4000 per reel
–40 to 85
A6276ELWTR-T
24-pin SOICW
1000 per reel
–40 to 85
A6276SLWTR-T*
24-pin SOICW
1000 per reel
–20 to 85
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is
obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant
should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer
available. Status date change November 1, 2008. Deadline for receipt of LAST TIME BUY orders is April 25, 2009.
Absolute Maximum Ratings*
Characteristic
Symbol
Notes
Rating
Units
Supply Voltage
VDD
7.0
V
Output Voltage
VO
–0.5 to 17
V
VROUT
–0.4 to VDD + 0.4
V
Output Current
IO
90
mA
Ground Current
IGND
Input Voltage
1475
mA
Range S
–20 to 85
ºC
Range E
Operating Ambient Temperature
TA
–40 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Value Units
Package A, 1-layer PCB based on JEDEC standard
Package Thermal Resistance
RθJA
Package LP, 2-layer PCB with 3.8
in.2
copper area each side
Package LW, 1-layer PCB based on JEDEC standard
50
ºC/W
32
ºC/W
85
ºC/W
*Additional thermal information available on the Allegro website
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
4.0
3.5
24-PIN TSSOP*, R θJA = 32°C/W
3.0
24-PIN DIP, RθJA = 50°C/W
2.5
24-LEAD SOIC, RθJA = 85°C/W
2.0
1.5
1.0
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE IN ° C
150
*Mounted on single-layer, two-sided PCB, with 3.8 in2 copper each side;
additional information on Allegro Web site
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Pin-out Diagram
(A, LP, and LW packages)
V DD
GROUND
1
SERIAL
DATA IN
2
CLOCK
3
CK
LATCH
ENABLE
4
L
IO
REGULATOR
OE
24
LOGIC
SUPPLY
23
R EXT
22
SERIAL
DATA OUT
21
OUTPUT
ENABLE
20
OUT 15
REGISTER
OUT 0
5
OUT 1
6
19
OUT 14
OUT 2
7
18
OUT 13
OUT 3
8
17
OUT 12
OUT 4
9
16
OUT 11
OUT 5
10
15
OUT 10
OUT 6
11
14
OUT 9
OUT 7
12
13
OUT 8
LATCHES
Terminal Description
Terminal No.
1
Terminal Name
GND
Function
Reference terminal for control logic.
2
SERIAL DATA IN
Serial-data input to the shift-register.
3
CLOCK
4
LATCH ENABLE
5-20
OUT0-15
21
OUTPUT ENABLE
When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
22
SERIAL DATA OUT
CMOS serial-data output to the following shift-register.
23
REXT
24
SUPPLY
Clock input terminal for data shift on rising edge.
Data strobe input terminal; serial data is latched with high-level input.
The 16 current-sinking output terminals.
An external resistor at this terminal establishes the output current for all
sink drivers.
(VDD) The logic supply voltage (typically 5 V).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright © 2000, 2003 Allegro MicroSystems, Inc.
3
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
V DD
V DD
IN
IN
Dwg. EP-010-12
Dwg. EP-010-11
OUTPUT ENABLE (active low)
LATCH ENABLE
V DD
V DD
OUT
IN
Dwg. EP-063-6
Dwg. EP-010-13
CLOCK and SERIAL DATA IN
SERIAL DATA OUT
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial Latch
Data Enable
Output Input
Latch Contents
I1
I2
I3
...
IN-1
IN
Output
Enable
Input
Output Contents
I1 I2 I3 ... IN-1 IN
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
H H H ... H
X
X
...
P1 P2 P3 ...
X
PN-1 PN
X
X
...
X
H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic
Symbol
Supply Voltage Range
VDD
Under-Voltage Lockout
VDD(UV)
Output Current
(any single output)
Output Current Matching
IO
∆IO
(difference between any
two outputs at same VCE)
Test Conditions
Min.
Typ.
Max.
Unit
Operating
4.5
5.0
5.5
V
VDD = 0 5 V
3.4
–
4.0
V
VCE = 0.7 V, REXT = 250 
64.2
75.5
86.8
mA
VCE = 0.7 V, REXT = 470 
34.1
40.0
45.9
mA
REXT = 250 
–
±1.5
±6.0
%
REXT = 470 
–
±1.5
±6.0
%
–
1.0
5.0
μA
0.4 V VCE(A) = VCE(B) 0.7 V:
Output Leakage Current
ICEX
Logic Input Voltage
VIH
0.7VDD
–
VDD
V
VIL
GND
–
0.3VDD
V
SERIAL DATA OUT
Voltage
Input Resistance
Supply Current
VOH = 15 V
VOL
IOL = 500 μA
–
–
0.4
V
VOH
IOH = -500 μA
4.6
–
–
V
ENABLE Input, Pull Up
150
300
600
k
LATCH Input, Pull Down
100
200
400
k
REXT = open, VOE = 5 V
–
0.8
1.4
mA
REXT = 470 Ω, VOE = 5 V
3.5
6.0
8.0
mA
REXT = 250 Ω, VOE = 5 V
6.5
11
15
mA
REXT = 470 , VOE = 0 V
7.0
13
20
mA
REXT = 250 , VOE = 0 V
10
22
32
mA
RI
IDD(OFF)
IDD(ON)
Typical Data is at VDD = 5 V and is for design information only.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic
Propagation Delay Time
Propagation Delay Time
Symbol
tpHL
tpLH
Test Conditions
Min.
Typ.
Max.
Unit
CLOCK-OUTn
–
350
1000
ns
LATCH-OUTn
–
350
1000
ns
ENABLE-OUTn
–
350
1000
ns
CLOCK-SERIAL DATA OUT
–
40
–
ns
CLOCK-OUTn
–
300
1000
ns
LATCH-OUTn
–
300
1000
ns
ENABLE-OUTn
–
300
1000
ns
CLOCK-SERIAL DATA OUT
–
40
–
ns
Output Fall Time
tf
90% to 10% voltage
150
350
1000
ns
Output Rise Time
tr
10% to 90% voltage
150
300
600
ns
Min.
Typ.
Max.
Unit
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Supply Voltage
VDD
4.5
5.0
5.5
V
Output Voltage
VO
–
1.0
4.0
V
Output Current
IO
Continuous, any one output
–
–
90
mA
IOH
SERIAL DATA OUT
–
–
-1.0
mA
IOL
SERIAL DATA OUT
–
–
1.0
mA
VIH
0.7VDD
–
VDD + 0.3
V
VIL
-0.3
–
0.3VDD
V
–
–
10
MHz
Logic Input Voltage
Clock Frequency
fCK
Conditions
Cascade operation
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
tp
SERIAL
DATA OUT
DATA
50%
D
E
LATCH
ENABLE
OUTPUT
ENABLE
50%
LOW = ALL OUTPUTS ENABLED
tp
HIGH = OUTPUT OFF
DATA
50%
OUT N
LOW = OUTPUT ON
Dwg. WP-029-1
HIGH = ALL OUTPUTS DISABLED (BLANKED)
OUTPUT
ENABLE
50%
t pLH
F
tf
90%
OUT N
t pHL
DATA
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ............................. 50 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................. 20 ns
C. Clock Pulse Width, tw(CK) .................................. 50 ns
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................... 100 ns
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................... 4.5 μs
tr
50%
10%
Dwg. WP-030-1A
Serial data present at the input is transferred to the shift
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-toparallel conversion). The latches continue to accept new data as
NOTE: Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable.
Max. Clock Transition Time, tr or tf ....................... 10 μs
long as the LATCH ENABLE is held high. Applications where
the latches are bypassed (LATCH ENABLE tied high) will
require that the OUTPUT ENABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, the output sink
drivers are disabled (OFF). The information stored in the latches
is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state
of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A6276EA
A6276ELW
100
100
80
VCE = 2 V
VCE = 3 V
60
VCE = 4 V
40
TA = +25oC
VDD = 5 V
RQJA = 50oC/W
20
VCE = 0.7 V
ALLOWABLE OUTPUT CURRENT IN mA/BIT
ALLOWABLE OUTPUT CURRENT IN mA/BIT
VCE = 1 V
VCE = 1 V
80
VCE = 2 V
60
VCE = 3 V
VCE = 4 V
40
TA = +25oC
VDD = 5 V
RQJA = 75oC/W
20
0
0
0
20
40
60
80
0
100
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-6
Dwg. GP-062-11
100
100
80
VCE = 2 V
VCE = 3 V
60
VCE = 4 V
40
TA = +50oC
VDD = 5 V
RQJA = 50oC/W
20
0
0
20
40
60
80
VCE = 0.7 V
ALLOWABLE OUTPUT CURRENT IN mA/BIT
ALLOWABLE OUTPUT CURRENT IN mA/BIT
VCE = 1 V
100
DUTY CYCLE IN PER CENT
80
VCE = 1 V
VCE = 2 V
60
VCE = 3 V
40
VCE = 4 V
TA = +50oC
VDD = 5 V
RQJA = 75oC/W
20
0
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
Dwg. GP-062-10
Dwg. GP-062-7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6276EA
A6276ELW
100
100
VCE = 0.4 V
ALLOWABLE OUTPUT CURRENT IN mA/BIT
VCE = 1 V
80
VCE = 2 V
60
VCE = 3 V
40
VCE = 4 V
TA = +85oC
VDD = 5 V
RQJA = 50oC/W
20
80
VCE = 0.7 V
VCE = 1 V
60
VCE = 2 V
VCE = 3 V
40
VCE = 4 V
TA = +85oC
VDD = 5 V
RQJA = 75oC/W
20
0
0
0
20
40
60
80
0
100
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-8
Dwg. GP-062-9
TYPICAL CHARACTERISTICS
60
OUTPUT CURRENT IN mA/BIT
ALLOWABLE OUTPUT CURRENT IN mA/BIT
VCE = 0.7 V
40
TA = +25oC
REXT = 500 7
20
0
0
0.5
1.0
1.5
2.0
VCE IN VOLTS
Dwg. GP-063
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6276ELP
100
ALLOWABLE OUTPUT CURRENT IN mA/BIT
VCE = 1 V
80
VCE = 2 V
VCE = 3 V
60
VCE = 4 V
40
TA = +25ı°C
VDD = 5 V
RˇQJA = 40ı°C/W
20
0
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
100
ALLOWABLE OUTPUT CURRENT IN mA/BIT
VCE = 1 V
80
VCE = 2 V
VCE = 3 V
60
VCE = 4 V
40
TA = +50ı°C
VDD = 5 V
RˇQJA = 40ı°C/W
20
0
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Applications Information
The load current per bit (IO) is set by the external resistor
(REXT) as shown in the figure below.
100
V CE = 0.7 V
80
For reference, typical LED forward voltages are:
White
3.5 – 4.0 V
Blue
3.0 – 4.0 V
Green
1.8 – 2.2 V
Yellow
2.0 – 2.1 V
Amber
1.9 – 2.65 V
Red
1.6 – 2.25 V
Infrared
1.2 – 1.5 V
60
40
20
0
100
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
200
300
500
700
CURRENT-CONTROL RESISTANCE, R
2k
1k
EXT
3k
5k
IN OHMS
Dwg. GP-061
Package Power Dissipation (PD). The maximum allowable package power dissipation is determined as
PD(max) = (150 - TA)/RJA.
The actual package power dissipation is
PD(act) = DC • (VCE • IO • 16) + (VDD • IDD) ,
where DC is the duty cycle.
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage reducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are designed to operate with driver voltage drops (VCE) of
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
Pattern Layout. This device has a common logic-ground
and power-ground terminal. If ground pattern layout
contains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
V
LED
V DROP
VF
V CE
Dwg. EP-064
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
11
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Package A, 24-pin DIP
+0.25
30.10 –0.64
24
+0.10
0.38 –0.05
+0.76
6.35 –0.25
+0.38
10.92 –0.25
5.33 MAX
For Reference Only
(reference JEDEC MS-001 BE)
Dimensions in millimeters
7.62
A
1
2
+0.51
3.30 –0.38
1.27 MIN
2.54
+0.25
1.52 –0.38
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
0.018
0.46 ±0.12
Package A, 24-pin TSSOP
with exposed thermal pad
7.80 ±0.10
24
0.65
0.45
4° ±4
+0.05
0.15 –0.06
B
3.00
4.40 ±0.10
6.40 ±0.20
A
1
6.10
(1.00)
2
4.32
0.25
24X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.60 ±0.15
0.65
1.20 MAX
0.15 MAX
C
SEATING PLANE
GAUGE PLANE
1.65
4.32
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
Package LW, 24-pin SOICW
15.40±0.20
4° ±4
24
+0.07
0.27 –0.06
2.20
10.30±0.33
7.50±0.10
A
1
24
9.60
+0.44
0.84 –0.43
2
1
2
0.65
0.25
24X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
2.65 MAX
0.20 ±0.10
C
SEATING PLANE
GAUGE PLANE
1.27
B PCB Layout Reference View
For Reference Only
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2000-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13