MICROCONTROLLERS JTAGICE mkII On-chip DEBUG AVR APPLICATIONS USING JTAG OR DEBUGWIRE INTERFACE The AVR® JTAGICE mklI from Atmel® is a powerful development tool for On-chip Debugging of all AVR 8-bit RISC microcontrollers with IEEE 1149.1 compliant JTAG interface or debugWIRE Interface. DebugWIRE enables on chip debug of AVR microcontrollers in small pin count packages, using only a single wire for the debug interface. The JTAGICE mkII and the AVR Studio® user interface give the user complete control of the internal resources of the microcontroller, helping to reduce development time by making debugging easier. The JTAGICE mkII performs Real Time emulation of the microcontroller while it is running in a target system. The JTAGICE mkII provides emulation capability at a fraction of the cost of traditional emulators. O AVR Studio Operated O Program and Data Breakpoints O Full Emulation of All Analog and Digital O All Operations and Breakpoints are Real Time Functions O Full JTAG Programming Support O O Supports Multiple Devices in a JTAG Scan Chain Adapter for Direct Connection to STK500 O Upgrades are done from AVR Studio O USB 1.1 or RS-232 Interface to PC O Target Voltage 1.8 – 5.5V O Full Support for Assembly and High Level Languages O Supply Voltage 9V – 12V, or Powered from USB port Debug System J TA G I C E MK Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 USA TEL: (1)(408) 441-0311 FAX: (1)(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL: (41) 26-426-5555 FAX: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL: (852) 2721-9778 FAX: (852) 2722-1369 II AVR ON-CHIP DEBUG SYSTEM The JTAGICE mkII allows access to all the powerful features of the AVR microcontroller. All AVR resources can be monitored: Flash memory, EEPROM memory, SRAM memory, Register File, Program Counter, Fuse and Lock Bits, and all I/O modules. The JTAGICE mkII also offers extensive On-chip Debug support for break conditions, including break on change of Program memory flow, Program memory Break Points on single address or address range, and Data memory Break Points on single address or address range. The debugWIRE uses the Reset line for electrical connection; hence the system designer does not have to sacrifice I/O capabilities to take full advantage of the On-Chip-Debug system. Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL: (81) 3-3523-3551 FAX: (81) 3-3523-7581 The JTAGICE mkII will automatically be Web Site http://www.atmel.com they are released. upgraded by future AVR Studio releases to support future devices with JTAG and debugWIRE support as The JTAGICE mkII interface is integrated in AVR Studio, Atmel’s front-end tool for development on the AVR architecture. All phases of the AVR development can be done in this Integrated Development Environment. Supported Devices JTAG DebugWIRE ATmega16 ATmega6490 ATtiny13 ATmega162 ATmega128 ATtiny2313 ATmega169 ATmega1281 ATtiny25 ATmega32 ATmega1280 ATtiny45 ATmega329 ATmega128CAN11 ATmega48 ATmega3290 ATmega256 ATmega88 ATmega64 ATmega2560 ATmega168 ATmega649 Note: Low voltage devices are also supported. Ordering Information The JTAGICE is available from Atmel franchised distributors. © Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof, AVR®, AVR Studio®, are registered trademarks of Atmel. Other terms and product names may be trademarks of others. 2489D-AVR-02/04/0M The ordering code is ATJTAGICE2 The latest version of AVR Studio is available free of charge from Atmel web site: www.atmel.com The JTAGICE will automatically be upgraded by future AVR Studio releases to support future devices with JTAG support as they are released.