SILABS C8051F331-GM Mixed-signal isp flash mcu Datasheet

C8051F330/1/2/3/4/5
Mixed-Signal ISP Flash MCU
Analog Peripherals
- 10-Bit ADC (‘F330/2/4 only)
• Up to 200 ksps
• Up to 16 external single-ended or differential inputs
• VREF from internal VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- 10-Bit Current Output DAC (‘F330 only)
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current (0.4 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 768 bytes internal data RAM (256 + 512)
- 8 kB (‘F330/1), 4 kB (‘F332/3), or 2 kB (‘F334/5)
Flash; In-system programmable in 512-byte Sectors—512 bytes are reserved in the 8 kB devices
Digital Peripherals
- 17 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART, SMBus™, and
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping, 
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
-
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.4 mA at 25 MHz;
enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules
Real time clock mode using PCA or timer and external clock source
Clock Sources
- Two internal oscillators:
• 24.5 MHz with ±2% accuracy supports crystal-less
9 µA at 32 kHz
- Typical stop mode current: 0.1 µA
Temperature Range: –40 to +85 °C
UART operation
80/40/20/10 kHz low frequency, low power
•
-
External oscillator: Crystal, RC, C, or clock 
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
20-Pin QFN Package
ANALOG
PERIPHERALS
10-bit
200 ksps
ADC
TEMP
SENSOR
‘F330/2/4 only
10-bit
Current
DAC
‘F330 only
+
VOLTAGE
COMPARATOR
24.5 MHz PRECISION
INTERNAL OSCILLATOR
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CROSSBAR
A
M
U
X
DIGITAL I/O
Port 0
Port 1
P2.0
LOW FREQUENCY INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
2/4/8 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
Rev. 1.7 12/10
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR
Copyright © 2010 by Silicon Laboratories
WDT
C8051F330/1/2/3/4/5
C8051F330/1/2/3/4/5
2
Rev. 1.7
C8051F330/1/2/3/4/5
Table of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 22
1.1.1. Fully 8051 Compatible.............................................................................. 22
1.1.2. Improved Throughput ............................................................................... 22
1.1.3. Additional Features .................................................................................. 23
1.2. On-Chip Memory............................................................................................... 24
1.3. On-Chip Debug Circuitry................................................................................... 25
1.4. Programmable Digital I/O and Crossbar ........................................................... 26
1.5. Serial Ports ....................................................................................................... 26
1.6. Programmable Counter Array ........................................................................... 27
1.7. 10-Bit Analog to Digital Converter..................................................................... 28
1.8. Comparators ..................................................................................................... 29
1.9. 10-bit Current Output DAC................................................................................ 30
2. Absolute Maximum Ratings .................................................................................. 31
3. Global Electrical Characteristics .......................................................................... 32
4. Pinout and Package Definitions............................................................................ 35
5. 10-Bit ADC (ADC0, C8051F330/2/4 only) .............................................................. 41
5.1. Analog Multiplexer ............................................................................................ 41
5.2. Temperature Sensor ......................................................................................... 42
5.3. Modes of Operation .......................................................................................... 43
5.3.1. Starting a Conversion............................................................................... 44
5.3.2. Tracking Modes........................................................................................ 45
5.3.3. Settling Time Requirements ..................................................................... 46
5.4. Programmable Window Detector ...................................................................... 51
5.4.1. Window Detector In Single-Ended Mode ................................................. 53
5.4.2. Window Detector In Differential Mode...................................................... 54
6. 10-Bit Current Mode DAC (IDA0, C8051F330 only).............................................. 57
6.1. IDA0 Output Scheduling ................................................................................... 57
6.1.1. Update Output On-Demand ..................................................................... 57
6.1.2. Update Output Based on Timer Overflow ................................................ 58
6.1.3. Update Output Based on CNVSTR Edge................................................. 58
6.2. IDAC Output Mapping....................................................................................... 58
7. Voltage Reference (C8051F330/2/4 only).............................................................. 61
8. Comparator0 ........................................................................................................... 65
9. CIP-51 Microcontroller ........................................................................................... 71
9.1. Instruction Set ................................................................................................... 72
9.1.1. Instruction and CPU Timing ..................................................................... 72
9.1.2. MOVX Instruction and Program Memory ................................................. 72
9.2. Memory Organization........................................................................................ 76
9.2.1. Program Memory...................................................................................... 77
9.2.2. Data Memory............................................................................................ 78
9.2.3. General Purpose Registers ...................................................................... 78
9.2.4. Bit Addressable Locations........................................................................ 78
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C8051F330/1/2/3/4/5
9.2.5. Stack ....................................................................................................... 78
9.2.6. Special Function Registers....................................................................... 79
9.2.7. Register Descriptions ............................................................................... 83
9.3. Interrupt Handler ............................................................................................... 85
9.3.1. MCU Interrupt Sources and Vectors ........................................................ 86
9.3.2. External Interrupts .................................................................................... 87
9.3.3. Interrupt Priorities ..................................................................................... 87
9.3.4. Interrupt Latency ...................................................................................... 87
9.3.5. Interrupt Register Descriptions................................................................. 89
9.4. Power Management Modes .............................................................................. 94
9.4.1. Idle Mode.................................................................................................. 94
9.4.2. Stop Mode ................................................................................................ 95
10. Reset Sources......................................................................................................... 97
10.1.Power-On Reset ............................................................................................... 98
10.2.Power-Fail Reset/VDD Monitor ........................................................................ 98
10.3.External Reset .................................................................................................. 99
10.4.Missing Clock Detector Reset .......................................................................... 99
10.5.Comparator0 Reset ........................................................................................ 100
10.6.PCA Watchdog Timer Reset .......................................................................... 100
10.7.Flash Error Reset ........................................................................................... 100
10.8.Software Reset ............................................................................................... 100
11. Flash Memory ....................................................................................................... 103
11.1.Programming The Flash Memory ................................................................... 103
11.1.1.Flash Lock and Key Functions ............................................................... 103
11.1.2.Flash Erase Procedure .......................................................................... 103
11.1.3.Flash Write Procedure ........................................................................... 104
11.2.Non-volatile Data Storage .............................................................................. 104
11.3.Security Options ............................................................................................. 105
11.4.Flash Write and Erase Guidelines .................................................................. 107
11.4.1.VDD Maintenance and the VDD monitor ................................................. 107
11.4.2.PSWE Maintenance ............................................................................... 107
11.4.3.System Clock ......................................................................................... 108
12. External RAM ........................................................................................................ 111
13. Oscillators ............................................................................................................. 113
13.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 113
13.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 115
13.2.1.Calibrating the Internal L-F Oscillator..................................................... 115
13.3.External Oscillator Drive Circuit...................................................................... 116
13.3.1.External Crystal Example....................................................................... 118
13.3.2.External RC Example............................................................................. 120
13.3.3.External Capacitor Example................................................................... 120
13.4.System Clock Selection.................................................................................. 121
14. Port Input/Output.................................................................................................. 123
14.1.Priority Crossbar Decoder .............................................................................. 125
14.2.Port I/O Initialization ....................................................................................... 127
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14.3.General Purpose Port I/O ............................................................................... 129
15. SMBus ................................................................................................................... 135
15.1.Supporting Documents ................................................................................... 136
15.2.SMBus Configuration...................................................................................... 136
15.3.SMBus Operation ........................................................................................... 136
15.3.1.Arbitration............................................................................................... 137
15.3.2.Clock Low Extension.............................................................................. 138
15.3.3.SCL Low Timeout................................................................................... 138
15.3.4.SCL High (SMBus Free) Timeout .......................................................... 138
15.4.Using the SMBus............................................................................................ 138
15.4.1.SMBus Configuration Register............................................................... 140
15.4.2.SMB0CN Control Register ..................................................................... 143
15.4.3.Data Register ......................................................................................... 146
15.5.SMBus Transfer Modes.................................................................................. 146
15.5.1.Master Transmitter Mode ....................................................................... 146
15.5.2.Master Receiver Mode ........................................................................... 148
15.5.3.Slave Receiver Mode ............................................................................. 149
15.5.4.Slave Transmitter Mode ......................................................................... 150
15.6.SMBus Status Decoding................................................................................. 150
16. UART0.................................................................................................................... 153
16.1.Enhanced Baud Rate Generation................................................................... 154
16.2.Operational Modes ......................................................................................... 155
16.2.1.8-Bit UART ............................................................................................. 155
16.2.2.9-Bit UART ............................................................................................. 156
16.3.Multiprocessor Communications .................................................................... 156
17. Enhanced Serial Peripheral Interface (SPI0)...................................................... 163
17.1.Signal Descriptions......................................................................................... 164
17.1.1.Master Out, Slave In (MOSI).................................................................. 164
17.1.2.Master In, Slave Out (MISO).................................................................. 164
17.1.3.Serial Clock (SCK) ................................................................................. 164
17.1.4.Slave Select (NSS) ................................................................................ 164
17.2.SPI0 Master Mode Operation ......................................................................... 165
17.3.SPI0 Slave Mode Operation ........................................................................... 167
17.4.SPI0 Interrupt Sources ................................................................................... 167
17.5.Serial Clock Timing......................................................................................... 168
17.6.SPI Special Function Registers ...................................................................... 169
18. Timers.................................................................................................................... 177
18.1.Timer 0 and Timer 1 ....................................................................................... 177
18.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 177
18.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 178
18.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 179
18.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 180
18.2.Timer 2 .......................................................................................................... 185
18.2.1.16-bit Timer with Auto-Reload................................................................ 185
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C8051F330/1/2/3/4/5
18.2.2.8-bit Timers with Auto-Reload................................................................ 186
18.3.Timer 3 .......................................................................................................... 189
18.3.1.16-bit Timer with Auto-Reload................................................................ 189
18.3.2.8-bit Timers with Auto-Reload................................................................ 190
19. Programmable Counter Array ............................................................................. 193
19.1.PCA Counter/Timer ........................................................................................ 194
19.2.Capture/Compare Modules ............................................................................ 195
19.2.1.Edge-triggered Capture Mode................................................................ 196
19.2.2.Software Timer (Compare) Mode........................................................... 197
19.2.3.High-Speed Output Mode ...................................................................... 198
19.2.4.Frequency Output Mode ........................................................................ 199
19.2.5.8-Bit Pulse Width Modulator Mode......................................................... 200
19.2.6.16-Bit Pulse Width Modulator Mode....................................................... 201
19.3.Watchdog Timer Mode ................................................................................... 201
19.3.1.Watchdog Timer Operation .................................................................... 202
19.3.2.Watchdog Timer Usage ......................................................................... 203
19.4.Register Descriptions for PCA........................................................................ 204
20. C2 Interface ........................................................................................................... 209
20.1.C2 Interface Registers.................................................................................... 209
20.2.C2 Pin Sharing ............................................................................................... 211
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C8051F330/1/2/3/4/5
List of Figures
1. System Overview
Figure 1.1. C8051F330 Block Diagram.................................................................... 19
Figure 1.2. C8051F331 Block Diagram.................................................................... 19
Figure 1.3. C8051F332 Block Diagram.................................................................... 20
Figure 1.4. C8051F333 Block Diagram.................................................................... 20
Figure 1.5. C8051F334 Block Diagram.................................................................... 21
Figure 1.6. C8051F335 Block Diagram.................................................................... 21
Figure 1.7. Comparison of Peak MCU Execution Speeds ....................................... 22
Figure 1.8. On-Chip Clock and Reset ...................................................................... 23
Figure 1.9. On-Board Memory Map ......................................................................... 24
Figure 1.10. Development/In-System Debug Diagram............................................. 25
Figure 1.11. Digital Crossbar Diagram ..................................................................... 26
Figure 1.12. PCA Block Diagram.............................................................................. 27
Figure 1.13. PCA Block Diagram.............................................................................. 27
Figure 1.14. 10-Bit ADC Block Diagram ................................................................... 28
Figure 1.15. Comparator0 Block Diagram ................................................................ 29
Figure 1.16. IDA0 Functional Block Diagram ........................................................... 30
2. Absolute Maximum Ratings
3. Global Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. QFN-20 Pinout Diagram (Top View)...................................................... 37
5. 10-Bit ADC (ADC0, C8051F330/2/4 only)
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 41
Figure 5.2. Typical Temperature Sensor Transfer Function .................................... 43
Figure 5.3. 10-Bit ADC Track and Conversion Example Timing.............................. 45
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 46
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data... 53
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 53
Figure 5.7. ADC Window Compare Example: Right-Justified Differential Data ....... 54
Figure 5.8. ADC Window Compare Example: Left-Justified Differential Data ......... 54
6. 10-Bit Current Mode DAC (IDA0, C8051F330 only)
Figure 6.1. IDA0 Functional Block Diagram............................................................. 57
Figure 6.2. IDA0 Data Word Mapping...................................................................... 58
7. Voltage Reference (C8051F330/2/4 only)
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 61
8. Comparator0
Figure 8.1. Comparator0 Functional Block Diagram................................................ 65
Figure 8.2. Comparator Hysteresis Plot................................................................... 66
9. CIP-51 Microcontroller
Figure 9.1. CIP-51 Block Diagram ........................................................................... 71
Figure 9.2. Memory Map.......................................................................................... 77
10. Reset Sources
Figure 10.1. Reset Sources...................................................................................... 97
Rev. 1.7
7
C8051F330/1/2/3/4/5
Figure 10.2. Power-On and VDD Monitor Reset Timing .......................................... 98
11. Flash Memory
Figure 11.1. Flash Program Memory Map.............................................................. 105
12. External RAM
13. Oscillators
Figure 13.1. Oscillator Diagram.............................................................................. 113
Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 119
14. Port Input/Output
Figure 14.1. Port I/O Functional Block Diagram ..................................................... 123
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 124
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped ............................... 125
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 126
15. SMBus
Figure 15.1. SMBus Block Diagram ....................................................................... 135
Figure 15.2. Typical SMBus Configuration ............................................................. 136
Figure 15.3. SMBus Transaction ............................................................................ 137
Figure 15.4. Typical SMBus SCL Generation......................................................... 141
Figure 15.5. Typical Master Transmitter Sequence................................................ 147
Figure 15.6. Typical Master Receiver Sequence.................................................... 148
Figure 15.7. Typical Slave Receiver Sequence...................................................... 149
Figure 15.8. Typical Slave Transmitter Sequence.................................................. 150
16. UART0
Figure 16.1. UART0 Block Diagram ....................................................................... 153
Figure 16.2. UART0 Baud Rate Logic .................................................................... 154
Figure 16.3. UART Interconnect Diagram .............................................................. 155
Figure 16.4. 8-Bit UART Timing Diagram............................................................... 155
Figure 16.5. 9-Bit UART Timing Diagram............................................................... 156
Figure 16.6. UART Multi-Processor Mode Interconnect Diagram .......................... 157
17. Enhanced Serial Peripheral Interface (SPI0)
Figure 17.1. SPI Block Diagram ............................................................................. 163
Figure 17.2. Multiple-Master Mode Connection Diagram ....................................... 166
Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode 
Connection Diagram166
Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 
Connection Diagram166
Figure 17.5. Master Mode Data/Clock Timing ........................................................ 168
Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 169
Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 169
Figure 17.8. SPI Master Timing (CKPHA = 0)........................................................ 173
Figure 17.9. SPI Master Timing (CKPHA = 1)........................................................ 173
Figure 17.10. SPI Slave Timing (CKPHA = 0)........................................................ 174
Figure 17.11. SPI Slave Timing (CKPHA = 1)........................................................ 174
18. Timers
Figure 18.1. T0 Mode 0 Block Diagram.................................................................. 178
Figure 18.2. T0 Mode 2 Block Diagram.................................................................. 179
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C8051F330/1/2/3/4/5
Figure 18.3. T0 Mode 3 Block Diagram.................................................................. 180
Figure 18.4. Timer 2 16-Bit Mode Block Diagram .................................................. 185
Figure 18.5. Timer 2 8-Bit Mode Block Diagram .................................................... 186
Figure 18.6. Timer 3 16-Bit Mode Block Diagram .................................................. 189
Figure 18.7. Timer 3 8-Bit Mode Block Diagram .................................................... 190
19. Programmable Counter Array
Figure 19.1. PCA Block Diagram............................................................................ 193
Figure 19.2. PCA Counter/Timer Block Diagram.................................................... 194
Figure 19.3. PCA Interrupt Block Diagram ............................................................. 195
Figure 19.4. PCA Capture Mode Diagram.............................................................. 196
Figure 19.5. PCA Software Timer Mode Diagram .................................................. 197
Figure 19.6. PCA High-Speed Output Mode Diagram............................................ 198
Figure 19.7. PCA Frequency Output Mode ............................................................ 199
Figure 19.8. PCA 8-Bit PWM Mode Diagram ......................................................... 200
Figure 19.9. PCA 16-Bit PWM Mode...................................................................... 201
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled ................................. 202
20. C2 Interface
Figure 20.1. Typical C2 Pin Sharing....................................................................... 211
Rev. 1.7
9
C8051F330/1/2/3/4/5
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 18
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 31
3. Global Electrical Characteristics
Table 3.1. Global Electrical Characteristics ............................................................. 32
Table 3.2. Index to Electrical Characteristics Tables............................................... 34
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5........................................... 35
Table 4.2. QFN-20 Package Dimensions ................................................................ 38
Table 4.3. QFN-20 PCB Land Pattern Dimesions ................................................... 39
5. 10-Bit ADC (ADC0, C8051F330/2/4 only)
Table 5.1. ADC0 Electrical Characteristics.............................................................. 55
6. 10-Bit Current Mode DAC (IDA0, C8051F330 only)
Table 6.1. IDAC Electrical Characteristics............................................................... 60
7. Voltage Reference (C8051F330/2/4 only)
Table 7.1. Voltage Reference Electrical Characteristics.......................................... 63
8. Comparator0
Table 8.1. Comparator Electrical Characteristics .................................................... 70
9. CIP-51 Microcontroller
Table 9.1. CIP-51 Instruction Set Summary ............................................................ 73
Table 9.2. Special Function Register (SFR) Memory Map ...................................... 79
Table 9.3. Special Function Registers ..................................................................... 80
Table 9.4. Interrupt Summary .................................................................................. 88
10. Reset Sources
Table 10.1. Reset Electrical Characteristics .......................................................... 102
11. Flash Memory
Table 11.1. Flash Electrical Characteristics........................................................... 104
Table 11.2. Flash Security Summary..................................................................... 106
12. External RAM
13. Oscillators
Table 13.1. Internal Oscillator Electrical Characteristics ....................................... 122
14. Port Input/Output
Table 14.1. Port I/O DC Electrical Characteristics................................................. 134
15. SMBus
Table 15.1. SMBus Clock Source Selection .......................................................... 140
Table 15.2. Minimum SDA Setup and Hold Times ................................................ 141
Table 15.3. Sources for Hardware Changes to SMB0CN ..................................... 145
Table 15.4. SMBus Status Decoding..................................................................... 151
16. UART0
Table 16.1. Timer Settings for Standard Baud Rates Using the 
Internal 24.5 MHz Oscillator ............................................................... 160
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C8051F330/1/2/3/4/5
Table 16.2. Timer Settings for Standard Baud Rates Using an 
External 25.0 MHz Oscillator ..............................................................
Table 16.3. Timer Settings for Standard Baud Rates Using an 
External 22.1184 MHz Oscillator ........................................................
Table 16.4. Timer Settings for Standard Baud Rates Using an 
External 18.432 MHz Oscillator ..........................................................
Table 16.5. Timer Settings for Standard Baud Rates Using an 
External 11.0592 MHz Oscillator ........................................................
Table 16.6. Timer Settings for Standard Baud Rates Using an 
External 3.6864 MHz Oscillator ..........................................................
17. Enhanced Serial Peripheral Interface (SPI0)
Table 17.1. SPI Slave Timing Parameters ............................................................
18. Timers
19. Programmable Counter Array
Table 19.1. PCA Timebase Input Options .............................................................
Table 19.2. PCA0CPM Register Settings for PCA Capture/Compare Modules ....
Table 19.3. Watchdog Timer Timeout Intervals1...................................................
20. C2 Interface
12
Rev. 1.7
160
161
161
162
162
175
194
195
204
C8051F330/1/2/3/4/5
List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 47
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 51
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 51
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 52
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 52
SFR Definition 6.1. IDA0CN: IDA0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SFR Definition 6.2. IDA0H: IDA0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SFR Definition 6.3. IDA0L: IDA0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SFR Definition 8.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 9.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 9.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 10.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 10.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SFR Definition 11.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 11.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 11.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 111
SFR Definition 13.1. OSCICL: Internal H-F Oscillator Calibration . . . . . . . . . . . . . . . 114
SFR Definition 13.2. OSCICN: Internal H-F Oscillator Control . . . . . . . . . . . . . . . . . . 114
SFR Definition 13.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 115
SFR Definition 13.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 117
SFR Definition 13.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 128
SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 129
SFR Definition 14.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Rev. 1.7
13
C8051F330/1/2/3/4/5
SFR Definition 14.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SFR Definition 14.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 14.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 14.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 14.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.10. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.11. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SFR Definition 14.12. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 133
SFR Definition 15.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 142
SFR Definition 15.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SFR Definition 15.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 16.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 16.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 159
SFR Definition 17.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 170
SFR Definition 17.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
SFR Definition 17.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 17.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 18.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
SFR Definition 18.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SFR Definition 18.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
SFR Definition 18.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 18.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 18.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 18.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SFR Definition 18.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 188
SFR Definition 18.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 188
SFR Definition 18.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
SFR Definition 18.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
SFR Definition 18.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
SFR Definition 18.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 192
SFR Definition 18.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 192
SFR Definition 18.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SFR Definition 18.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SFR Definition 19.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
SFR Definition 19.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
SFR Definition 19.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 207
SFR Definition 19.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 208
SFR Definition 19.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 208
SFR Definition 19.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 208
SFR Definition 19.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 208
C2 Register Definition 20.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
C2 Register Definition 20.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 209
C2 Register Definition 20.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 210
14
Rev. 1.7
C8051F330/1/2/3/4/5
C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 210
C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 210
Rev. 1.7
15
C8051F330/1/2/3/4/5
1.
System Overview
C8051F330/1/2/3/4/5 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.
•
•
•
•
•
•
•
•
•
•
•
•
•
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 10-bit 200 ksps 16-channel single-ended/differential ADC with analog multiplexer
10-bit Current Output DAC
Precision programmable 25 MHz internal oscillator
Up to 8 kB of on-chip Flash memory—512 bytes are reserved
768 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with three capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
On-chip Voltage Comparator
17 Port I/O (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F330/1/2/3/4/5 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can
be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–40 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F330/1/2/3/4/5 are available in
20-pin QFN packages (also referred to as MLP or MLF packages). Lead-free (RoHS compliant) packages
are also available. See Table 1.1 for ordering part numbers. Block diagrams are included in Figure 1.1,
Figure 1.2, Figure 1.3, Figure 1.4, Figure 1.5, and Figure 1.6.
Rev. 1.7
17
MIPS (Peak)
Flash Memory (kB)
RAM (bytes)
Calibrated Internal 24.5 MHz Oscillator
Internal 80 kHz Oscillator
SMBus/I2C
Enhanced SPI
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
10-bit 200ksps ADC
10-bit Current Output DAC
Internal Voltage Reference
Temperature Sensor
Analog Comparator
Lead-free (RoHS Compliant)
Package
Ordering Part Number
C8051F330/1/2/3/4/5
Table 1.1. Product Selection Guide
C8051F330-GM 25
8
768





4

17






QFN-20
C8051F331-GM 25
8
768





4

17
— — — —


QFN-20
C8051F332-GM 25
4
768





4

17




QFN-20
C8051F333-GM 25
4
768





4

17
— — — —


QFN-20
C8051F334-GM 25
2
768





4

17




QFN-20
C8051F335-GM 25
2
768





4

17
— — — —


QFN-20
18
Rev. 1.7
—
—


C8051F330/1/2/3/4/5
Port 0
Latch
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
UART
VDD
Analog/Digital
Power
GND
C2D
Debug HW
Reset
RST/C2CK
POR
BrownOut
External
Oscillator
Circuit
XTAL1
XTAL2
P
0
Timer 0,
1, 2, 3
System Clock
24.5 MHz (2%)
Internal
Oscillator
8
0
5
1
D
r
v
3-Chnl
PCA/
WDT
8 kB
FLASH
SMBus
SPI
256 byte
SRAM
P0.6/CNVSTR
P0.7
X
B
A
R
P1.0
P1.1
P1.2
P1.3
P1.4
Port 1
Latch
512 byte
XRAM
P
1
C
o SFR Bus
r
e
D
r
v
CP0
80 kHz
Internal
Oscillator
P1.5
P1.6
P1.7
+
-
VREF
10-bit
DAC
VDD
VREF
Temp
A
M
U
X
10-bit
200ksps
ADC
AIN0-AIN15
C2D
Port 2
Latch
P2.0/C2D
Figure 1.1. C8051F330 Block Diagram
Port 0
Latch
P0.0
P0.1
UART
VDD
GND
C2D
Debug HW
Reset
RST/C2CK
POR
XTAL1
XTAL2
BrownOut
External
Oscillator
Circuit
24.5 MHz (2%)
Internal
Oscillator
P
0
Timer 0,
1, 2, 3
Analog/Digital
Power
System Clock
8
0
5
1
D
r
v
3-Chnl
PCA/
WDT
8 kB
FLASH
SMBus
SPI
256 byte
SRAM
P0.6
P0.7
X
B
A
R
Port 1
Latch
512 byte
XRAM
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P
1
C
o SFR Bus
r
e
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
CP0
80 kHz
Internal
Oscillator
Port 2
Latch
+
-
C2D
P2.0/C2D
Figure 1.2. C8051F331 Block Diagram
Rev. 1.7
19
C8051F330/1/2/3/4/5
Port 0
Latch
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
UART
VDD
Timer 0,
1, 2, 3
Analog/Digital
Power
GND
C2D
Debug HW
Reset
/RST/C2CK
POR
BrownOut
External
Oscillator
Circuit
XTAL1
XTAL2
P
0
System Clock
24.5 MHz (2%)
Internal
Oscillator
8
0
5
1
D
r
v
3-Chnl
PCA/
WDT
4 kB
FLASH
SMBus
SPI
256 byte
SRAM
X
B
A
R
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 1
Latch
512 byte
XRAM
P
1
C
o SFR Bus
r
e
D
r
v
P1.6
P1.7
CP0
80 kHz
Internal
Oscillator
+
-
VREF
VDD
VREF
Temp
A
M
U
X
10-bit 200
ksps ADC
AIN0-AIN15
C2D
Port 2
Latch
P2.0/C2D
Figure 1.3. C8051F332 Block Diagram
Port 0
Latch
UART
VDD
GND
C2D
Debug HW
Reset
/RST/C2CK
POR
XTAL1
XTAL2
BrownOut
External
Oscillator
Circuit
24.5 MHz (2%)
Internal
Oscillator
P
0
Timer 0,
1, 2, 3
Analog/Digital
Power
System Clock
8
0
5
1
D
r
v
3-Chnl
PCA/
WDT
4 kB
FLASH
SMBus
SPI
256 byte
SRAM
X
B
A
R
P
1
C
o SFR Bus
r
e
D
r
v
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
CP0
80 kHz
Internal
Oscillator
Port 2
Latch
Figure 1.4. C8051F333 Block Diagram
20
P0.4/TX
P0.5/RX
P0.6
P0.7
P1.0
Port 1
Latch
512 byte
XRAM
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
Rev. 1.7
+
-
C2D
P2.0/C2D
C8051F330/1/2/3/4/5
Port 0
Latch
P0.0/VREF
P0.1
UART
VDD
Timer 0,
1, 2, 3
Analog/Digital
Power
GND
C2D
Debug HW
Reset
/RST/C2CK
POR
BrownOut
External
Oscillator
Circuit
XTAL1
XTAL2
System Clock
24.5 MHz (2%)
Internal
Oscillator
8
0
5
1
3-Chnl
PCA/
WDT
2 kB
FLASH
SMBus
SPI
256 byte
SRAM
P
0
P0.2/XTAL1
P0.3/XTAL2
D
r
v
P0.4/TX
P0.5/RX
P0.6/CNVST
X
B
A
R
P0.7
P1.0
P1.1
Port 1
Latch
512 byte
XRAM
C
o SFR Bus
r
e
P
1
P1.2
P1.3
D
r
v
P1.4
P1.5
P1.6
P1.7
CP0
80 kHz
Internal
Oscillator
+
-
VREF
VDD
VREF
Temp
A
M
U
X
10-bit 200
ksps ADC
AIN0-AIN15
C2D
Port 2
Latch
P2.0/C2D
Figure 1.5. C8051F334 Block Diagram
Port 0
Latch
P0.0
P0.1
UART
VDD
Timer 0,
1, 2, 3
Analog/Digital
Power
GND
C2D
Debug HW
Reset
/RST/C2CK
POR
XTAL1
XTAL2
BrownOut
External
Oscillator
Circuit
24.5 MHz (2%)
Internal
Oscillator
System Clock
8
0
5
1
3-Chnl
PCA/
WDT
2 kB
FLASH
SMBus
SPI
256 byte
SRAM
P
0
P0.2/XTAL1
D
r
v
P0.4/TX
P0.5/RX
P0.6
X
B
A
R
P0.7
P1.0
Port 1
Latch
512 byte
XRAM
P0.3/XTAL2
P1.1
C
o SFR Bus
r
e
P
1
P1.2
D
r
v
P1.4
P1.3
P1.5
P1.6
P1.7
CP0
80 kHz
Internal
Oscillator
Port 2
Latch
+
-
C2D
P2.0/C2D
Figure 1.6. C8051F335 Block Diagram
Rev. 1.7
21
C8051F330/1/2/3/4/5
1.1.
CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F330/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,
including four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an
enhanced SPI port, 768 bytes of internal RAM, 128 byte Special Function Register (SFR) address space,
and 17 I/O pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.7
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.
25
MIPS
20
15
10
5
Silicon Labs
Microchip
Philips
ADuC812
CIP-51
PIC17C75x
80C51
8051
(25 MHz clk) (33 MHz clk) (33 MHz clk) (16 MHz clk)
Figure 1.7. Comparison of Peak MCU Execution Speeds
22
Rev. 1.7
C8051F330/1/2/3/4/5
1.1.3. Additional Features
The C8051F330/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below VRST as given in Table 10.1 on page 102), a Watchdog Timer, a
Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external
reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input
Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization.
The internal oscillator factory calibrated to 24.5 MHz ±2%. This internal oscillator period may be user programmed in ~0.5% increments. An additional low-frequency oscillator is also available which facilitates
low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic
resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock
source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power
saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed.
VDD
Power On
Reset
Supply
Monitor
Px.x
Px.x
+
-
Comparator 0
'0'
Enable
(wired-OR)
/RST
+
C0RSEF
Missing
Clock
Detector
(oneshot)
EN
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
Errant
FLASH
Operation
Internal
Oscillator
XTAL1
XTAL2
External
Oscillator
Drive
MCD
Enable
System
Clock
Clock Select
WDT
Enable
EN
Low
Frequency
Oscillator
CIP-51
Microcontroller
Core
System Reset
Extended Interrupt
Handler
Figure 1.8. On-Chip Clock and Reset
Rev. 1.7
23
C8051F330/1/2/3/4/5
1.2.
On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 2/4/8 kB of Flash. This memory may be reprogrammed in-system in 512 byte
sectors, and requires no special off-chip programming voltage. See Figure 1.9 for the MCU system memory map.
C8051F330/1
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
0xFF
0x1E00
Upper 128 RAM
(Indirect Addressing
Only)
RESERVED
0x1DFF
0x80
0x7F
(Direct and Indirect
Addressing)
8 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
Bit Addressable
0x20
0x1F
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
0x00
0x0000
EXTERNAL DATA ADDRESS SPACE
C8051F332/3
PROGRAM/DATA MEMORY
(FLASH)
0x1000
0xFFFF
RESERVED
Same 512 bytes as from
0x0000 to 0x01FF, wrapped
on 512-byte boundaries
0x0FFF
4 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0200
0x01FF
0x0000
XRAM - 512 Bytes
(accessable using MOVX
instruction)
0x0000
C8051F334/5
PROGRAM/DATA MEMORY
(FLASH)
0x800
RESERVED
0x7FF
2 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
Figure 1.9. On-Board Memory Map
24
Rev. 1.7
C8051F330/1/2/3/4/5
1.3.
On-Chip Debug Circuitry
The C8051F330/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides
non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them synchronized.
The C8051F330DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F330/1/2/3/4/5 MCUs. The kit includes software
with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter. It also has a
target application board with the associated MCU installed and prototyping area, plus the required cables,
and wall-mount power supply. The Development Kit requires a PC running Windows98SE or later.
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to
standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
Silicon Labs Integrated
Development Environment
WINDOWS 98SE or later
Debug
Adapter
C2 (x2), VDD, GND
VDD
TARGET PCB
GND
C8051F330
Figure 1.10. Development/In-System Debug Diagram
Rev. 1.7
25
C8051F330/1/2/3/4/5
1.4.
Programmable Digital I/O and Crossbar
C8051F330/1/2/3/4/5 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The
C8051F330/1/2/3/4/5 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be
configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be
globally disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See
Figure 1.11.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control
registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for the particular application.
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Priority
Decoder
(Internal Digital Signals)
Highest
Priority
UART
8
P0
I/O
Cells
4
SPI
SMBus
CP0
Outputs
2
Digital
Crossbar
8
P1
I/O
Cells
P0.0
P0.7
P1.0
P1.7
2
SYSCLK
4
PCA
Lowest
Priority
2
T0, T1
2
(Port Latches)
8
P0
(P0.0-P0.7)
8
P1
(P1.0-P1.7)
Figure 1.11. Digital Crossbar Diagram
1.5.
Serial Ports
The C8051F330/1/2/3/4/5 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced
baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in
hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
26
Rev. 1.7
C8051F330/1/2/3/4/5
1.6.
Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
PCA
CLOCK
MUX
16-Bit Counter/Timer
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2 / WDT
CEX2
CEX1
CEX0
ECI
Crossbar
Port I/O
Figure 1.13. PCA Block Diagram
Rev. 1.7
27
C8051F330/1/2/3/4/5
1.7.
10-Bit Analog to Digital Converter
The C8051F330/2/4 devices include an on-chip 10-bit SAR ADC with a 16-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of
±1 LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports0-1 are available as an ADC inputs; additionally, the on-chip Temperature Sensor
output and the power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the
ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
P0.0
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0INT
AD0BUSY
AD0EN
VDD
P1.7
Start
Conversion
10-Bit
SAR
P0.0
(+)
18-to-1
AMUX
P1.7
AD0BUSY (W)
001
Timer 0 Overflow
010
Timer 2 Overflow
011
Timer 1 Overflow
100
CNVSTR Input
101
Timer 3 Overflow
ADC0H
ADC
(-)
SYSCLK
P0.7
P1.0
ADC0L
VDD
000
REF
Temp
Sensor
AD0TM
AMX0P0
ADC0CN
AMX0P1
AMX0P2
18-to-1
AMUX
AMX0P3
P0.7
P1.0
AMX0P4
AMX0P
AD0WINT
VREF
AD0SC0
AD0LJST
AD0SC1
AD0SC2
AD0SC3
AMX0N0
AMX0N1
AMX0N2
AMX0N3
AMX0N4
AMX0N
AD0SC4
GND
ADC0CF
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
Figure 1.14. 10-Bit ADC Block Diagram
28
Rev. 1.7
Window
Compare
Logic
C8051F330/1/2/3/4/5
1.8.
Comparators
C8051F330/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two
comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed
and low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.15 shows the Comparator0 block diagram.
CP0EN
CPT0CN
CP0OUT
CMX0N1
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0HYP0
CMX0N0
CP0HYN1
CMX0P3
CP0HYN0
CMX0P2
CMX0P1
CMX0P0
P0.0
P0.2
P0.4
P0.6
CP0 +
CP0
+
P1.0
D
-
P1.2
SET
CLR
D
Q
Q
SET
CLR
Q
Q
Crossbar
P1.4
(SYNCHRONIZER)
GND
P1.6
CP0A
Reset
Decision
Tree
P0.1
CP0RIF
P0.3
CP0FIF
P0.5
P0.7
0
CP0EN
EA
1
0
0
0
1
1
CP0
Interrupt
1
CP0 -
P1.1
P1.3
P1.5
P1.7
CPT0MD
CPT0MX
CMX0N3
CMX0N2
CP0RIE
CP0FIE
CP0MD1
CP0MD0
Figure 1.15. Comparator0 Block Diagram
Rev. 1.7
29
C8051F330/1/2/3/4/5
1.9.
10-bit Current Output DAC
IDA0CN
CNVSTR
Timer 3
Timer 2
Timer 1
IDA0EN
IDA0CM2
IDA0CM1
IDA0CM0
Timer 0
IDA0H
The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum
current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA.
IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDA0 output
updates on a write to IDA0H, on a Timer overflow, or on an external pin edge.
IDA0H
8
IDA0L
IDA0OMD1
IDA0OMD0
2
10
Latch
IDA0
Figure 1.16. IDA0 Functional Block Diagram
30
Rev. 1.7
IDA0
C8051F330/1/2/3/4/5
2.
Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings
Parameter
Conditions
Min
Typ
Max
Units
Ambient temperature under bias
–55
—
125
°C
Storage Temperature
–65
—
150
°C
Voltage on any Port I/O Pin or RST with
respect to GND
–0.3
—
5.8
V
Voltage on VDD with respect to GND
–0.3
—
4.2
V
Maximum Total current through VDD or GND
—
—
500
mA
Maximum output current sunk by RST or any
Port pin
—
—
100
mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Rev. 1.7
31
C8051F330/1/2/3/4/5
3.
Global Electrical Characteristics
Table 3.1. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
VRST1
3.0
3.6
V
Digital Supply RAM Data
Retention Voltage
—
1.5
—
V
SYSCLK (System Clock)
(Note 2)
0
—
25
MHz
TSYSH (SYSCLK High Time)
18
—
—
ns
TSYSL (SYSCLK Low Time)
18
—
—
ns
Specified Operating 
Temperature Range
–40
—
+85
°C
Digital Supply Voltage
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD (Note 3)
IDD Supply Sensitivity (Note 3)
IDD Frequency Sensitivity
(Note 3, Note 4)
32
VDD = 3.6 V, F = 25 MHz
—
10.7
11.7
mA
VDD = 3.0 V, F = 25 MHz
—
7.8
8.3
mA
VDD = 3.0 V, F = 1 MHz
—
0.38
—
mA
VDD = 3.0 V, F = 80 kHz
—
31
—
µA
F = 25 MHz
—
65
—
%/V
F = 1 MHz
—
61
—
%/V
VDD = 3.0 V, F < 15 MHz, T = 25 °C
—
0.38
—
mA/MHz
VDD = 3.0 V, F > 15 MHz, T = 25 °C
—
0.21
—
mA/MHz
VDD = 3.6 V, F < 15 MHz, T = 25 °C
—
0.53
—
mA/MHz
VDD = 3.6 V, F > 15 MHz, T = 25 °C
—
0.27
—
mA/MHz
Rev. 1.7
C8051F330/1/2/3/4/5
Table 3.1. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD (Note 3)
IDD Supply Sensitivity (Note 3)
IDD Frequency Sensitivity
(Note 3, Note 5)
Digital Supply Current
(Stop Mode, shutdown)
VDD = 3.6 V, F = 25 MHz
—
4.8
5.2
mA
VDD = 3.0 V, F = 25 MHz
—
3.8
4.1
mA
VDD = 3.0 V, F = 1 MHz
—
0.20
—
mA
VDD = 3.0 V, F = 80 kHz
—
16
—
µA
F = 25 MHz
—
43
—
%/V
F = 1 MHz
—
55
—
%/V
VDD = 3.0 V, F < 1 MHz, T = 25 °C
—
0.20
—
mA/MHz
VDD = 3.0 V, F > 1 MHz, T = 25 °C
—
0.15
—
mA/MHz
VDD = 3.6 V, F < 1 MHz, T = 25 °C
—
0.24
—
mA/MHz
VDD = 3.6 V, F > 1 MHz, T = 25 °C
—
0.19
—
mA/MHz
Oscillator not running,
VDD Monitor Disabled
—
< 0.1
—
µA
Notes:
1. Given in Table 10.1 on page 102.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data; Not production tested.
4. IDD can be estimated for frequencies <= 15 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate IDD for >15 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency
sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 7.8 mA - (25 MHz 20 MHz) * 0.21 mA/MHz = 6.75 mA.
5. Idle IDD can be estimated for frequencies <= 1 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency
sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 4.8 mA - (25 MHz 5 MHz) * 0.15 mA/MHz = 1.8 mA.
Other electrical characteristics tables are found in the data sheet section corresponding to the associated
peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page
indicated in Table 3.2.
Rev. 1.7
33
C8051F330/1/2/3/4/5
Table 3.2. Index to Electrical Characteristics Tables
Peripheral Electrical Characteristics
Page No.
ADC0 Electrical Characteristics
55
IDAC Electrical Characteristics
60
Voltage Reference Electrical Characteristics
63
Comparator Electrical Characteristics
70
Reset Electrical Characteristics
102
Flash Electrical Characteristics
104
Internal Oscillator Electrical Characteristics
122
Port I/O DC Electrical Characteristics
134
34
Rev. 1.7
C8051F330/1/2/3/4/5
4.
Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5
Name
Pin
Pin
‘F330/1/2/
’F330-GP
3/4/5-GM
Type
Description
VDD
3
6
Power Supply Voltage.
GND
2
5
Ground.
RST/
4
7
C2CK
P2.0/
5
8
C2D
P0.0/
1
4
VREF
P0.1
20
3
D I/O
Clock signal for the C2 Debug Interface.
D I/O
Port 3.0. See Section 14 for a complete description.
D I/O
Bi-directional data signal for the C2 Debug Interface.
D I/O or Port 0.0. See Section 14 for a complete description.
A In
19
2
1
XTAL2
IDA0 Output. See Section 6 for a complete description.
D I/O or Port 0.2. See Section 14 for a complete description.
A In
A In
18
External VREF input. See Section 7 for a complete description.
D I/O or Port 0.1. See Section 14 for a complete description.
A In
AOut
XTAL1
P0.3/
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
A In
IDA0
P0.2/
D I/O
External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Section 13 for a complete description.
D I/O or Port 0.3. See Section 14 for a complete description.
A In
A I/O or External Clock Output. For an external crystal or resonator,
this pin is the excitation driver. This pin is the external clock
D In
input for CMOS, capacitor, or RC oscillator configurations.
See Section 13 for a complete description.
P0.4
17
20
D I/O or Port 0.4. See Section 14 for a complete description.
A In
P0.5
16
19
D I/O or Port 0.5. See Section 14 for a complete description.
A In
Rev. 1.7
35
C8051F330/1/2/3/4/5
Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5 (Continued)
Name
P0.6/
Pin
Pin
‘F330/1/2/
’F330-GP
3/4/5-GM
15
18
CNVSTR
36
Type
Description
D I/O or Port 0.6. See Section 14 for a complete description.
A In
D In
ADC0 External Convert Start or IDA0 Update Source Input.
See Section 5 and Section 6 for a complete description.
P0.7
14
17
D I/O or Port 0.7. See Section 14 for a complete description.
A In
P1.0
13
16
D I/O or Port 1.0. See Section 14 for a complete description.
A In
P1.1
12
15
D I/O or Port 1.1. See Section 14 for a complete description.
A In
P1.2
11
14
D I/O or Port 1.2. See Section 14 for a complete description.
A In
P1.3
10
13
D I/O or Port 1.3. See Section 14 for a complete description.
A In
P1.4
9
12
D I/O or Port 1.4. See Section 14 for a complete description.
A In
P1.5
8
11
D I/O or Port 1.5. See Section 14 for a complete description.
A In
P1.6
7
10
D I/O or Port 1.6. See Section 14 for a complete description.
A In
P1.7
6
9
D I/O or Port 1.7. See Section 14 for a complete description.
A In
Rev. 1.7
P0.1
P0.2
P0.3
P0.4
P0.5
20
19
18
17
16
C8051F330/1/2/3/4/5
P0.0
1
15
P0.6
GND
2
14
P0.7
VDD
3
13
P1.0
/RST/C2CK
4
12
P1.1
P2.0/C2D
5
11
P1.2
C8051F330/1/2/3/4/5-GM
Top View
6
7
8
9
10
P1.7
P1.6
P1.5
P1.4
P1.3
GND
Figure 4.1. QFN-20 Pinout Diagram (Top View)
Rev. 1.7
37
C8051F330/1/2/3/4/5
Figure 4.2. QFN-20 Package Drawing
Table 4.2. QFN-20 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
A1
b
D
D2
e
E
E2
0.80
0.00
0.18
0.90
0.02
0.23
4.00 BSC.
2.15
0.50 BSC.
4.00 BSC.
2.15
1.00
0.05
0.30
L
L1
aaa
bbb
ddd
eee
Z
Y
0.45
0.00
—
—
—
—
—
—
0.55
—
—
—
—
—
0.43
0.18
0.65
0.15
0.15
0.10
0.05
0.08
—
—
2.00
2.00
2.25
2.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small
Body Components.
38
Rev. 1.7
C8051F330/1/2/3/4/5
Figure 4.3. QFN-20 Recommended PCB Land Pattern
Table 4.3. QFN-20 PCB Land Pattern Dimesions
Dimension
C1
C2
E
X1
Min
Max
Dimension
Min
Max
X2
Y1
Y2
2.15
0.90
2.15
2.25
1.00
2.25
3.70
3.70
0.50
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 0.95 mm openings on a 1.1 mm pitch should be used for the center pad to
assure the proper paste volume (71% Paste Coverage).
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.7
39
C8051F330/1/2/3/4/5
5.
10-Bit ADC (ADC0, C8051F330/2/4 only)
The ADC0 subsystem for the C8051F330/2/4 consists of two analog multiplexers (referred to collectively
as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes,
and window detector are all configurable under software control via the Special Function Registers shown
in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure Ports0-1, the Temperature Sensor output, or VDD with respect to Ports0-1 or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The
ADC0 subsystem is in low power shutdown when this bit is logic 0.
P0.0
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0INT
AD0BUSY
AD0EN
VDD
P1.7
Start
Conversion
10-Bit
SAR
P0.0
(+)
P1.7
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
011
100
Timer 1 Overflow
CNVSTR Input
101
Timer 3 Overflow
ADC0H
ADC
(-)
18-to-1
AMUX
SYSCLK
P0.7
P1.0
ADC0L
VDD
000
001
010
REF
Temp
Sensor
AD0TM
AMX0P0
ADC0CN
AMX0P1
AMX0P2
18-to-1
AMUX
AMX0P3
P0.7
P1.0
AMX0P4
AMX0P
AD0WINT
VREF
AD0SC0
AD0LJST
AD0SC1
AD0SC2
AD0SC3
AMX0N0
AMX0N1
AMX0N2
AMX0N3
AMX0N4
AMX0N
AD0SC4
GND
ADC0CF
32
ADC0LTH
ADC0LTL
Window
Compare
Logic
ADC0GTH ADC0GTL
Figure 5.1. ADC0 Functional Block Diagram
5.1.
Analog Multiplexer
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: Ports0-1, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be selected as the negative input: Ports0-1, VREF, or GND. When GND is selected as the
negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR
Definition 5.1 and SFR Definition 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST.
When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are
Rev. 1.7
41
C8051F330/1/2/3/4/5
measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and leftjustified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
Input Voltage
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
0x03FF
0x0200
0x0100
0x0000
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0xFFC0
0x8000
0x4000
0x0000
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Input Voltage
VREF x 511/512
VREF x 256/512
0
–VREF x 256/512
–VREF
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
0x01FF
0x0100
0x0000
0xFF00
0xFE00
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0x7FC0
0x4000
0x0000
0xC000
0x8000
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1). To force the Crossbar to skip a Port
pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1). See Section “14. Port Input/Output”
on page 123 for more Port I/O configuration details.
5.2.
Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the
positive ADC input when the temperature sensor is selected by bits AMX0P4–0 in register AMX0P.
42
Rev. 1.7
C8051F330/1/2/3/4/5
(Volts)
1.000
0.900
0.800
VTEMP = 2.86(TEMPC) + 776 mV
0.700
0.600
0.500
-50
0
50
100
(Celsius)
Figure 5.2. Typical Temperature Sensor Transfer Function
5.3.
Modes of Operation
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC
+ 1) for 0  AD0SC 31).
Rev. 1.7
43
C8051F330/1/2/3/4/5
5.3.1. Starting a Conversion
A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following:
1.
2.
3.
4.
5.
6.
Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
A Timer 0 overflow (i.e., timed continuous conversions)
A Timer 2 overflow
A Timer 1 overflow
A rising edge on the CNVSTR input signal (pin P0.6)
A Timer 3 overflow
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See Section “18. Timers” on page 177 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “14. Port
Input/Output” on page 123 for details on Port I/O configuration.
44
Rev. 1.7
C8051F330/1/2/3/4/5
5.3.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 5.1. The AD0TM bit in register ADC0CN controls
the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a
conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold
mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-ofconversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode,
ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see
Figure 5.3). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep
modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due
to the settling time requirements described in Section “5.3.3. Settling Time Requirements” on page 46.
A. ADC0 Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=100)
1
2
3
4
5
6
7
8
9
10 11
SAR Clocks
AD0TM=1
AD0TM=0
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
Low Power
or Convert
Track
Track or Convert
Convert
Low Power
Mode
Convert
Track
B. ADC0 Timing for Internal Trigger Source
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SAR Clocks
AD0TM=1
Low Power
or Convert
Track
1
2
3
Convert
4
5
6
7
8
9
Low Power Mode
10 11
SAR Clocks
AD0TM=0
Track or
Convert
Convert
Track
Figure 5.3. 10-Bit ADC Track and Conversion Example Timing
Rev. 1.7
45
C8051F330/1/2/3/4/5
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum
tracking time is required before an accurate conversion can be performed. This tracking time is determined
by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements.
Figure 5.4 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature
Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum
settling time requirements.
n
2
t = ln  -------  R TOTAL C SAMPLE
 SA
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Differential Mode
Single-Ended Mode
MUX Select
MUX Select
Px.x
Px.x
RMUX = 5k
RMUX = 5k
CSAMPLE = 5pF
CSAMPLE = 5pF
RCInput= RMUX * CSAMPLE
RCInput= RMUX * CSAMPLE
CSAMPLE = 5pF
Px.x
RMUX = 5k
MUX Select
Figure 5.4. ADC0 Equivalent Input Circuits
46
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select
R
R
R
R/W
R/W
R/W
R/W
R/W
-
-
-
AMX0P4
AMX0P3
AMX0P2
AMX0P1
AMX0P0
Reset Value
00011111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBB
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection
AMX0P4–0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010 – 11111
ADC0 Positive Input
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Temp Sensor
VDD
no input selected
Rev. 1.7
47
C8051F330/1/2/3/4/5
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
AMX0N4
AMX0N3
AMX0N2
AMX0N1
AMX0N0
00011111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBA
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
AMX0N4–0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010–11111
48
ADC0 Negative Input
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VREF
GND (ADC in Single-Ended Mode)
no input selected
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 5.3. ADC0CF: ADC0 Configuration
R/W
R/W
R/W
R/W
AD0SC4
AD0SC3
AD0SC2
AD0SC1
Bit7
Bit6
Bit5
Bit4
R/W
R/W
AD0SC0 AD0LJST
Bit3
Bit2
R
R
Reset Value
-
-
11111000
Bit1
Bit0
SFR Address:
0xBC
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in Table 5.1.
AD0SC = SYSCLK
---------------------- – 1
CLK SAR
Bit2:
AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bits1–0: UNUSED. Read = 00b; Write = don’t care.
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xBE
Bits7–0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1–0 are the upper 2 bits of the
10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word.
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBD
Bits7–0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always
read ‘0’.
Rev. 1.7
49
C8051F330/1/2/3/4/5
SFR Definition 5.6. ADC0CN: ADC0 Control
R/W
R/W
AD0EN
AD0TM
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Bit0
(bit addressable)
Bit7:
Reset Value
AD0CM0 00000000
SFR Address:
0xE8
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6:
AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2–0 bits (see below).
Bit5:
AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4:
AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2–0 = 000b
Bit3:
AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising
CNVSTR edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.
11x: Reserved.
50
Rev. 1.7
C8051F330/1/2/3/4/5
5.4.
Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
11111111
0xC4
Bits7–0: High byte of ADC0 Greater-Than Data Word
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
11111111
0xC3
Bits7–0: Low byte of ADC0 Greater-Than Data Word
Rev. 1.7
51
C8051F330/1/2/3/4/5
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC6
Bits7–0: High byte of ADC0 Less-Than Data Word
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xC5
Bits7–0: Low byte of ADC0 Less-Than Data Word
52
Rev. 1.7
C8051F330/1/2/3/4/5
5.4.1. Window Detector In Single-Ended Mode
Figure 5.5 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode,
the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a
10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0
conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.6 shows an example using left-justified data with the same comparison values.
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
Input Voltage
(Px.x - GND)
0x03FF
VREF x (1023/1024)
0x03FF
AD0WINT
not affected
AD0WINT=1
0x0081
VREF x (128/1024)
0x0080
0x0081
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x007F
0x0080
0x007F
AD0WINT=1
VREF x (64/1024)
0x0041
0x0040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x003F
0x0041
0x0040
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x003F
AD0WINT=1
AD0WINT
not affected
0
0x0000
0
0x0000
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
Input Voltage
(Px.x - GND)
0xFFC0
VREF x (1023/1024)
0xFFC0
AD0WINT
not affected
AD0WINT=1
0x2040
VREF x (128/1024)
0x2000
0x2040
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x1FC0
0x2000
0x1FC0
AD0WINT=1
0x1040
VREF x (64/1024)
0x1000
0x1040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x0FC0
0x1000
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x0FC0
AD0WINT=1
AD0WINT
not affected
0
ADC0GTH:ADC0GTL
0x0000
0
0x0000
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data
Rev. 1.7
53
C8051F330/1/2/3/4/5
5.4.2. Window Detector In Differential Mode
Figure 5.7 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (–1d). In differential mode, the
measurable voltage between the input pins is between –VREF and VREF x (511/512). Output codes are
represented as 10-bit 2s complement signed integers. In the left example, an AD0WINT interrupt will be
generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by
ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (–1d) < ADC0H:ADC0L < 0x0040 (64d)). In the
right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range
defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (–1d) or
ADC0H:ADC0L > 0x0040 (+64d)). Figure 5.8 shows an example using left-justified data with the same
comparison values.
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
Input Voltage
(Px.x - Px.x)
0x01FF
VREF x (511/512)
0x01FF
AD0WINT
not affected
AD0WINT=1
0x0041
VREF x (64/512)
0x0040
0x0041
ADC0LTH:ADC0LTL
VREF x (64/512)
0x003F
0x0040
0x003F
AD0WINT=1
0x0000
VREF x (-1/512)
0xFFFF
0x0000
ADC0GTH:ADC0GTL
VREF x (-1/512)
0xFFFE
0xFFFF
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0xFFFE
AD0WINT=1
AD0WINT
not affected
-VREF
0x0200
-VREF
0x0200
Figure 5.7. ADC Window Compare Example: Right-Justified Differential Data
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
Input Voltage
(Px.x - Px.y)
0x7FC0
VREF x (511/512)
0x7FC0
AD0WINT
not affected
AD0WINT=1
0x1040
VREF x (64/512)
0x1000
0x1040
ADC0LTH:ADC0LTL
VREF x (64/512)
0x0FC0
0x1000
0x0FC0
AD0WINT=1
0x0000
VREF x (-1/512)
0xFFC0
0x0000
ADC0GTH:ADC0GTL
VREF x (-1/512)
0xFF80
0xFFC0
AD0WINT
not affected
ADC0LTH:ADC0LTL
0xFF80
AD0WINT=1
AD0WINT
not affected
-VREF
ADC0GTH:ADC0GTL
0x8000
-VREF
0x8000
Figure 5.8. ADC Window Compare Example: Left-Justified Differential Data
54
Rev. 1.7
C8051F330/1/2/3/4/5
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified.
Parameter
Conditions
DC Accuracy
Min
Resolution
Typ
Max
10
Integral Nonlinearity
Units
bits
—
±0.5
±1
LSB
—
±0.5
±1
LSB
Offset Error
-15
0
15
LSB
Full Scale Error
-15
–1
15
LSB
Offset Temperature Coefficient
—
10
—
ppm/°C
Differential Nonlinearity
Guaranteed Monotonic
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
53
55.5
—
dB
—
–67
—
dB
—
78
—
dB
SAR Conversion Clock
—
—
3
MHz
Conversion Time in SAR Clocks
10
—
—
clocks
Track/Hold Acquisition Time
300
—
—
ns
—
—
200
ksps
0
–VREF
—
VREF
VREF
V
V
Absolute Pin Voltage with respect
Single Ended or Differential
to GND
0
—
VDD
V
Input Capacitance
—
5
—
pF
Linearity
—
± 0.2
—
°C
Absolute Accuracy
—
±3
—
°C
Gain
—
2.86
—
mV/°C
Gain Error*
—
±33.5
—
µV/°C
—
776
—
mV
—
±8.51
—
mV
—
400
900
µA
—
±0.3
—
mV/V
Total Harmonic Distortion
Up to the 5th harmonic
Spurious-Free Dynamic Range
Conversion Rate
Throughput Rate
Analog Inputs
ADC Input Voltage Range
Single Ended (AIN+ – GND)
Differential (AIN+ – AIN–)
Temperature Sensor
Offset
Temp = 0 °C
Offset Error*
Power Specifications
Power Supply Current 
(VDD supplied to ADC0)
Operating Mode, 200 ksps
Power Supply Rejection
*Note: Represents one standard deviation from the mean.
Rev. 1.7
55
C8051F330/1/2/3/4/5
56
Rev. 1.7
C8051F330/1/2/3/4/5
6. 10-Bit Current Mode DAC (IDA0, C8051F330 only)
The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum
current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA.
The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see SFR Definition 6.1).
When IDA0EN is set to ‘0’, the IDAC port pin (P0.1) behaves as a normal GPIO pin. When IDA0EN is set
to ‘1’, the digital output drivers and weak pullup for the IDAC pin are automatically disabled, and the pin is
connected to the IDAC output. An internal bandgap bias generator is used to generate a reference current
for the IDAC whenever it is enabled. When using the IDAC, bit 1 in the P0SKIP register should be set to ‘1’,
to force the Crossbar to skip the IDAC pin.
6.1.
IDA0 Output Scheduling
IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output
updates on a write to IDA0H, on a Timer overflow, or on an external pin edge.
6.1.1. Update Output On-Demand
CNVSTR
Timer 3
Timer 2
Timer 1
Timer 0
IDA0H
IDA0EN
IDA0CM2
IDA0CM1
IDA0CM0
IDA0H
IDA0OMD1
IDA0OMD0
8
IDA0L
2
10
IDA0
Latch
IDA0CN
In its default mode (IDA0CN.[6:4] = ‘111’) the IDA0 output is updated “on-demand” on a write to the highbyte of the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode,
and have no effect on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the
IDAC data registers, the 10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) data registers. Data is latched into IDA0 after a write to the IDA0H register, so the write sequence should be
IDA0L followed by IDA0H if the full 10-bit resolution is required. The IDAC can be used in 8-bit mode by
initializing IDA0L to the desired value (typically 0x00), and writing data to only IDA0H (see Section 6.2 for
information on the format of the 10-bit IDAC data word within the 16-bit SFR space).
IDA0
Figure 6.1. IDA0 Functional Block Diagram
Rev. 1.7
57
C8051F330/1/2/3/4/5
6.1.2. Update Output Based on Timer Overflow
Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow independently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event.
This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling
rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the
IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘000’, ‘001’, ‘010’ or ‘011’, writes to both
IDAC data registers (IDA0L and IDA0H) are held until an associated Timer overflow event (Timer 0,
Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDA0H:IDA0L contents are copied to
the IDAC input latches, allowing the IDAC output to change to the new value.
6.1.3. Update Output Based on CNVSTR Edge
The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the
external CNVSTR signal. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘100’, ‘101’, or ‘110’, writes to
both IDAC data registers (IDA0L and IDA0H) are held until an edge occurs on the CNVSTR input pin. The
particular setting of the IDA0CM bits determines whether IDAC outputs are updated on rising, falling, or
both edges of CNVSTR. When a corresponding edge occurs, the IDA0H:IDA0L contents are copied to the
IDAC input latches, allowing the IDAC output to change to the new value.
6.2.
IDAC Output Mapping
The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC
output word are mapped to bits 7–0 of the IDA0H register, and the two LSBs of the IDAC output word are
mapped to bits 7 and 6 of the IDA0L register. The data word mapping for the IDAC is shown in Figure 6.2.
IDA0H
D9
D8
D7
Input Data Word
(D9–D0)
0x000
0x001
0x200
0x3FF
D6
D5
IDA0L
D4
D3
Output Current
IDA0OMD[1:0] = ‘1x’
0 mA
1/1024 x 2 mA
512/1024 x 2 mA
1023/1024 x 2 mA
D2
D1
D0
Output Current
IDA0OMD[1:0] = ‘01’
0 mA
1/1024 x 1 mA
512/1024 x 1 mA
1023/1024 x 1 mA
Output Current
IDA0OMD[1:0] = ‘00’
0 mA
1/1024 x 0.5 mA
512/1024 x 0.5 mA
1023/1024 x 0.5 mA
Figure 6.2. IDA0 Data Word Mapping
The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default,
the IDAC is set to a full-scale output current of 2 mA. The IDA0OMD bits can also be configured to provide
full-scale output currents of 1 mA or 0.5 mA, as shown in SFR Definition 6.1.
58
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 6.1. IDA0CN: IDA0 Control
R/W
R/W
IDA0EN
Bit7
R/W
R/W
R
-
-
Bit4
Bit3
Bit2
IDA0CM
Bit6
Bit5
R
R/W
R/W
IDA0OMD
Bit1
Bit0
Reset Value
01110010
SFR Address:
0xB9
Bit 7:
IDA0EN: IDA0 Enable.
0: IDA0 Disabled.
1: IDA0 Enabled.
Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select bits.
000: DAC output updates on Timer 0 overflow.
001: DAC output updates on Timer 1 overflow.
010: DAC output updates on Timer 2 overflow.
011: DAC output updates on Timer 3 overflow.
100: DAC output updates on rising edge of CNVSTR.
101: DAC output updates on falling edge of CNVSTR.
110: DAC output updates on any edge of CNVSTR.
111: DAC output updates on write to IDA0H.
Bits 3–2: Unused. Read = 00b. Write = don’t care.
Bits 1:0: IDA0OMD[1:0]: IDA0 Output Mode Select bits.
00: 0.5 mA full-scale output current.
01: 1.0 mA full-scale output current.
1x: 2.0 mA full-scale output current.
SFR Definition 6.2. IDA0H: IDA0 Data Word MSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x97
Bits 7–0: IDA0 Data Word High-Order Bits.
Bits 7–0 are the most-significant bits of the 10-bit IDA0 Data Word.
Rev. 1.7
59
C8051F330/1/2/3/4/5
SFR Definition 6.3. IDA0L: IDA0 Data Word LSB
R/W
Bit7
R/W
Bit6
R
R
R
R
R
R
Reset Value
—
—
—
—
—
—
00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x96
Bits 7–6: IDA0 Data Word Low-Order Bits.
Lower 2 bits of the 10-bit Data Word.
Bits 5–0: UNUSED. Read = 000000b, Write = don’t care.
Table 6.1. IDAC Electrical Characteristics
–40 to +85 °C, VDD = 3.0 V Full-scale output current set to 2 mA unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Static Performance
Resolution
10
Integral Nonlinearity
bits
—
±0.5
—
LSB
—
±0.5
±1
LSB
—
—
VDD – 1.2
V
—
1
—
nA/rtHz
—
0
—
LSB
—
0
—
LSB
Full Scale Error Tempco
—
30
—
ppm/°C
VDD Power Supply 
Rejection Ratio
—
52
—
dB
Output Capacitance
—
2
—
pF
Output Settling Time to 1/2
IDA0H:L = 0x3FF to 0x000
LSB
—
5
—
µs
Startup Time
—
5
—
µs
—
—
±1
±1
—
—
%
%
—
—
—
2100
1100
600
—
—
—
µA
µA
µA
Differential Nonlinearity
Guaranteed Monotonic
Output Compliance Range
Output Noise
IOUT = 2 mA; RLOAD = 100 
Offset Error
Full Scale Error
2 mA Full Scale Output 
Current
Dynamic Performance
Gain Variation
1 mA Full Scale Output Current
0.5 mA Full Scale Output Current
Power Consumption
2 mA Full Scale Output Current
Power Supply Current (VDD
1 mA Full Scale Output Current
supplied to IDAC)
0.5 mA Full Scale Output Current
60
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C8051F330/1/2/3/4/5
7.
Voltage Reference (C8051F330/2/4 only)
The Voltage reference MUX on the C8051F330/2/4 devices is configurable to use an externally connected
voltage reference, the internal reference voltage generator, or the VDD power supply voltage (see
Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For
an external source or the internal reference, REFSL should be set to ‘0’. To use VDD as the reference
source, REFSL should be set to ‘1’.
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
internal oscillators, and Current DAC. This bias is enabled when any of the aforementioned peripherals are
enabled. The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register
REF0CN; see SFR Definition 7.1 for REF0CN register details. The electrical specifications for the voltage
reference circuit are given in Table 7.1.
The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference
generator and a gain-of-two output buffer amplifier. The internal voltage reference can be driven out on the
VREF pin by setting the REFBE bit in register REF0CN to a ‘1’ (see SFR Definition 7.1). The maximum
load seen by the VREF pin must be less than 200 µA to GND. When using the internal voltage reference,
bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the internal reference is not used, the REFBE bit should be cleared to ‘0’. Electrical specifications for the internal voltage
reference are given in Table 7.1.
Important Note about the VREF Pin: Port pin P0.0 is used as the external VREF input and as an output
for the internal VREF. When using either an external voltage reference or the internal reference circuitry,
P0.0 should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P0.0 as an
analog pin, set to ‘0’ Bit0 in register P0MDIN. To configure the Crossbar to skip P0.0, set Bit 0 in register
P0SKIP to ‘1’. Refer to Section “14. Port Input/Output” on page 123 for complete Port I/O configuration
details. The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the
temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the
sensor result in meaningless data.
REFSL
TEMPE
BIASE
REFBE
REF0CN
EN
VDD
To ADC, IDAC,
Internal Oscillators
IOSCE
N
External
Voltage
Reference
Circuit
R1
Bias Generator
EN
VREF
Temp Sensor
To Analog Mux
0
VREF
(to ADC)
GND
VDD
1
REFBE
4.7F
+
0.1F
EN
Internal
Reference
Recommended Bypass
Capacitors
Figure 7.1. Voltage Reference Functional Block Diagram
Rev. 1.7
61
C8051F330/1/2/3/4/5
SFR Definition 7.1. REF0CN: Reference Control
R
R
R
R
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
REFSL
TEMPE
BIASE
REFBE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD1
Bits7–4: UNUSED. Read = 0000b; Write = don’t care.
Bit3:
REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
Bit2:
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1:
BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0:
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.
62
Rev. 1.7
C8051F330/1/2/3/4/5
Table 7.1. Voltage Reference Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
2.38
2.44
2.50
V
VREF Short-Circuit Current
—
—
10
mA
VREF Temperature 
Coefficient
—
15
—
ppm/°C
Internal Reference (REFBE = 1)
Output Voltage
25 °C ambient
Load Regulation
Load = 0 to 200 µA to AGND
—
0.5
—
ppm/µA
VREF Turn-on Time 1
4.7 µF tantalum, 0.1 µF ceramic
bypass
—
2
—
ms
VREF Turn-on Time 2
0.1 µF ceramic bypass
—
20
—
µs
VREF Turn-on Time 3
no bypass cap
—
10
—
µs
—
140
—
ppm/V
0
—
VDD
V
—
12
—
µA
Power Supply Rejection
External Reference (REFBE = 0)
Input Voltage Range
Input Current
Sample Rate = 200 ksps; VREF =
3.0 V
Power Specifications
ADC Bias Generator
BIASE = ‘1’ or AD0EN = ‘1’ or
IOSCEN = ‘1’
—
100
—
µA
Reference Bias Generator
REFBE = ‘1’ or TEMPE = ‘1’ or
IDA0EN = ‘1’
—
40
—
µA
Rev. 1.7
63
C8051F330/1/2/3/4/5
64
Rev. 1.7
C8051F330/1/2/3/4/5
8.
Comparator0
C8051F330/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown
in Figure 8.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when in when the system
clock is not active. This allows the Comparator to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull
(see Section “14.2. Port I/O Initialization” on page 127). Comparator0 may also be used as a reset
source (see Section “10.5. Comparator0 Reset” on page 100).
CPT0CN
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.2). The CMX0P1–
CMX0P0 bits select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0
negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs
should be configured as analog inputs in their associated Port configuration register, and configured to be
skipped by the Crossbar (for details on Port configuration, see Section “14.3. General Purpose Port I/O”
on page 129).
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
VDD
CP0HYN0
P0.0
P0.2
P0.4
P0.6
CP0 +
CP0
+
P1.0
D
-
P1.2
SET
CLR
Q
D
Q
SET
CLR
Q
Q
Crossbar
P1.4
(SYNCHRONIZER)
GND
P1.6
CP0A
Reset
Decision
Tree
P0.1
CP0RIF
P0.3
CP0FIF
P0.5
P0.7
0
CP0EN
EA
1
0
0
0
1
1
CP0
Interrupt
1
CP0 -
P1.1
P1.3
P1.5
P1.7
CPT0MD
CPT0MX
CMX0N3
CMX0N2
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0RIE
CP0FIE
CP0MD1
CP0MD0
Figure 8.1. Comparator0 Functional Block Diagram
Rev. 1.7
65
C8051F330/1/2/3/4/5
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and its supply current falls to less than 100 nA. See Section “14.1. Priority Crossbar Decoder” on
page 125 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator
electrical specifications are given in Table 8.1.
The Comparator response time may be configured in software via the CPT0MD register (see SFR Definition 8.3). Selecting a longer response time reduces the Comparator supply current. See Table 8.1 for complete timing and power consumption specifications.
VIN+
VIN-
CP0+
CP0-
+
CP0
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Positive Hysteresis
Disabled
Maximum
Negative Hysteresis
Maximum
Positive Hysteresis
Figure 8.2. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and
negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 8.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 8.2, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “8.3. Interrupt Handler” on page 58). The CP0FIF flag is set to
66
Rev. 1.7
C8051F330/1/2/3/4/5
logic 1 upon a Comparator falling-edge occurrence, and the CP0RIF flag is set to logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator
rising-edge interrupt mask is enabled by setting CP0RIE to a logic 1. The Comparator0 falling-edge interrupt mask is enabled by setting CP0FIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Comparator is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed. This Power Up Time is specified in Table 8.1 on page 70.
SFR Definition 8.1. CPT0CN: Comparator0 Control
R/W
R
R/W
R/W
CP0EN
CP0OUT
CP0RIF
CP0FIF
Bit7
Bit6
Bit5
Bit4
R/W
R/W
R/W
R/W
Reset Value
CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x9B
Bit7:
CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6:
CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5:
CP0RIF: Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Bit4:
CP0FIF: Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.7
67
C8051F330/1/2/3/4/5
SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection
R/W
R/W
R/W
R/W
R/W
CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
R/W
CMX0P2
CMX0P1
CMX0P0
Reset Value
11111111
Bit2
Bit1
Bit0
SFR Address:
0x9F
Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
CMX0N3 CMX0N2 CMX0N1 CMX0N0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
x
x
x
Negative Input
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
None
Bits3–0: CMX0P3–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
CMX0P3 CMX0P2 CMX0P1 CMX0P0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
x
x
x
68
Rev. 1.7
Positive Input
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
None
C8051F330/1/2/3/4/5
SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection
R
R
R/W
R/W
R
R
-
-
CP0RIE
CP0FIE
-
-
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
CP0MD1 CP0MD0 00000010
Bit1
Bit0
SFR Address:
0x9D
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bit5:
CP0RIE: Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
Bit4:
CP0FIE: Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
Mode
CP0MD1
CP0MD0
0
1
2
3
0
0
1
1
0
1
0
1
CP0 Response Time
(TYP)
100 ns
175 ns
320 ns
1050 ns
Rev. 1.7
69
C8051F330/1/2/3/4/5
Table 8.1. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Response Time:
Mode 0, Vcm* = 1.5 V
CP0+ – CP0– = 100 mV
—
100
—
ns
CP0+ – CP0– = –100 mV
—
250
—
ns
Response Time:
Mode 1, Vcm* = 1.5 V
CP0+ – CP0– = 100 mV
—
175
—
ns
CP0+ – CP0– = –100 mV
—
500
—
ns
Response Time:
Mode 2, Vcm* = 1.5 V
CP0+ – CP0– = 100 mV
—
320
—
ns
CP0+ – CP0– = –100 mV
—
1100
—
ns
Response Time:
Mode 3, Vcm* = 1.5 V
CP0+ – CP0– = 100 mV
—
1050
—
ns
CP0+ – CP0– = –100 mV
—
5200
—
ns
—
1.5
4
mV/V
Common-Mode Rejection Ratio
Positive Hysteresis 1
CP0HYP1–0 = 00
—
0
1
mV
Positive Hysteresis 2
CP0HYP1–0 = 01
2
5
10
mV
Positive Hysteresis 3
CP0HYP1–0 = 10
7
10
20
mV
Positive Hysteresis 4
CP0HYP1–0 = 11
15
20
30
mV
Negative Hysteresis 1
CP0HYN1–0 = 00
0
1
mV
Negative Hysteresis 2
CP0HYN1–0 = 01
2
5
10
mV
Negative Hysteresis 3
CP0HYN1–0 = 10
7
10
20
mV
Negative Hysteresis 4
CP0HYN1–0 = 11
15
20
30
mV
–0.25
—
VDD + 0.25
V
Input Capacitance
—
4
—
pF
Input Bias Current
—
0.001
—
nA
Input Offset Voltage
–5
—
+5
mV
Power Supply Rejection
—
0.1
—
mV/V
Power-up Time
—
10
—
µs
Mode 0
—
7.6
—
µA
Mode 1
—
3.2
—
µA
Mode 2
—
1.3
—
µA
Mode 3
—
0.4
—
µA
Inverting or Non-Inverting Input
Voltage Range
Power Supply
Supply Current at DC
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
70
Rev. 1.7
C8051F330/1/2/3/4/5
9.
CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in Section 18), an enhanced full-duplex UART (see description
in Section 16), an Enhanced SPI (see description in Section 17), 256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (Section 9.2.6), and 17 Port I/O (see description in Section 14). The CIP-51 also includes on-chip debug hardware (see description in Section 20), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
-
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
17 Port I/O
Extended Interrupt Handler
Reset Input
Power Management Modes
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
D8
D8
ACCUMULATOR
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
D8
D8
D8
ALU
SRAM
(256 X 8)
D8
DATA BUS
B REGISTER
D8
D8
D8
DATA BUS
DATA BUS
SFR_ADDRESS
BUFFER
D8
DATA POINTER
D8
D8
SFR
BUS
INTERFACE
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
DATA BUS
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
MEM_ADDRESS
D8
MEM_CONTROL
A16
MEMORY
INTERFACE
MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE
RESET
D8
CONTROL
LOGIC
SYSTEM_IRQs
CLOCK
D8
STOP
IDLE
POWER CONTROL
REGISTER
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
Figure 9.1. CIP-51 Block Diagram
Rev. 1.7
71
C8051F330/1/2/3/4/5
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-programmable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “20. C2 Interface” on page 209.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.
9.1.
Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
9.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F330/1/2/3/4/5
does not support off-chip data or program memory). In the CIP-51, the MOVX instruction can be used to
access on-chip XRAM or on-chip program memory space implemented as re-programmable Flash memory. The Flash access feature provides a mechanism for the CIP-51 to update program code and use the
72
Rev. 1.7
C8051F330/1/2/3/4/5
program memory space for non-volatile data storage. Refer to Section “11. Flash Memory” on page 103
for further details.
Table 9.1. CIP-51 Instruction Set Summary
Mnemonic
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
Description
Arithmetic Operations
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
Logical Operations
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Rev. 1.7
Bytes
Clock
Cycles
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
73
C8051F330/1/2/3/4/5
Table 9.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
CLR C
CLR bit
SETB C
SETB bit
74
Description
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
Data Transfer
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
Boolean Manipulation
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Rev. 1.7
Bytes
Clock
Cycles
2
2
3
1
1
1
1
1
1
1
2
2
3
1
1
1
1
1
1
1
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
1
2
1
2
1
2
1
2
C8051F330/1/2/3/4/5
Table 9.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Description
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Program Branching
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Rev. 1.7
Bytes
Clock
Cycles
1
2
2
2
2
2
2
2
2
2
3
3
3
1
2
2
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
2
3
1
1
2
3
2
1
2
2
3
3
3
4
5
5
3
4
3
3
2/3
2/3
3/4
3/4
3
3/4
3
4/5
2
3
1
2/3
3/4
1
75
C8051F330/1/2/3/4/5
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location
(0x00–0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
9.2.
Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 9.2
76
Rev. 1.7
C8051F330/1/2/3/4/5
C8051F330/1
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
0xFF
RESERVED
0x1E00
0x1DFF
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
8 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
0x0000
EXTERNAL DATA ADDRESS SPACE
C8051F332/3
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
Same 512 bytes as from
0x0000 to 0x01FF, wrapped
on 512-byte boundaries
0x0FFF
4 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0200
0x01FF
0x0000
XRAM - 512 Bytes
(accessable using MOVX
instruction)
0x0000
C8051F334/5
PROGRAM/DATA MEMORY
(FLASH)
0x7FF
2 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
Figure 9.2. Memory Map
9.2.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F330/1 implements 8 kB of this program
memory space as in-system, re-programmable Flash memory, organized in a contiguous block from
addresses 0x0000 to 0x1DFF. Addresses above 0x1DFF are reserved on the 8 kB devices. The
C8051F332/3 and C8051F334/5 implement, in contiguous blocks, 2 and 4 kB, from addresses 0x0000 to
0x07FF or 0x0000 to 0x0FFF, respectively. Addresses above 0x0800 and 0x1000 are reserved on the 2
and 4 kB devices, respectively.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX write instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to Section “11. Flash Memory” on page 103 for further details.
Rev. 1.7
77
C8051F330/1/2/3/4/5
9.2.2. Data Memory
The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting
of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51.
9.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 9.4). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
9.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
9.2.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
78
Rev. 1.7
C8051F330/1/2/3/4/5
9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 9.3, for a detailed description of each register.
Table 9.2. Special Function Register (SFR) Memory Map
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
SPI0CN
PCA0L
PCA0H PCA0CPL0 PCA0CPH0
B
P0MDIN
P1MDIN
EIP1
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
ACC
XBR0
XBR1
OSCLCN
IT01CF
EIE1
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
PSW
REF0CN
P0SKIP
P1SKIP
TMR2CN
TMR2RLL TMR2RLH
TMR2L
TMR2H
SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
IP
IDA0CN
AMX0N
AMX0P
ADC0CF
ADC0L
ADC0H
OSCXCN
OSCICN
OSCICL
FLSCL
IE
CLKSEL
EMI0CN
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT
SCON0
SBUF0
CPT0CN
CPT0MD
P1
TMR3CN TMR3RLL TMR3RLH
TMR3L
TMR3H
IDA0L
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P0
SP
DPL
DPH
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
(bit addressable)
Rev. 1.7
VDM0CN
RSTSRC
FLKEY
CPT0MX
IDA0H
PSCTL
PCON
7(F)
79
C8051F330/1/2/3/4/5
Table 9.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
Page
ACC
0xE0
Accumulator
85
ADC0CF
0xBC
ADC0 Configuration
49
ADC0CN
0xE8
ADC0 Control
50
ADC0GTH
0xC4
ADC0 Greater-Than Compare High
51
ADC0GTL
0xC3
ADC0 Greater-Than Compare Low
51
ADC0H
0xBE
ADC0 High
49
ADC0L
0xBD
ADC0 Low
49
ADC0LTH
0xC6
ADC0 Less-Than Compare Word High
52
ADC0LTL
0xC5
ADC0 Less-Than Compare Word Low
52
AMX0N
0xBA
AMUX0 Negative Channel Select
48
AMX0P
0xBB
AMUX0 Positive Channel Select
47
B
0xF0
B Register
85
CKCON
0x8E
Clock Control
183
CLKSEL
0xA9
Clock Select
121
CPT0CN
0x9B
Comparator0 Control
67
CPT0MD
0x9D
Comparator0 Mode Selection
69
CPT0MX
0x9F
Comparator0 MUX Selection
68
DPH
0x83
Data Pointer High
83
DPL
0x82
Data Pointer Low
83
EIE1
0xE6
Extended Interrupt Enable 1
91
EIP1
0xF6
Extended Interrupt Priority 1
92
EMI0CN
0xAA
External Memory Interface Control
111
FLKEY
0xB7
Flash Lock and Key
109
FLSCL
0xB6
Flash Scale
109
IDA0CN
0xB9
Current Mode DAC0 Control
59
IDA0H
0x97
Current Mode DAC0 High
59
IDA0L
0x96
Current Mode DAC0 Low
60
IE
0xA8
Interrupt Enable
89
IP
0xB8
Interrupt Priority
90
IT01CF
0xE4
INT0/INT1 Configuration
93
OSCICL
0xB3
Internal Oscillator Calibration
114
OSCICN
0xB2
Internal Oscillator Control
114
OSCLCN
0xE3
Low-Frequency Oscillator Control
115
80
Rev. 1.7
C8051F330/1/2/3/4/5
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
Page
OSCXCN
0xB1
External Oscillator Control
117
P0
0x80
Port 0 Latch
130
P0MDIN
0xF1
Port 0 Input Mode Configuration
130
P0MDOUT
0xA4
Port 0 Output Mode Configuration
131
P0SKIP
0xD4
Port 0 Skip
131
P1
0x90
Port 1 Latch
131
P1MDIN
0xF2
Port 1 Input Mode Configuration
132
P1MDOUT
0xA5
Port 1 Output Mode Configuration
132
P1SKIP
0xD5
Port 1 Skip
132
P2
0xA0
Port 2 Latch
133
P2MDOUT
0xA6
Port 2 Output Mode Configuration
133
PCA0CN
0xD8
PCA Control
205
PCA0CPH0
0xFC
PCA Capture 0 High
208
PCA0CPH1
0xEA
PCA Capture 1 High
208
PCA0CPH2
0xEC
PCA Capture 2 High
208
PCA0CPL0
0xFB
PCA Capture 0 Low
208
PCA0CPL1
0xE9
PCA Capture 1 Low
208
PCA0CPL2
0xEB
PCA Capture 2 Low
208
PCA0CPM0
0xDA
PCA Module 0 Mode Register
207
PCA0CPM1
0xDB
PCA Module 1 Mode Register
207
PCA0CPM2
0xDC
PCA Module 2 Mode Register
207
PCA0H
0xFA
PCA Counter High
208
PCA0L
0xF9
PCA Counter Low
208
PCA0MD
0xD9
PCA Mode
206
PCON
0x87
Power Control
95
PSCTL
0x8F
Program Store R/W Control
108
PSW
0xD0
Program Status Word
84
REF0CN
0xD1
Voltage Reference Control
62
RSTSRC
0xEF
Reset Source Configuration/Status
101
SBUF0
0x99
UART0 Data Buffer
159
SCON0
0x98
UART0 Control
158
SMB0CF
0xC1
SMBus Configuration
142
SMB0CN
0xC0
SMBus Control
144
SMB0DAT
0xC2
SMBus Data
146
Rev. 1.7
81
C8051F330/1/2/3/4/5
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
Page
SP
0x81
Stack Pointer
83
SPI0CFG
0xA1
SPI Configuration
170
SPI0CKR
0xA2
SPI Clock Rate Control
172
SPI0CN
0xF8
SPI Control
171
SPI0DAT
0xA3
SPI Data
172
TCON
0x88
Timer/Counter Control
181
TH0
0x8C
Timer/Counter 0 High
184
TH1
0x8D
Timer/Counter 1 High
184
TL0
0x8A
Timer/Counter 0 Low
184
TL1
0x8B
Timer/Counter 1 Low
184
TMOD
0x89
Timer/Counter Mode
182
TMR2CN
0xC8
Timer/Counter 2 Control
187
TMR2H
0xCD
Timer/Counter 2 High
188
TMR2L
0xCC
Timer/Counter 2 Low
188
TMR2RLH
0xCB
Timer/Counter 2 Reload High
188
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
188
TMR3CN
0x91
Timer/Counter 3Control
191
TMR3H
0x95
Timer/Counter 3 High
192
TMR3L
0x94
Timer/Counter 3Low
192
TMR3RLH
0x93
Timer/Counter 3 Reload High
192
TMR3RLL
0x92
Timer/Counter 3 Reload Low
192
VDM0CN
0xFF
VDD Monitor Control
99
XBR0
0xE1
Port I/O Crossbar Control 0
128
XBR1
0xE2
Port I/O Crossbar Control 1
129
82
Rev. 1.7
C8051F330/1/2/3/4/5
9.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
SFR Definition 9.1. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory or XRAM.
SFR Definition 9.2. DPH: Data Pointer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x83
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory or XRAM.
SFR Definition 9.3. SP: Stack Pointer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000111
0x81
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
Rev. 1.7
83
C8051F330/1/2/3/4/5
SFR Definition 9.4. PSW: Program Status Word
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset Value
CY
AC
F0
RS1
RS0
OV
F1
PARITY
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xD0
Bit7:
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6:
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
Bit5:
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
Bit2:
Bit1:
Bit0:
84
RS1
RS0
Register Bank
Address
0
0
0
0x00–0x07
0
1
1
0x08–0x0F
1
0
2
0x10–0x17
1
1
3
0x18–0x1F
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 9.5. ACC: Accumulator
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Reset Value
0xE0
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 9.6. B: B Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xF0
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
9.3.
Interrupt Handler
The CIP-51 includes an extended interrupt system supporting a total of 13 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interruptpending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears the EA bit should be immediately followed by an instruction that has two
or more opcode bytes. For example:
// in 'C':
EA = 0; // clear EA bit.
Rev. 1.7
85
C8051F330/1/2/3/4/5
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is
followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
9.3.1. MCU Interrupt Sources and Vectors
The MCUs support 13 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 9.4 on page 88. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
86
Rev. 1.7
C8051F330/1/2/3/4/5
9.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “18.1. Timer 0 and Timer 1” on page 177) select level
or edge sensitive. The table below lists the possible configurations.
IT0
1
1
0
0
IN0PL
0
1
0
1
/INT0 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
IT1
1
1
0
0
IN1PL
0
1
0
1
/INT1 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 9.11).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section
“14.1. Priority Crossbar Decoder” on page 125 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 9.4.
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Rev. 1.7
87
C8051F330/1/2/3/4/5
Bit addressable?
Cleared by HW?
Table 9.4. Interrupt Summary
0x0000
Top
None
N/A
N/A
Always
Enabled
0x0003
0
IE0 (TCON.1)
Y
Y
EX0 (IE.0) PX0 (IP.0)
0x000B
1
TF0 (TCON.5)
Y
Y
ET0 (IE.1) PT0 (IP.1)
0x0013
2
IE1 (TCON.3)
Y
Y
EX1 (IE.2) PX1 (IP.2)
0x001B
3
Y
Y
ET1 (IE.3) PT1 (IP.3)
UART0
0x0023
4
Y
N
ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow
0x002B
5
Y
N
ET2 (IE.5) PT2 (IP.5)
SPI0
0x0033
6
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN
(SPI0CN.4)
Y
N
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
0x003B
7
SI (SMB0CN.0)
Y
N
RESERVED
0x0043
8
N/A
N/A
ADC0 Window Compare 0x004B
9
N/A
AD0WINT
(ADC0CN.3)
AD0INT
(ADC0CN.5)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
N/A
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
Y
N
Y
N
Y
N
N
N
N/A
N/A
N
N
ESMB0
(EIE1.0)
N/A
EWADC0
(EIE1.2)
EADC0
(EIE1.3)
EPCA0
(EIE1.4)
ECP0
(EIE1.5)
N/A
ET3
(EIE1.7)
PSMB0
(EIP1.0)
N/A
PWADC0
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
N/A
PT3
(EIP1.7)
Interrupt Source
Reset
External Interrupt 0
(/INT0)
Timer 0 Overflow
External Interrupt 1
(/INT1)
Timer 1 Overflow
ADC0 Conversion
Complete
Programmable Counter
Array
Interrupt Priority
Vector
Order
0x0053
10
0x005B
11
Comparator0
0x0063
12
RESERVED
0x006B
13
Timer 3 Overflow
0x0073
14
88
Pending Flag
Rev. 1.7
Enable
Flag
Priority
Control
Always
Highest
C8051F330/1/2/3/4/5
9.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
SFR Definition 9.7. IE: Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
0xA8
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
Rev. 1.7
89
C8051F330/1/2/3/4/5
SFR Definition 9.8. IP: Interrupt Priority
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
10000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
90
UNUSED. Read = 1, Write = don't care.
PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
Rev. 1.7
0xB8
C8051F330/1/2/3/4/5
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1
R/W
R/W
R/W
R/W
R/W
ET3
Reserved
ECP0
EPCA0
EADC0
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
EWADC0 Reserved
Bit2
Bit1
R/W
Reset Value
ESMB0
00000000
Bit0
SFR Address:
0xE6
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
RESERVED. Read = 0. Must Write 0.
ECP0: Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EADC0: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
RESERVED. Read = 0. Must Write 0.
ESMB0: Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev. 1.7
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C8051F330/1/2/3/4/5
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1
R/W
R/W
R/W
R/W
R/W
PT3
Reserved
PCP0
PPCA0
PADC0
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
PWADC0 Reserved
Bit2
R/W
Reset Value
PSMB0
00000000
Bit0
SFR Address:
Bit1
0xF6
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
92
PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
RESERVED. Read = 0. Must Write 0.
PCP0: Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
RESERVED. Read = 0. Must Write 0.
PSMB0: SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 9.11. IT01CF: INT0/INT1 Configuration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
IN1PL
IN1SL2
IN1SL1
IN1SL0
IN0PL
IN0SL2
IN0SL1
IN0SL0
00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE4
*Note: Refer to SFR Definition 18.1 for INT0/1 edge- or level-sensitive interrupt selection.
Bit7:
IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
IN1SL2–0
000
001
010
011
100
101
110
111
/INT1 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Bit3:
IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
IN0SL2–0
000
001
010
011
100
101
110
111
/INT0 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Rev. 1.7
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C8051F330/1/2/3/4/5
9.4.
Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped
(analog peripherals remain in their selected states; the external oscillator is not effected). Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Definition 9.12 describes the Power Control Register (PCON) used to control the CIP-51's power management
modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscillators lowers power consumption considerably; however a reset is required to restart the MCU.
9.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “10.6. PCA Watchdog
Timer Reset” on page 100 for more information on the use and configuration of the WDT.
94
Rev. 1.7
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9.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
SFR Definition 9.12. PCON: Power Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
GF5
GF4
GF3
GF2
GF1
GF0
STOP
IDLE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x87
Bits7–2: GF5–GF0: General Purpose Flags 5–0.
These are general purpose flags for use under software control.
Bit1:
STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
Bit0:
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
Rev. 1.7
95
C8051F330/1/2/3/4/5
96
Rev. 1.7
C8051F330/1/2/3/4/5
10. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External Port pins are forced to a known state
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “13. Oscillators” on page 113 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “19.3. Watchdog Timer Mode” on page 201 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
VDD
Power On
Reset
Supply
Monitor
(wired-OR)
/RST
C0RSEF
Missing
Clock
Detector
(oneshot)
EN
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
Errant
FLASH
Operation
EN
System
Clock
WDT
Enable
Px.x
'0'
Enable
+
-
MCD
Enable
Px.x
+
-
Comparator 0
CIP-51
Microcontroller
Core
System Reset
Figure 10.1. Reset Sources
Rev. 1.7
97
C8051F330/1/2/3/4/5
10.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 10.2. plots the
power-on and VDD monitor reset timing. The maximum VDD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than
1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms.
volts
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is disabled following a
power-on reset.
VDD
2.70
2.55
VRST
VD
D
2.0
1.0
t
Logic HIGH
Logic LOW
/RST
TPORDelay
VDD
Monitor
Reset
Power-On
Reset
Figure 10.2. Power-On and VDD Monitor Reset Timing
10.2. Power-Fail Reset/VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the
VDD monitor will still be enabled after the reset.
98
Rev. 1.7
C8051F330/1/2/3/4/5
Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. The procedure for configuring the VDD monitor as a reset source is shown below:
Step 1. Enable the VDD monitor (VDMEN bit in VDM0CN = ‘1’).
Step 2. Wait for the VDD monitor to stabilize (see Table 10.1 for the VDD Monitor turn-on time).
Step 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
See Figure 10.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.
See Table 10.1 for complete electrical characteristics of the VDD monitor.
SFR Definition 10.1. VDM0CN: VDD Monitor Control
R/W
VDMEN
Bit7
R
R
R
R
R
R
R
VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Reset Value
Variable
Bit0
SFR Address: 0xFF
Bit7:
VDMEN: VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets
until it is also selected as a reset source in register RSTSRC (SFR Definition 10.2). The VDD
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it has stabilized may generate a system reset.
See Table 10.1 for the minimum VDD Monitor turn-on time.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
Bit6:
VDD STAT: VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
Bits5–0: Reserved. Read = 000000b. Write = don’t care.
10.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete RST pin
specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
10.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
Rev. 1.7
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C8051F330/1/2/3/4/5
10.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the noninverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying
Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by
this reset.
10.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “19.3. Watchdog Timer Mode” on
page 201; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.3) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
10.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
•
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX write operation targets an address above address 0x1DFF.
• A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above address 0x1DFF.
• A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above 0x1DFF.
• A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“11.3. Security Options” on page 105).
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
10.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the RST pin is unaffected by this reset.
100
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 10.2. RSTSRC: Reset Source
R
Bit7
R
R/W
FERROR C0RSEF
Bit6
Bit5
R/W
SWRSF
Bit4
R
R/W
WDTRSF MCDRSF
Bit3
R/W
R
Reset Value
PORSF
PINRSF
Variable
Bit1
Bit0
Bit2
SFR Address: 0xEF
Note:
Do not use read-modify-write operations (ORL, ANL) on this register.
Bit7:
Bit6:
UNUSED. Read = 0. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a FlashFlash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source
(active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit. Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the VDD
monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled
and stabilized may cause a system reset. See register VDM0CN (SFR Definition 10.1)
0: Read: Last reset was not a power-on or VDD monitor reset. Write: VDD monitor is not a
reset source.
1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags 
indeterminate. Write: VDD monitor is a reset source.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Rev. 1.7
101
C8051F330/1/2/3/4/5
Table 10.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Min
Typ
Max
Units
—
—
0.6
V
RST Input High Voltage
0.7 x VDD
—
—
V
RST Input Low Voltage
—
—
0.3 x VDD
—
25
40
µA
2.40
2.55
2.70
V
100
220
600
µs
—
—
32
µs
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
VDD Monitor Turn-on Time
100
—
—
µs
—
20
50
µA
RST Output Low Voltage
RST Input Pullup Current
Conditions
IOL = 8.5 mA, 
VDD = 2.7 V to 3.6 V
RST = 0.0 V
VDD POR Threshold (VRST)
Missing Clock Detector Timeout
Time from last system clock
rising edge to reset initiation
Reset Time Delay
Delay between release of any
reset source and code 
execution at location 0x0000
VDD Monitor Supply Current
102
Rev. 1.7
C8051F330/1/2/3/4/5
11. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to
logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and
erase operations are automatically timed by hardware for proper execution; data polling to determine the
end of the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation. Refer to Table 11.1 for complete Flash memory electrical characteristics.
11.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section “20. C2 Interface”
on page 209.
To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor
be enabled in any system that includes code that writes and/or erases Flash memory from software. See Section 11.4 for more details.
11.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 11.2.
11.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit
(PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the Flash key
codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed should be erased before a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Disable interrupts (recommended).
Set thePSEE bit (register PSCTL).
Set the PSWE bit (register PSCTL).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Using the MOVX instruction, write a data byte to any location within the 512-byte page to
be erased.
Step 7. Clear the PSWE and PSEE bits.
Rev. 1.7
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11.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
Step 1. Disable interrupts (recommended).
Step 2. Erase the 512-byte Flash page containing the target location, as described in Section
11.1.2.
Step 3. Set the PSWE bit (register PSCTL).
Step 4. Clear the PSEE bit (register PSCTL).
Step 5. Write the first key code to FLKEY: 0xA5.
Step 6. Write the second key code to FLKEY: 0xF1.
Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512byte sector.
Step 8. Clear the PSWE bit.
Steps 5–7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory.
Table 11.1. Flash Electrical Characteristics
VDD = 2.7 to 3.6 V; –40 to +85 ºC unless otherwise specified.
Parameter
Conditions
C8051F330/1
Flash Size
Endurance
Erase Cycle Time
Write Cycle Time
Typ
—
Max
—
Units
8192*
C8051F332/3
4096
—
—
bytes
C8051F334/5
2048
20 k
10
40
—
100 k
15
55
—
—
20
70
Erase/Write
ms
µs
25 MHz System Clock
25 MHz System Clock
Min
*Note: 512 bytes at addresses 0x1E00 to 0x1FFF are reserved.
11.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
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11.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1’s complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked
(all bits of the Lock Byte are ‘1’) and locked when any other Flash pages are locked (any bit of the
Lock Byte is ‘0’). See example below.
Addresses locked:
11111101b
00000010b
3 (First two Flash pages + Lock Byte Page)
0x0000 to 0x03FF (first two Flash pages) and 0x1C00 to 0x1DFF or 0x0E00 to
0x0FFF or 0x0600 to 0x07FF (Lock Byte Page)
C8051F330/1
C8051F332/3
Reserved
Reserved
0x1E00
Locked when
any other FLASH
pages are locked
Lock Byte
C8051F334/5
0x1DFF
Reserved
0x1000
Lock Byte
0x0FFF
0x800
Lock Byte
0x07FF
0x1DFE
0x0FFE
0x07FE
0x1C00
0x0E00
0x0600
Unlocked FLASH Pages
Unlocked FLASH Pages
Unlocked FLASH Pages
Locked Flash Pages
Locked Flash Pages
Access limit set
according to the
FLASH security
lock byte
Locked Flash Pages
0x0000
0x0000
FLASH memory organized in
512-byte pages
Security Lock Byte:
1s Complement:
Flash pages locked:
0x0000
Figure 11.2. Flash Program Memory Map
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The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 11.2 summarizes the Flash security
features of the 'F330/1/2/3/4/5 devices.
Table 11.2. Flash Security Summary
Action
C2 Debug
Interface
User Firmware executing from:
an unlocked page
a locked page
Permitted
Permitted
Permitted
Not Permitted
Flash Error Reset
Permitted
Read or Write page containing Lock Byte
(if no pages are locked)
Permitted
Permitted
Permitted
Read or Write page containing Lock Byte
(if any page is locked)
Not Permitted
Flash Error Reset
Permitted
Read contents of Lock Byte
(if no pages are locked)
Permitted
Permitted
Permitted
Read contents of Lock Byte
(if any page is locked)
Not Permitted
Flash Error Reset
Permitted
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Read, Write or Erase locked pages
(except page with Lock Byte)
Erase page containing Lock Byte
(if no pages are locked)
Permitted
Flash Error Reset Flash Error Reset
C2 Device
Erase Only
Flash Error Reset Flash Error Reset
Lock additional pages
(change '1's to '0's in the Lock Byte)
Not Permitted
Flash Error Reset Flash Error Reset
Unlock individual pages
(change '0's to '1's in the Lock Byte)
Not Permitted
Flash Error Reset Flash Error Reset
Read, Write or Erase Reserved Area
Not Permitted
Flash Error Reset Flash Error Reset
Erase page containing Lock Byte - Unlock all
pages (if any page is locked)

C2 Device Erase - Erases all Flash pages including the page containing the Lock Byte.
Flash Error Reset - Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after
reset).
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
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11.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
11.4.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot
meet this rise time specification, then add an external VDD brownout circuit to the RST pin of
the device that holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD
drops below 2.7 V.
3. Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For
'C'-based systems, this will involve modifying the startup code added by the 'C' compiler. See
your compiler documentation for more details. Make certain that there are no delays in software between enabling the VDD monitor and enabling the VDD monitor as a reset source.
Code examples showing this can be found in “AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site.
4. As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a
reset source inside the functions that write and erase Flash memory. The VDD monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
11.4.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There
should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that sets PSWE and PSEE both to a '1' to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address
updates and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code
examples showing this can be found in AN201, "Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser-
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viced in priority order after the Flash operation has been completed and interrupts have been
re-enabled by software.
10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See
your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas.
11. Add address bounds checking to the routines that write or erase Flash memory to ensure that
a routine called with an illegal address does not result in modification of the Flash.
11.4.3. System Clock
12. If operating from an external crystal, be advised that crystal performance is susceptible to
electrical interference and is sensitive to layout and to changes in temperature. If the system
is operating in an electrically noisy environment, use the internal oscillator or use an external
CMOS clock.
13. If operating from the external oscillator, switch to the internal oscillator during Flash write or
erase operations. The external oscillator can continue to run, and the CPU can switch back to
the external oscillator after the Flash operation has completed.
Additional Flash recommendations and example code can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site.
SFR Definition 11.1. PSCTL: Program Store R/W Control
R
R
R
R
R
R
R/W
R/W
Reset Value
—
—
—
—
—
—
PSEE
PSWE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x8F
Bits7–2: UNUSED: Read = 000000b, Write = don’t care.
Bit1:
PSEE: Program Store Erase Enable
Setting this bit (in combination with PSWE) allows an entire page of Flash program memory
to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to
Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Bit0:
PSWE: Program Store Write Enable
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
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SFR Definition 11.2. FLKEY: Flash Lock and Key
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xB7
Bits7–0: FLKEY: Flash Lock and Key Register
Write:
This register provides a lock and key function for Flash erasures and writes. Flash writes
and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash
writes and erases are automatically disabled after the next write or erase is complete. If any
writes to FLKEY are performed incorrectly, or if a Flash write or erase operation is attempted
while these operations are disabled, the Flash will be permanently locked from writes or erasures until the next device reset. If an application never writes to Flash, it can intentionally
lock the Flash by writing a non-0xA5 value to FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
SFR Definition 11.3. FLSCL: Flash Scale
R/W
FOSE
Bit7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xB6
Bit7:
FOSE: Flash One-shot Enable
This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash
sense amps are enabled for a full clock cycle during Flash reads. At system clock frequencies below 10 MHz, disabling the Flash one-shot will increase system power consumption.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
Bits6–0: RESERVED. Read = 0. Must Write 0.
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12. External RAM
The C8051F330/1/2/3/4/5 devices include 512 bytes of RAM mapped into the external data memory
space. All of these address locations may be accessed using the external move instruction (MOVX) and
the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an
8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External
Memory Interface Control Register (EMI0CN as shown in SFR Definition 12.1). Note: the MOVX instruction
is also used for writes to the Flash memory. See Section “11. Flash Memory” on page 103 for details.
The MOVX instruction accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 7 bits of the 16-bit external data memory address word
are "don't cares". As a result, the 512-byte RAM is mapped modulo style over the entire 64 k external data
memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses
0x0200, 0x0400, 0x0600, 0x0800, etc. This is a useful feature when performing a linear memory fill, as the
address pointer doesn't have to be reset when reaching the RAM block boundary.
SFR Definition 12.1. EMI0CN: External Memory Interface Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
—
—
—
—
—
PGSEL
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xAA
Bits7–1: UNUSED. Read = 0000000b. Write = don’t care.
Bit 0:
PGSEL: XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory address
when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since
the upper (unused) bits of the register are always zero, the PGSEL determines which page
of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
Rev. 1.7
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13. Oscillators
C8051F330/1/2/3/4/5 devices include a programmable internal high-frequency oscillator, a programmable
internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 13.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the
OSCLCN register, as shown in SFR Definition 13.3. The system clock can be sourced by the external
oscillator circuit or either internal oscillator. Both internal oscillators offer a selectable post-scaling feature.
The internal oscillators’ electrical specifications are given in Table 13.1 on page 122.
OSCLEN
OSCLRDY
OSCLF3
OSCLF2
OSCLF1
OSCLF0
OSCLD1
OSCLD0
OSCLCN
IFCN1
IFCN0
OSCICN
IOSCEN
IFRDY
OSCICL
Option 3
XTAL2
OSCLF OSCLD
EN
Programmable
Internal Clock
Generator
Option 4
XTAL2
n
OSCLF
EN
Option 2
Low Frequency
Oscillator
VDD
Option 1
OSCLD
XTAL1
XTAL2
Input
Circuit
10M
SYSCLK
n
OSC
OSCXCN
SEL1
SEL0
XFCN2
XFCN1
XFCN0
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XTAL2
CLKSEL
Figure 13.1. Oscillator Diagram
13.1. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F330/1/2/3/4/5 devices include a programmable internal high-frequency oscillator that defaults
as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL
register as defined by SFR Definition 13.1.
On C8051F330/1/2/3/4/5 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 122. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
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SFR Definition 13.1. OSCICL: Internal H-F Oscillator Calibration
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
Bit7
Variable
0xB3
Bit7:
UNUSED. Read = 0. Write = don’t care.
Bits 6–0: OSCICL: Internal Oscillator Calibration Register.
This register determines the internal oscillator period. When set to 0000000b, the H-F oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its
slowest setting. On C8051F330/1/2/3/4/5 devices, the reset value is factory calibrated to
generate an internal oscillator frequency of 24.5 MHz.
SFR Definition 13.2. OSCICN: Internal H-F Oscillator Control
R/W
R
R
R
R
R
R/W
R/W
Reset Value
IOSCEN
IFRDY
-
-
-
-
IFCN1
IFCN0
11000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB2
Bit7:
IOSCEN: Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
Bit6:
IFRDY: Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
Bits5–2: UNUSED. Read = 0000b, Write = don't care.
Bits1–0: IFCN1–0: Internal H-F Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
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13.2. Programmable Internal Low-Frequency (L-F) Oscillator
All C8051F330/1/2/3/4/5 devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be
changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Definition 13.3). Additionally, the OSCLF bits (OSCLCN5:2) can be used to adjust the oscillator’s output frequency.
13.2.1. Calibrating the Internal L-F Oscillator
Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when running from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture
Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a
capture event on the corresponding timer. As a capture event occurs, the current timer value
(TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.
SFR Definition 13.3. OSCLCN: Internal L-F Oscillator Control
R/W
R
R/W
OSCLEN OSCLRDY OSCLF3
Bit7
Bit6
Bit5
R/W
R/W
R/W
R/W
R/W
OSCLF2
OSCLF1
OSCLF0
OSCLD1
OSCLD0
Reset Value
00vvvv00
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE3
Bit7:
OSCLEN: Internal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
Bit6:
OSCLRDY: Internal L-F Oscillator Ready.
0: Internal L-F Oscillator frequency not stabilized.
1: Internal L-F Oscillator frequency stabilized.
Bits5–2: OSCLF[3:0]: Internal L-F Oscillator Frequency Control bits.
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the L-F
oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator operates at its
slowest setting.
Bits1–0: OSCLD[1:0]: Internal L-F Oscillator Divider Select.
00: Divide by 8 selected.
01: Divide by 4 selected.
10: Divide by 2 selected.
11: Divide by 1 selected.
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13.3. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13.1. A
10 Mresistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 13.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 13.4).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “14.1. Priority Crossbar Decoder” on page 125 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog
inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section
“14.2. Port I/O Initialization” on page 127 for details on Port input mode selection.
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SFR Definition 13.4. OSCXCN: External Oscillator Control
R
R/W
R/W
R/W
XTLVLD XOSCMD2 XOSCMD1 XOSCMD0
Bit7
Bit6
Bit5
Bit4
R
R/W
R/W
R/W
Reset Value
-
XFCN2
XFCN1
XFCN0
00000000
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB1
Bit7:
XTLVLD: Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
Bits6–4: XOSCMD2–0: External Oscillator Mode Bits.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
Bit3:
RESERVED. Read = 0, Write = don't care.
Bits2–0: XFCN2–0: External Oscillator Frequency Control Bits.
000–111: See table below:
XFCN
000
001
010
011
100
101
110
111
Crystal (XOSCMD = 11x)
f  32 kHz
32 kHz f 84 kHz
84 kHz  f 225 kHz
225 kHz  f 590 kHz
590 kHz  f 1.5 MHz
1.5 MHz  f 4 MHz
4 MHz  f 10 MHz
10 MHz  f 30 MHz
RC (XOSCMD = 10x)
f 25 kHz
25 kHz f 50 kHz
50 kHz f 100 kHz
100 kHz f 200 kHz
200 kHz f 400 kHz
400 kHz f 800 kHz
800 kHz f 1.6 MHz
1.6 MHz f 3.2 MHz
C (XOSCMD = 10x)
K Factor = 0.87
K Factor = 2.6
K Factor = 7.7
K Factor = 22
K Factor = 65
K Factor = 180
K Factor = 664
K Factor = 1590
CRYSTAL MODE (Circuit from Figure 13.1, Option 1; XOSCMD = 11x)
Choose XFCN value to match crystal frequency.
RC MODE (Circuit from Figure 13.1, Option 2; XOSCMD = 10x)
Choose XFCN value to match frequency range:
f = 1.23(103) / (R * C), where
f = frequency of clock in MHz
C = capacitor value in pF
R = Pullup resistor value in k
C MODE (Circuit from Figure 13.1, Option 3; XOSCMD = 10x)
Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C * VDD), where
f = frequency of clock in MHz
C = capacitor value the XTAL2 pin in pF
VDD = Power Supply on MCU in volts
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13.3.1. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 13.4 (OSCXCN register). For
example, an 11.0592 MHz crystal requires an XFCN setting of 111b and a 32.768 kHz Watch Crystal
requires an XFCN setting of 001b. After an external 32.768 kHz oscillator is stabilized, the XFCN setting
can be switched to 000 to save power. It is recommended to enable the missing clock detector before
switching the system clock to any external oscillator source.
When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is:
Step 1. Force XTAL1 and XTAL2 to a low state. This involves enabling the Crossbar and writing ‘0’
to port latches P0.2 and P0.3.
Step 2. Configure XTAL1 and XTAL2 as analog inputs using register P0MDIN.
Step 3. Enable the external oscillator.
Step 4. Wait at least 1 ms.
Step 5. Poll for XTLVLD => ‘1’.
Step 6. Enable the Missing Clock Detector.
Step 7. Switch the system clock to the external oscillator.
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
118
Rev. 1.7
C8051F330/1/2/3/4/5
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The desired load capacitance depends upon the crystal and the manufacturer. Please refer to the
crystal data sheet when completing these calculations.
For example, a tuning-fork crystal of 32.768 kHz with a recommended load capacitance of 12.5 pF should
use the configuration shown in Figure 13.1, Option 1. The total value of the capacitors and the stray capacitance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 13.2.
XTAL1
10M
XTAL2
32.768 kHz
22pF*
22pF*
* Capacitor values depend on
crystal specifications
Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram
Rev. 1.7
119
C8051F330/1/2/3/4/5
13.3.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation. If the frequency desired is
100 kHz, let R = 246 k and C = 50 pF:
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 13.4, the required XFCN setting is 010b.
13.3.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 13.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and
f = 150 kHz:
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 13.4
(OSCXCN) as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
120
Rev. 1.7
C8051F330/1/2/3/4/5
13.4. System Clock Selection
The internal oscillator requires little start-up time and may be selected as the system clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in
register OSCXCN) is set to '1' by hardware when the external oscillator is settled. In crystal mode, to
avoid reading a false XTLVLD, software should delay at least 1 ms between enabling the external
oscillator and checking XTLVLD. RC and C modes typically require no startup time.
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscillator, and Clock Multiplier so long as the selected clock source is enabled and has settled.
SFR Definition 13.5. CLKSEL: Clock Select
R
R
R
R
R
R
R/W
R/W
Reset Value
-
-
-
-
-
-
CLKSL1
CLKSL0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xA9
Bits7–2: UNUSED. Read = 000000b, Write = don't care.
Bits1–0: CLKSL[1:0]: System Clock Source Select Bits.
00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN
bits in register OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD
bits in register OSCLCN.
11: reserved.
Rev. 1.7
121
C8051F330/1/2/3/4/5
Table 13.1. Internal Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified
Parameter
Conditions
Min
Typ
Internal High-Frequency Oscillator (Using Factory-Calibrated Settings)
Oscillator Frequency
IFCN = 11b
24
24.5
=
3.0
V,
25
°C,
V
Oscillator Supply Current 
DD
—
450
(from VDD)
OSCICN.7 = 1
0.3 ±
0.1*
Temperature Sensitivity
Constant Supply
—
50 ± 10*
Internal Low-Frequency Oscillator (Using Factory-Calibrated Settings)
Oscillator Frequency
OSCLD = 11b
72
80
=
3.0
V,
25
°C,
V
Oscillator Supply Current 
DD
—
5.5
(from VDD)
OSCLCN.7 = 1
Power Supply Sensitivity
Constant Temperature
—
–3 ± 0.1*
Temperature Sensitivity
Constant Supply
—
20 ± 8*
Power Supply Sensitivity
Constant Temperature
*Note: Represents mean ±1 standard deviation.
122
Rev. 1.7
—
Max
Units
25
MHz
—
µA
—
%/V
—
ppm / °C
88
kHz
—
µA
—
—
%/V
ppm/°C
C8051F330/1/2/3/4/5
14. Port Input/Output
Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide
Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog
input; Port pins P0.0 - P1.7 can be assigned to one of the internal digital resources as shown in
Figure 14.3. The designer has complete control over which functions are assigned, limited only by the
number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority
Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch,
regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in SFR Definition 14.1 and SFR
Definition 14.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 14.1 on page 134.
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Priority
Decoder
(Internal Digital Signals)
Highest
Priority
8
P0
I/O
Cells
4
SPI
2
SMBus
CP0
Outputs
Digital
Crossbar
8
P1
I/O
Cells
P0.0
P0.7
P1.0
P1.7
2
SYSCLK
4
PCA
Lowest
Priority
2
UART
T0, T1
2
(Port Latches)
8
P0
(P0.0-P0.7)
8
P1
(P1.0-P1.7)
Figure 14.1. Port I/O Functional Block Diagram
Rev. 1.7
123
C8051F330/1/2/3/4/5
/WEAK-PULLUP
VDD
PUSH-PULL
/PORT-OUTENABLE
VDD
(WEAK)
PORT
PAD
PORT-OUTPUT
GND
Analog Select
ANALOG INPUT
PORT-INPUT
Figure 14.2. Port I/O Cell Block Diagram
124
Rev. 1.7
C8051F330/1/2/3/4/5
14.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.3 and/or
P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC or IDAC is configured to use the external
conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips
selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 14.3 shows
the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP = 0x00); Figure 14.4 shows the
Crossbar Decoder priority with the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C).
P0
SF Signals
PIN I/O
VREF IDA
0
1
x1
2
x2
3
P1
4
5
CNVSTR
6
7
0
1
2
3
P2
4
5
6
7
0
0
0
0
TX0
RX0
SCK
MISO
MOSI
*NSS is only pinned out in 4-wire SPI Mode
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
0
P0SKIP[0:7]
0
0
P1SKIP[0:7]
Port pin potentially available to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped
Rev. 1.7
125
C8051F330/1/2/3/4/5
P0
SF Signals
PIN I/O
VREF IDA
0
1
x1
2
x2
3
P2
P1
4
5
CNVSTR
6
7
0
1
2
3
4
5
6
7
0
TX0
RX0
SCK
MISO
MOSI
*NSS is only pinned out in 4-wire SPI Mode
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
1
1
0
0
0
0
0
0
0
P0SKIP[0:7]
0
0
0
0
0
P1SKIP[0:7]
Port pin potentially available to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
126
Rev. 1.7
C8051F330/1/2/3/4/5
14.2. Port I/O Initialization
Port I/O initialization consists of the following steps:
Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode
register (PnMDIN).
Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output
Mode register (PnMDOUT).
Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
Step 4. Assign Port pins to desired peripherals.
Step 5. Enable the Crossbar (XBARE = ‘1’).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates
a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. See SFR Definition 14.4 for the PnMDIN register details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the
Port I/O pin-assignments based on the XBRn Register settings.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
Rev. 1.7
127
C8051F330/1/2/3/4/5
SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
CP0AE
CP0E
SYSCKE
SMB0E
SPI0E
URT0E
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE1
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bit5:
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
Bit4:
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
Bit3:
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
Bit2:
SMB0E: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
Bit1:
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
Bit0:
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
128
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1
R/W
R/W
R/W
R/W
R/W
R
WEAKPUD
XBARE
T1E
T0E
ECIE
-
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
PCA0ME
Bit1
Bit0
Reset Value
00000000
SFR Address:
0xE2
Bit7:
WEAKPUD: Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input).
1: Weak Pullups disabled.
Bit6:
XBARE: Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
Bit5:
T1E: T1 Enable
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
Bit4:
T0E: T0 Enable
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
Bit3:
ECIE: PCA0 External Counter Input Enable
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Bit2:
Unused. Read = 0b. Write = don’t care.
Bits1–0: PCA0ME: PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
14.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Ports2–0 are accessed through corresponding special function registers (SFRs) that
are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is
latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins
are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions that target a Port Latch register as the destination. The
read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL,
INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For
these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR.
Rev. 1.7
129
C8051F330/1/2/3/4/5
SFR Definition 14.3. P0: Port0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Reset Value
0x80
Bits7–0: P0.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
SFR Definition 14.4. P0MDIN: Port0 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
11111111
0xF1
Bits7–0: Analog Input Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured as analog inputs have their weak pullup, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is not configured as an analog input.
130
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 14.5. P0MDOUT: Port0 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xA4
Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
(Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless
of the value of P0MDOUT).
SFR Definition 14.6. P0SKIP: Port0 Skip
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xD4
Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 14.7. P1: Port1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0x90
Bits7–0: P1.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port
pin when configured as digital input.
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Rev. 1.7
131
C8051F330/1/2/3/4/5
SFR Definition 14.8. P1MDIN: Port1 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
11111111
0xF2
Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured as analog inputs have their weak pullup, digital driver, and digital
receiver disabled.
0: Corresponding P1.n pin is configured as an analog input.
1: Corresponding P1.n pin is not configured as an analog input.
SFR Definition 14.9. P1MDOUT: Port1 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xA5
Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
SFR Definition 14.10. P1SKIP: Port1 Skip
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Reset Value
00000000
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD5
Bit7:
UNUSED: Read = 0b; Write = don’t care.
Bits6–0: P1SKIP[6:0]: Port1 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
132
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 14.11. P2: Port2
R
R
R
R
R
R
R
R/W
Reset Value
-
-
-
-
-
-
-
P2.0
00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xA0
Bits7–1: Unused. Read = 0000000b. Write = don’t care.
Bit0:
P2.0
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).
Read - Directly reads Port pin.
0: P2.n pin is logic low.
1: P2.n pin is logic high.
SFR Definition 14.12. P2MDOUT: Port2 Output Mode
R
R
R
R
R
R
R
-
-
-
-
-
-
-
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Reset Value
00000000
Bit0
SFR Address:
0xA6
Bits7–1: Unused. Read = 0000000b. Write = don’t care.
Bit0:
Output Configuration Bit for P2.0.
0: P2.0 Output is open-drain.
1: P2.0 Output is push-pull.
Rev. 1.7
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Table 14.1. Port I/O DC Electrical Characteristics
VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Conditions
IOH = –3 mA, Port I/O push-pull
Output High Voltage IOH = –10 µA, Port I/O push-pull
Output Low Voltage
134
Typ
—
Max
VDD – 0.1
—
—
—
IOH = –10 mA, Port I/O push-pull
IOL = 8.5 mA
—
—
—
0.6
IOL = 10 µA
—
—
0.1
IOL = 25 mA
—
1.0
—
Weak Pullup Off
2.0
—
—
—
—
—
—
0.8
±1
Weak Pullup On, VIN = 0 V
—
25
50
Rev. 1.7
Units
—
VDD – 0.8
Input High Voltage
Input Low Voltage
Input Leakage 
Current
Min
VDD – 0.7
V
V
V
V
µA
C8051F330/1/2/3/4/5
15. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus:
SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data
register, used for both transmitting and receiving SMBus data and slave addresses.
SMB0CN
MT S S A A A S
A X T T CRC I
SMAOK B K
T O
R L
E D
QO
R E
S
T
SMB0CF
E I B E S S S S
N N U XMMMM
S H S T B B B B
M Y H T F CC
B
OOT S S
L E E 1 0
D
00
T0 Overflow
01
T1 Overflow
10
TMR2H Overflow
11
TMR2L Overflow
SMBUS CONTROL LOGIC
Interrupt
Request
SCL
FILTER
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Data Path
IRQ Generation
Control
SCL
Control
C
R
O
S
S
B
A
R
N
SDA
Control
SMB0DAT
7 6 5 4 3 2 1 0
Port I/O
SDA
FILTER
N
Figure 15.1. SMBus Block Diagram
Rev. 1.7
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C8051F330/1/2/3/4/5
15.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
15.2. SMBus Configuration
Figure 15.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 15.2. Typical SMBus Configuration
15.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 15.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL.
136
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The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 15.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
START
SLA5-0
Slave Address + R/W
R/W
D7
ACK
D6-0
Data Byte
NACK
STOP
Figure 15.3. SMBus Transaction
15.3.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “15.3.4. SCL High (SMBus Free) Timeout”
on page 138). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will
be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and
receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device
always wins, and no data is lost.
Rev. 1.7
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15.3.2. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
15.3.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
15.3.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a
Master START, the START will be generated following this timeout. Note that a clock source is required for
free timeout detection, even in a slave-only implementation.
15.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
•
•
•
•
•
•
•
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting,
this interrupt is generated after the ACK cycle so that software may read the received ACK value; when
receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing
ACK value. See Section “15.5. SMBus Transfer Modes” on page 146 for more details on transmission
sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section
“15.4.2. SMB0CN Control Register” on page 143; Table 15.4 provides a quick SMB0CN decoding reference.
138
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SMBus configuration options include:
•
•
•
•
Timeout detection (SCL Low Timeout and/or Bus Free Timeout)
SDA setup and hold time extensions
Slave event enable/disable
Clock source selection
These options are selected in the SMB0CF register, as described in Section “15.4.1. SMBus Configuration Register” on page 140.
Rev. 1.7
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C8051F330/1/2/3/4/5
15.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
Table 15.1. SMBus Clock Source Selection
SMBCS1
0
0
1
1
SMBCS0
0
1
0
1
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 15.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “18. Timers” on page 177.
1
T HighMin = T LowMin = --------------------------------------------f ClockSourceOverflow
Equation 15.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 15.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 15.2.
f ClockSourceOverflow
BitRate = --------------------------------------------3
Equation 15.2. Typical SMBus Bit Rate
140
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Figure 15.4 shows the typical SCL generation described by Equation 15.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 15.1.
Timer Source
Overflows
SCL
TLow
SCL High Timeout
THigh
Figure 15.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 15.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 15.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Tlow – 4 system clocks
Minimum SDA Hold Time
0
or
3 system clocks
1
1 system clock + s/w delay*
11 system clocks
12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w
delay occurs between the time SMB0DAT or ACK is written and when SI is cleared.
Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w
delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “15.3.3. SCL Low Timeout” on page 138). The SMBus interface will force Timer 3
to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 15.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an
interrupt will be generated, and STO will be set).
Rev. 1.7
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C8051F330/1/2/3/4/5
SFR Definition 15.1. SMB0CF: SMBus Clock/Configuration
R/W
R/W
R
ENSMB
INH
BUSY
Bit7
Bit6
Bit5
R/W
R/W
R/W
R/W
EXTHOLD SMBTOE SMBFTE SMBCS1
Bit4
Bit3
Bit2
Bit1
R/W
Reset Value
SMBCS0
00000000
Bit0
SFR Address: 0xC1
Bit7:
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
Bit6:
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
Bit5:
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
Bit4:
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to .
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
Bit3:
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to
reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload while SCL is high.
Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt
service routine should reset SMBus communication.
Bit2:
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 10 SMBus clock source periods.
Bits1–0: SMBCS1–SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 15.1.
SMBCS1
0
0
1
1
142
SMBCS0
0
1
0
1
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
Rev. 1.7
C8051F330/1/2/3/4/5
15.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 15.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive
modes, respectively.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a ‘1’ to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a ‘1’ to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit
indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating
that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing
value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit
before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit;
however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further
slave events will be ignored until the next START is detected.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 15.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
Table 15.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 15.4 for SMBus status decoding using the SMB0CN register.
Rev. 1.7
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C8051F330/1/2/3/4/5
SFR Definition 15.2. SMB0CN: SMBus Control
R
R
MASTER TXMODE
Bit7
Bit6
R/W
R/W
STA
STO
Bit5
Bit4
R
R
ACKRQ ARBLOST
Bit3
Bit2
R/W
R/W
Reset Value
ACK
SI
00000000
Bit1
Bit0
Bit
Addressable
SFR Address: 0xC0
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
144
MASTER: SMBus Master/Slave Indicator.
This read-only bit indicates when the SMBus is operating as a master.
0: SMBus operating in Slave Mode.
1: SMBus operating in Master Mode.
TXMODE: SMBus Transmit Mode Indicator.
This read-only bit indicates when the SMBus is operating as a transmitter.
0: SMBus in Receiver Mode.
1: SMBus in Transmitter Mode.
STA: SMBus Start Flag.
Write:
0: No Start generated.
1: When operating as a master, a START condition is transmitted if the bus is free (If the bus
is not free, the START is transmitted after a STOP is received or a timeout is detected). If
STA is set by software as an active Master, a repeated START will be generated after the
next ACK cycle.
Read:
0: No Start or repeated Start detected.
1: Start or repeated Start detected.
STO: SMBus Stop Flag.
Write:
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted after the next ACK
cycle. When the STOP condition is generated, hardware clears STO to logic 0. If both STA
and STO are set, a STOP condition is transmitted followed by a START condition.
Read:
0: No Stop condition detected.
1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode).
ACKRQ: SMBus Acknowledge Request
This read-only bit is set to logic 1 when the SMBus has received a byte and needs the ACK
bit to be written with the correct ACK response value.
ARBLOST: SMBus Arbitration Lost Indicator.
This read-only bit is set to logic 1 when the SMBus loses arbitration while operating as a
transmitter. A lost arbitration while a slave indicates a bus error condition.
ACK: SMBus Acknowledge Flag.
This bit defines the out-going ACK level and records incoming ACK levels. It should be written each time a byte is received (when ACKRQ=1), or read after each byte is transmitted.
0: A "not acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if
in Receiver Mode).
1: An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in
Receiver Mode).
SI: SMBus Interrupt Flag.
This bit is set by hardware under the conditions listed in Table 15.3. SI must be cleared by
software. While SI is set, SCL is held low and the SMBus is stalled.
Rev. 1.7
C8051F330/1/2/3/4/5
Table 15.3. Sources for Hardware Changes to SMB0CN
Bit
Set by Hardware When:
MASTER
• A START is generated.
TXMODE
• START is generated.
• SMB0DAT is written before the start of an
SMBus frame.
STA
STO
ACKRQ
ARBLOST
ACK
SI
• A START followed by an address byte is
received.
• A STOP is detected while addressed as a
slave.
• Arbitration is lost due to a detected STOP.
• A byte has been received and an ACK
response value is needed.
• A repeated START is detected as a MASTER
when STA is low (unwanted repeated START).
• SCL is sensed low while attempting to generate a STOP or repeated START condition.
• SDA is sensed low while transmitting a ‘1’
(excluding ACK bits).
• The incoming ACK value is low 
(ACKNOWLEDGE).
• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an
ACK/NACK received.
• A byte has been received.
• A START or repeated START followed by a
slave address + R/W has been received.
• A STOP has been received.
Rev. 1.7
Cleared by Hardware When:
• A STOP is generated.
• Arbitration is lost.
• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
start of an SMBus frame.
• Must be cleared by software.
• A pending STOP is generated.
• After each ACK cycle.
• Each time SI is cleared.
• The incoming ACK value is high (NOT
ACKNOWLEDGE).
• Must be cleared by software.
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15.4.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Definition 15.3. SMB0DAT: SMBus Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xC2
Bits7–0: SMB0DAT: SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read
from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to
logic 1. The serial data in the register remains stable as long as the SI flag is set. When the
SI flag is not set, the system may be in the process of shifting data in/out and the CPU
should not attempt to access this register.
15.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating as a receiver, and after the ACK cycle when operating as a transmitter.
15.5.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates
the START condition and transmits the first byte containing the address of the target slave and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits
one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the
slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will
switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 15.5 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any
number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode.
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S
SLA
W
Interrupt
A
Data Byte
Interrupt
A
Data Byte
Interrupt
A
P
Interrupt
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 15.5. Typical Master Transmitter Sequence
Rev. 1.7
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15.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the
START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the
slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial
data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write
the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit generates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last
byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and
a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an
active Master Receiver. Figure 15.6 shows a typical Master Receiver sequence. Two received data bytes
are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts
occur before the ACK cycle in this mode.
S
SLA
R
Interrupt
A
Interrupt
Data Byte
A
Interrupt
Data Byte
N
Interrupt
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 15.6. Typical Master Receiver Sequence
148
Rev. 1.7
P
C8051F330/1/2/3/4/5
15.5.3. Slave Receiver Mode
Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH =
0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit
(WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the
ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received
slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until
the next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The
interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 15.7 shows a typical Slave
Receiver sequence. Two received data bytes are shown, though any number of bytes may be received.
Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode.
Interrupt
S
SLA
W
A
Interrupt
Data Byte
A
Interrupt
Data Byte
A
P
Interrupt
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 15.7. Typical Slave Receiver Sequence
Rev. 1.7
149
C8051F330/1/2/3/4/5
15.5.4. Slave Transmitter Mode
Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH
= 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a
slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an
interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an
ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave
interrupts will be inhibited until a START is detected. If the received slave address is acknowledged, data
should be written to SMB0DAT to be transmitted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the
acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is
a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode). The interface
exits Slave Transmitter Mode after receiving a STOP. Note that the interface will switch to Slave Receiver
Mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 15.8 shows a typical Slave
Transmitter sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode.
Interrupt
S
SLA
R
A
Interrupt
Data Byte
A
Data Byte
Interrupt
N
P
Interrupt
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 15.8. Typical Slave Transmitter Sequence
15.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown
response options are only the typical responses; application-specific procedures are allowed as long as
they conform to the SMBus specification. Highlighted responses are allowed but do not conform to the
SMBus specification.
150
Rev. 1.7
C8051F330/1/2/3/4/5
Table 15.4. SMBus Status Decoding
Values
Written
Status
Vector
ACKRQ
ARBLOST
ACK
1110
0
0
X A master START was generated.
0
0
0
ACK
Load slave address + R/W
into SMB0DAT.
0
0
X
Set STA to restart transfer.
A master data or address byte
was transmitted; NACK received. Abort transfer.
1
0
X
0
1
X
Load next data byte into
SMB0DAT.
0
0
X
End transfer with STOP.
0
1
X
End transfer with STOP and
start another transfer.
1
1
X
Send repeated START.
1
0
X
Switch to Master Receiver
Mode (clear SI without writing new data to SMB0DAT).
0
0
X
Acknowledge received byte;
Read SMB0DAT.
0
0
1
Send NACK to indicate last
byte, and send STOP.
0
1
0
Send NACK to indicate last
byte, and send STOP followed by START.
1
1
0
Send ACK followed by
repeated START.
1
0
1
1
0
0
Send ACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
0
0
1
Send NACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
0
0
0
1100
0
1000
1
0
0
1
X
Typical Response Options
STo
Current SMbus State
STA
Master Receiver
Master Transmitter
Mode
Values Read
A master data or address byte
was transmitted; ACK received.
A master data byte was received; Send NACK to indicate last
ACK requested.
byte, and send repeated
START.
Rev. 1.7
151
C8051F330/1/2/3/4/5
Table 15.4. SMBus Status Decoding
Values
Written
ACK
STA
STo
ACK
0101
ARBLOST
Status
Vector
0100
ACKRQ
Slave Transmitter
Mode
Values Read
0
0
0
A slave byte was transmitted;
NACK received.
No action required (expecting STOP condition).
0
0
X
0
0
1
A slave byte was transmitted;
ACK received.
Load SMB0DAT with next
data byte to transmit.
0
0
X
0
1
X
A Slave byte was transmitted;
error detected.
No action required (expecting Master to end transfer).
0
0
X
0
X
X
An illegal STOP or bus error was
X detected while a Slave Transmis- Clear STO.
sion was in progress.
0
0
Acknowledge received
address.
0
0
1
Do not acknowledge
received address.
0
0
0
Acknowledge received
address.
0
0
1
Do not acknowledge
received address.
0
0
0
Reschedule failed transfer;
do not acknowledge received
address.
1
0
0
Lost arbitration while attempting a Abort failed transfer.
repeated START.
Reschedule failed transfer.
0
0
X
1
0
X
Lost arbitration while attempting a No action required (transfer
STOP.
complete/aborted).
0
0
0
0
0
X
0
0
X
1
0
X
Acknowledge received byte;
Read SMB0DAT.
0
0
1
Do not acknowledge
received byte.
0
0
0
0
0
0
1
0
0
1
0
Current SMbus State
Typical Response Options
A slave address was received;
X
ACK requested.
0010
Slave Receiver
1
0010
0001
0
1
1
Lost arbitration as master; slave
X address received; ACK
requested.
X
1
1
X
0
0
A STOP was detected while
X addressed as a Slave Transmitter Clear STO.
or Slave Receiver.
0
1
X
1
0
Lost arbitration due to a detected Abort transfer.
STOP.
Reschedule failed transfer.
A slave byte was received; ACK
X
requested.
0000
1
152
1
X
Lost arbitration while transmitting Abort failed transfer.
a data byte as master.
Reschedule failed transfer.
Rev. 1.7
C8051F330/1/2/3/4/5
16. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “16.1. Enhanced Baud Rate Generation” on page 154). Received data buffering allows
UART0 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
(TX Shift)
SET
D
Q
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Start
Data
Tx Control
Tx Clock
Send
Tx IRQ
SCON
TI
Serial
Port
Interrupt
MCE
REN
TB8
RB8
TI
RI
SMODE
UART Baud
Rate Generator
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Start
Shift
0x1FF
RB8
Load
SBUF
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Figure 16.1. UART0 Block Diagram
Rev. 1.7
153
C8051F330/1/2/3/4/5
16.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 16.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
2
TX Clock
Overflow
2
RX Clock
TH1
Start
Detected
RX Timer
Figure 16.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload” on page 179). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 16.1-A
and Equation 16.1-B.
A)
1
UartBaudRate = ---  T1_Overflow_Rate
2
B)
T1 CLK
T1_Overflow_Rate = ------------------------256 – TH1
Equation 16.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “18. Timers” on page 177. A quick
reference for typical baud rates and system clock frequencies is given in Table 16.1 through Table 16.6.
Note that the internal oscillator may still generate the system clock when the external oscillator is driving
Timer 1.
154
Rev. 1.7
C8051F330/1/2/3/4/5
16.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
TX
RS-232
LEVEL
XLTR
RS-232
RX
C8051Fxxx
OR
TX
TX
RX
RX
MCU
C8051Fxxx
Figure 16.3. UART Interconnect Diagram
16.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP
BIT
BIT TIMES
BIT SAMPLING
Figure 16.4. 8-Bit UART Timing Diagram
Rev. 1.7
155
C8051F330/1/2/3/4/5
16.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to ‘1’. After the stop bit
is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to ‘1’. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to ‘1’. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to ‘1’.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
BIT
BIT TIMES
BIT SAMPLING
Figure 16.5. 9-Bit UART Timing Diagram
16.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
156
Rev. 1.7
C8051F330/1/2/3/4/5
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Figure 16.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 1.7
157
C8051F330/1/2/3/4/5
SFR Definition 16.1. SCON0: Serial Port 0 Control
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
S0MODE
-
MCE0
REN0
TB80
RB80
TI0
RI0
01000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0x98
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
158
S0MODE: Serial Port 0 Operation Mode.
This bit selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
UNUSED. Read = 1b. Write = don’t care.
MCE0: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
S0MODE = 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
S0MODE = 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
REN0: Receive Enable.
This bit enables/disables the UART receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB80: Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0
interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service
routine. This bit must be cleared manually by software.
RI0: Receive Interrupt Flag.
Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit
sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU
to vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 16.2. SBUF0: Serial (UART0) Port Data Buffer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x99
Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When
data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch.
Rev. 1.7
159
C8051F330/1/2/3/4/5
SYSCLK from
Internal Osc.
Table 16.1. Timer Settings for Standard Baud Rates Using the Internal 24.5 MHz
Oscillator
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
115200
57600
28800
14400
9600
2400
1200
–0.32%
–0.32%
0.15%
–0.32%
0.15%
–0.32%
–0.32%
0.15%
Frequency: 24.5 MHz
SCA1–SCA0
Oscilla- Timer Clock
Source
(pre-scale
tor Divide
Factor
select)1
106
SYSCLK
XX2
212
SYSCLK
XX
426
SYSCLK
XX
848
SYSCLK/4
01
1704
SYSCLK/12
00
2544
SYSCLK/12
00
10176
SYSCLK/48
10
20448
SYSCLK/48
10
T1M1
Timer 1
Reload
Value (hex)
1
1
1
0
0
0
0
0
0xCB
0x96
0x2B
0x96
0xB9
0x96
0x96
0x2B
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
SYSCLK from SYSCLK from
Internal Osc. External Osc.
Table 16.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz
Oscillator
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
115200
57600
28800
14400
9600
2400
1200
57600
28800
14400
–0.47%
0.45%
–0.01%
0.45%
–0.01%
0.15%
0.45%
–0.01%
–0.47%
–0.47%
0.45%
9600
0.15%
Frequency: 25.0 MHz
SCA1–SCA0
Oscilla- Timer Clock
Source
(pre-scale
tor Divide
Factor
select)1
108
SYSCLK
XX2
218
SYSCLK
XX
434
SYSCLK
XX
872
SYSCLK / 4
01
1736
SYSCLK / 4
01
2608
EXTCLK / 8
11
10464
SYSCLK / 48
10
20832
SYSCLK / 48
10
432
EXTCLK / 8
11
864
EXTCLK / 8
11
1744
EXTCLK / 8
11
2608
EXTCLK / 8
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
160
Rev. 1.7
11
T1M1
Timer 1
Reload
Value (hex)
1
1
1
0
0
0
0
0
0
0
0
0xCA
0x93
0x27
0x93
0x27
0x5D
0x93
0x27
0xE5
0xCA
0x93
0
0x5D
C8051F330/1/2/3/4/5
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Table 16.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz
Oscillator
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
Frequency: 22.1184 MHz
SCA1–SCA0
Oscilla- Timer Clock
Source
(pre-scale
tor Divide
Factor
select)1
96
SYSCLK
XX2
192
SYSCLK
XX
384
SYSCLK
XX
768
SYSCLK / 12
00
1536
SYSCLK / 12
00
2304
SYSCLK / 12
00
9216
SYSCLK / 48
10
18432
SYSCLK / 48
10
96
EXTCLK / 8
11
192
EXTCLK / 8
11
384
EXTCLK / 8
11
768
EXTCLK / 8
11
1536
EXTCLK / 8
11
2304
EXTCLK / 8
11
T1M1
Timer 1
Reload
Value (hex)
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0xD0
0xA0
0x40
0xE0
0xC0
0xA0
0xA0
0x40
0xFA
0xF4
0xE8
0xD0
0xA0
0x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Table 16.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz
Oscillator
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
Frequency: 18.432 MHz
Oscilla- Timer Clock
SCA1–SCA0
tor Divide
Source
(pre-scale
Factor
select)1
80
SYSCLK
XX2
160
SYSCLK
XX
320
SYSCLK
XX
640
SYSCLK / 4
01
1280
SYSCLK / 4
01
1920
SYSCLK / 12
00
7680
SYSCLK / 48
10
15360
SYSCLK / 48
10
80
EXTCLK / 8
11
160
EXTCLK / 8
11
320
EXTCLK / 8
11
640
EXTCLK / 8
11
1280
EXTCLK / 8
11
1920
EXTCLK / 8
11
T1M1
Timer 1
Reload
Value (hex)
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0xD8
0xB0
0x60
0xB0
0x60
0xB0
0xB0
0x60
0xFB
0xF6
0xEC
0xD8
0xB0
0x88
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
Rev. 1.7
161
C8051F330/1/2/3/4/5
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Table 16.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz
Oscillator
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
Frequency: 11.0592 MHz
SCA1–SCA0
Oscilla- Timer Clock
Source
(pre-scale
tor Divide
Factor
select)1
48
SYSCLK
XX2
96
SYSCLK
XX
192
SYSCLK
XX
384
SYSCLK
XX
768
SYSCLK / 12
00
1152
SYSCLK / 12
00
4608
SYSCLK / 12
00
9216
SYSCLK / 48
10
48
EXTCLK / 8
11
96
EXTCLK / 8
11
192
EXTCLK / 8
11
384
EXTCLK / 8
11
768
EXTCLK / 8
11
1152
EXTCLK / 8
11
T1M1
Timer 1
Reload
Value (hex)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0xE8
0xD0
0xA0
0x40
0xE0
0xD0
0x40
0xA0
0xFD
0xFA
0xF4
0xE8
0xD0
0xB8
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Table 16.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz
Oscillator
Target
Baud Rate
(bps)
Baud
Rate%
Error
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
Frequency: 3.6864 MHz
Oscilla- Timer Clock
SCA1–SCA0
tor Divide
Source
(pre-scale
Factor
select)1
16
SYSCLK
XX2
32
SYSCLK
XX
64
SYSCLK
XX
128
SYSCLK
XX
256
SYSCLK
XX
384
SYSCLK
XX
1536
SYSCLK / 12
00
3072
SYSCLK / 12
00
16
EXTCLK / 8
11
32
EXTCLK / 8
11
64
EXTCLK / 8
11
128
EXTCLK / 8
11
256
EXTCLK / 8
11
384
EXTCLK / 8
11
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
2. X = Don’t care.
162
Rev. 1.7
T1M1
Timer 1
Reload
Value (hex)
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0xF8
0xF0
0xE0
0xC0
0x80
0x40
0xC0
0x80
0xFF
0xFE
0xFC
0xF8
0xF0
0xE8
C8051F330/1/2/3/4/5
17. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SYSCLK
SPI0CN
SPIF
WCOL
MODF
RXOVRN
NSSMD1
NSSMD0
TXBMT
SPIEN
SPI0CFG
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CKR
Clock Divide
Logic
SPI CONTROL LOGIC
Data Path
Control
SPI IRQ
Pin Interface
Control
MOSI
Tx Data
SPI0DAT
SCK
Transmit Data Buffer
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Pin
Control
Logic
MISO
C
R
O
S
S
B
A
R
Port I/O
NSS
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 17.1. SPI Block Diagram
Rev. 1.7
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C8051F330/1/2/3/4/5
17.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
17.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
17.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
17.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
17.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and
NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode.
Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This
is intended for point-to-point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and
NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When
operating as a master, a 1-to-0 transition of the NSS signal disables the master function of
SPI0 so that multiple master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as
an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This
configuration should only be used when operating SPI0 as a master device.
See Figure 17.2, Figure 17.3, and Figure 17.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “14. Port Input/Output” on page 123 for general purpose
port I/O and crossbar information.
164
Rev. 1.7
C8051F330/1/2/3/4/5
17.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 17.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 17.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 17.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
Rev. 1.7
165
C8051F330/1/2/3/4/5
Master
Device 1
NSS
GPIO
MISO
MISO
MOSI
MOSI
SCK
SCK
GPIO
NSS
Master
Device 2
Figure 17.2. Multiple-Master Mode Connection Diagram
Master
Device
MISO
MISO
MOSI
MOSI
SCK
SCK
Slave
Device
Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection
Diagram
Master
Device
GPIO
MISO
MISO
MOSI
MOSI
SCK
SCK
NSS
NSS
MISO
MOSI
Slave
Device
Slave
Device
SCK
NSS
Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection
Diagram
166
Rev. 1.7
C8051F330/1/2/3/4/5
17.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 17.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 17.3 shows a connection diagram between a slave device in 3wire slave mode and a master device.
17.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This
flag can occur in all SPI0 modes.
2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted
when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the
write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur
in all SPI0 modes.
3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master,
and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the
MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master
device to access the bus.
4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave,
and a transfer is completed and the receive buffer still holds an unread byte from a previous
transfer. The new byte is not transferred to the receive buffer, allowing the previously received
data byte to be read. The data byte which caused the overrun is lost.
Rev. 1.7
167
C8051F330/1/2/3/4/5
17.5. Serial Clock Timing
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 17.5. For slave mode, the clock and
data relationships are shown in Figure 17.6 and Figure 17.7. Note that CKPHA must be set to ‘0’ on both
the master and slave SPI when communicating between two of the following devices: C8051F04x,
C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 17.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NSS (Must Remain High
in Multi-Master Mode)
Figure 17.5. Master Mode Data/Clock Timing
168
Rev. 1.7
Bit 1
Bit 0
C8051F330/1/2/3/4/5
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (4-Wire Mode)
Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MISO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
NSS (4-Wire Mode)
Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1)
17.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
Rev. 1.7
169
C8051F330/1/2/3/4/5
SFR Definition 17.1. SPI0CFG: SPI0 Configuration
R
R/W
R/W
R/W
R
R
R
R
Reset Value
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA1
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SPIBSY: SPI Busy (read only).
This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
SLVSEL: Slave Selected Flag (read only).
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the
instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
NSSIN: NSS Instantaneous Pin Input (read only).
This bit mimics the instantaneous value that is present on the NSS port pin at the time that
the register is read. This input is not de-glitched.
SRMT: Shift Register Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register,
and there is no new information available to read from the transmit buffer or write to the
receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from
the transmit buffer or by a transition on SCK.
NOTE: SRMT = 1 when in Master Mode.
RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when the receive buffer has been read and contains no new
information. If there is new information available in the receive buffer that has not been read,
this bit will return to logic 0.
NOTE: RXBMT = 1 when in Master Mode.
*Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 17.1 for timing parameters.
170
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 17.2. SPI0CN: SPI0 Control
R/W
R/W
R/W
SPIF
WCOL
MODF
Bit7
Bit6
Bit5
R/W
R/W
R/W
RXOVRN NSSMD1 NSSMD0
Bit4
Bit3
Bit2
R
R/W
Reset Value
TXBMT
SPIEN
00000110
Bit1
Bit0
Bit
Addressable
SFR Address: 0xF8
Bit 7:
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
Bit 6:
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware if a write to SPI0DAT is attempted when the transmit
buffer has not been emptied to the SPI shift register. It must be cleared by software.
Bit 5:
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software.
Bit 4:
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Bits 3–2: NSSMD1–NSSMD0: Slave Select Mode.
Selects between the following NSS operation modes:
(See Section “17.2. SPI0 Master Mode Operation” on page 165 and Section “17.3. SPI0
Slave Mode Operation” on page 167).
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
Bit 1:
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
Bit 0:
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
Rev. 1.7
171
C8051F330/1/2/3/4/5
SFR Definition 17.3. SPI0CKR: SPI0 Clock Rate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA2
Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
SYSCLK
f SCK = -----------------------------------------------2   SPI0CKR + 1 
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000 f SCK = ------------------------2  4 + 1
f SCK = 200kHz
SFR Definition 17.4. SPI0DAT: SPI0 Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA3
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
172
Rev. 1.7
C8051F330/1/2/3/4/5
SCK*
T
T
MCKH
MCKL
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 17.8. SPI Master Timing (CKPHA = 0)
SCK*
T
T
MCKH
MCKL
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 17.9. SPI Master Timing (CKPHA = 1)
Rev. 1.7
173
C8051F330/1/2/3/4/5
NSS
T
T
SE
T
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
T
SEZ
T
SOH
SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 17.10. SPI Slave Timing (CKPHA = 0)
NSS
T
T
SE
T
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
T
T
SOH
SLH
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 17.11. SPI Slave Timing (CKPHA = 1)
174
Rev. 1.7
T
SDZ
C8051F330/1/2/3/4/5
Table 17.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing* (See Figure 17.8 and Figure 17.9)
TMCKH
SCK High Time
1 x TSYSCLK
—
ns
TMCKL
SCK Low Time
1 x TSYSCLK
—
ns
TMIS
MISO Valid to SCK Shift Edge
1 x TSYSCLK + 20
—
ns
TMIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing* (See Figure 17.10 and Figure 17.11)
TSE
NSS Falling to First SCK Edge
2 x TSYSCLK
—
ns
TSD
Last SCK Edge to NSS Rising
2 x TSYSCLK
—
ns
TSEZ
NSS Falling to MISO Valid
—
4 x TSYSCLK
ns
TSDZ
NSS Rising to MISO High-Z
—
4 x TSYSCLK
ns
TCKH
SCK High Time
5 x TSYSCLK
—
ns
TCKL
SCK Low Time
5 x TSYSCLK
—
ns
TSIS
MOSI Valid to SCK Sample Edge
2 x TSYSCLK
—
ns
TSIH
SCK Sample Edge to MOSI Change
2 x TSYSCLK
—
ns
TSOH
SCK Shift Edge to MISO Change
—
4 x TSYSCLK
ns
TSLH
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
6 x TSYSCLK
8 x TSYSCLK
ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 1.7
175
C8051F330/1/2/3/4/5
176
Rev. 1.7
C8051F330/1/2/3/4/5
18. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload
Timer 0 and Timer 1 Modes:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with autoreload
Two 8-bit counter/timers (Timer 0
only)
Timer 2 Modes:
Timer 3 Modes:
16-bit timer with auto-reload
16-bit timer with auto-reload
Two 8-bit timers with auto-reload
Two 8-bit timers with auto-reload
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 18.3 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
18.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (Section “9.3.5. Interrupt Register Descriptions” on page 89); Timer 1 interrupts can be enabled by
setting the ET1 bit in the IE register (Section 9.3.5). Both counter/timers operate in one of four primary
modes selected by setting the Mode Select bits T1M1–T0M0 in the Counter/Timer Mode register (TMOD).
Each timer can be configured independently. Each operating mode is described below.
18.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
Rev. 1.7
177
C8051F330/1/2/3/4/5
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“14.1. Priority Crossbar Decoder” on page 125 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 18.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 9.11). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal /INT0 (see Section “9.3.5. Interrupt Register
Descriptions” on page 89), facilitating pulse width measurements
TR0
0
1
1
1
GATE0
X
0
1
1
/INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 9.11).
CKCON
T
3
M
H
P re -s c a le d C lo c k
T
3
M
L
T
2
M
H
TM OD
T T T S S
2 1 0 C C
MMM A A
1 0
L
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
IT 0 1 C F
T
0
M
1
T
0
M
0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
0
SYS C LK
1
1
TCLK
TR 0
TL0
(5 b its )
TH 0
(8 b its )
G ATE0
C ro s s b a r
/IN T 0
IN 0 P L
TCON
T0
TF1
TR1
TF0
TR0
IE 1
IT 1
IE 0
IT 0
In te rru p t
XO R
Figure 18.1. T0 Mode 0 Block Diagram
18.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
178
Rev. 1.7
C8051F330/1/2/3/4/5
18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0
is active as defined by bit IN0PL in register IT01CF (see Section “9.3.2. External Interrupts” on page 87
for details on the external input signals /INT0 and /INT1).
CKCON
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
Pre-scaled Clock
TMOD
S
C
A
0
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
IT01CF
T
0
M
1
T
0
M
0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
0
SYSCLK
1
1
T0
TL0
(8 bits)
TCON
TCLK
TR0
Crossbar
GATE0
TH0
(8 bits)
/INT0
IN0PL
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Reload
XOR
Figure 18.2. T0 Mode 2 Block Diagram
Rev. 1.7
179
C8051F330/1/2/3/4/5
18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0
and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register
is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the
Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the
Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
CKCON
TMOD
T T T T T TSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
Pre-scaled Clock
G
A
T
E
1
C
/
T
1
T T
1 1
MM
1 0
G
A
T
E
0
C
/
T
0
T T
0 0
MM
1 0
0
TR1
SYSCLK
TH0
(8 bits)
1
TCON
0
1
T0
TL0
(8 bits)
TR0
Crossbar
/INT0
GATE0
IN0PL
XOR
Figure 18.3. T0 Mode 3 Block Diagram
180
Rev. 1.7
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
C8051F330/1/2/3/4/5
SFR Definition 18.1. TCON: Timer Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
0x88
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to ‘1’ when /INT1 is active
as defined by bit IN1PL in register IT01CF (see SFR Definition 9.11).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1
is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition
9.11).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to ‘1’ when /INT0 is active
as defined by bit IN0PL in register IT01CF (see SFR Definition 9.11).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0
is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition
9.11).
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
Rev. 1.7
181
C8051F330/1/2/3/4/5
SFR Definition 18.2. TMOD: Timer Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
GATE1
C/T1
T1M1
T1M0
GATE0
C/T0
T0M1
T0M0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x89
Bit7:
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in register IT01CF (see SFR Definition 9.11).
Bit6:
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.3).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5–4: T1M1–T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
0
0
1
1
T1M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with auto-reload
Mode 3: Timer 1 inactive
Bit3:
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 9.11).
Bit2:
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.2).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1–0: T0M1–T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T0M1
0
0
1
1
182
T0M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with auto-reload
Mode 3: Two 8-bit counter/timers
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 18.3. CKCON: Clock Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
T3MH
T3ML
T2MH
T2ML
T1M
T0M
SCA1
SCA0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8E
Bit7:
T3MH: Timer 3 High Byte Clock Select.
This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8bit timer mode. T3MH is ignored if Time 3 is in any other mode.
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
Bit6:
T3ML: Timer 3 Low Byte Clock Select.
This bit selects the clock supplied to Timer 3. If Timer 3 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
Bit5:
T2MH: Timer 2 High Byte Clock Select.
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
Bit4:
T2ML: Timer 2 Low Byte Clock Select.
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
Bit3:
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
Bit2:
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Counter/Timer 0 uses the system clock.
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits.
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
SCA1
SCA0
Prescaled Clock
0
0
System clock divided by 12
0
1
System clock divided by 4
1
0
System clock divided by 48
1
1
External clock divided by 8
Note: External clock divided by 8 is synchronized with
the system clock.
Rev. 1.7
183
C8051F330/1/2/3/4/5
SFR Definition 18.4. TL0: Timer 0 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8A
Bits 7–0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 18.5. TL1: Timer 1 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8B
Bits 7–0: TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
SFR Definition 18.6. TH0: Timer 0 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8C
Bits 7–0: TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 18.7. TH1: Timer 1 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0x8D
Bits 7–0: TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
184
Rev. 1.7
C8051F330/1/2/3/4/5
18.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
18.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 18.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T2XCLK
SYSCLK / 12
0
External Clock / 8
1
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
S
C
A
0
0
TCLK
TMR2L
TMR2H
TMR2CN
TR2
SYSCLK
To ADC,
SMBus
To SMBus
TL2
Overflow
1
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
Interrupt
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 18.4. Timer 2 16-Bit Mode Block Diagram
Rev. 1.7
185
C8051F330/1/2/3/4/5
18.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
0
0
1
T2XCLK
0
1
X
TMR2H Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
T2ML
0
0
1
T2XCLK
0
1
X
TMR2L Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
T2XCLK
SYSCLK / 12
0
External Clock / 8
1
S
C
A
0
TMR2RLH
Reload
To SMBus
0
TCLK
TR2
TMR2H
TMR2RLL
SYSCLK
Reload
TMR2CN
1
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
1
TCLK
TMR2L
To ADC,
SMBus
0
Figure 18.5. Timer 2 8-Bit Mode Block Diagram
186
Rev. 1.7
Interrupt
C8051F330/1/2/3/4/5
SFR Definition 18.8. TMR2CN: Timer 2 Control
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Reset Value
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
—
T2XCLK
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
0xC8
TF2H: Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine.
TF2H is not automatically cleared by hardware and must be cleared by software.
TF2L: Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L
will set when the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hardware.
TF2LEN: Timer 2 Low Byte Interrupt Enable.
This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 interrupts are enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
0: Timer 2 Low Byte interrupts disabled.
1: Timer 2 Low Byte interrupts enabled.
TF2CEN: Timer 2 Low-Frequency Oscillator Capture Enable.
This bit enables/disables Timer 2 Low-Frequency Oscillator Capture Mode. If TF2CEN is set
and Timer 2 interrupts are enabled, an interrupt will be generated on a falling edge of the
low-frequency oscillator output, and the current 16-bit timer value in TMR2H:TMR2L will be
copied to TMR2RLH:TMR2RLL. See Section “13. Oscillators” on page 113 for more
details.
0: Timer 2 Low-Frequency Oscillator Capture disabled.
1: Timer 2 Low-Frequency Oscillator Capture enabled.
T2SPLIT: Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TMR2H only;
TMR2L is always enabled in this mode.
0: Timer 2 disabled.
1: Timer 2 enabled.
UNUSED. Read = 0b. Write = don’t care.
T2XCLK: Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 2 external clock selection is the system clock divided by 12.
1: Timer 2 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
Rev. 1.7
187
C8051F330/1/2/3/4/5
SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xCA
Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 18.10. TMR2RLH: Timer 2 Reload Register High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xCB
Bits 7–0: TMR2RLH: Timer 2 Reload Register High Byte.
The TMR2RLH holds the high byte of the reload value for Timer 2.
SFR Definition 18.11. TMR2L: Timer 2 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xCC
Bits 7–0: TMR2L: Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-bit mode,
TMR2L contains the 8-bit low byte timer value.
SFR Definition 18.12. TMR2H Timer 2 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xCD
Bits 7–0: TMR2H: Timer 2 High Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-bit
mode, TMR2H contains the 8-bit high byte timer value.
188
Rev. 1.7
C8051F330/1/2/3/4/5
18.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines
the Timer 3 operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
18.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 18.6,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow from 0xFF to 0x00.
CKCON
T3XCLK
SYSCLK / 12
0
External Clock / 8
1
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
S
C
A
0
To ADC
0
SYSCLK
TCLK
TMR3L
TMR3H
TMR3CN
TR3
1
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
Interrupt
T3XCLK
TMR3RLL TMR3RLH
Reload
Figure 18.6. Timer 3 16-Bit Mode Block Diagram
Rev. 1.7
189
C8051F330/1/2/3/4/5
18.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 18.7. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
T3MH
T3XCLK
0
0
1
0
1
X
TMR3H Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK
T3ML
T3XCLK
0
0
1
0
1
X
TMR3L Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
T3XCLK
SYSCLK / 12
0
External Clock / 8
1
S
C
A
0
TMR3RLH
Reload
0
TCLK
TR3
TMR3H
TMR3RLL
SYSCLK
Reload
TMR3CN
1
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK
1
TCLK
TMR3L
To ADC
0
Figure 18.7. Timer 3 8-Bit Mode Block Diagram
190
Rev. 1.7
Interrupt
C8051F330/1/2/3/4/5
SFR Definition 18.13. TMR3CN: Timer 3 Control
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Reset Value
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
—
T3XCLK
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x91
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF3H: Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine.
TF3H is not automatically cleared by hardware and must be cleared by software.
TF3L: Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF3LEN is set and Timer 3 interrupts are enabled. TF3L
will set when the low byte overflows regardless of the Timer 3 mode. This bit is not automatically cleared by hardware.
TF3LEN: Timer 3 Low Byte Interrupt Enable.
This bit enables/disables Timer 3 Low Byte interrupts. If TF3LEN is set and Timer 3 interrupts are enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
0: Timer 3 Low Byte interrupts disabled.
1: Timer 3 Low Byte interrupts enabled.
TF3CEN: Timer 3 Low-Frequency Oscillator Capture Enable.
This bit enables/disables Timer 3 Low-Frequency Oscillator Capture Mode. If TF3CEN is set
and Timer 3 interrupts are enabled, an interrupt will be generated on a rising edge of the
low-frequency oscillator output, and the current 16-bit timer value in TMR3H:TMR3L will be
copied to TMR3RLH:TMR3RLL. See Section “13. Oscillators” on page 113 for more
details.
0: Timer 3 Low-Frequency Oscillator Capture disabled.
1: Timer 3 Low-Frequency Oscillator Capture enabled.
T3SPLIT: Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3. In 8-bit mode, this bit enables/disables TMR3H only;
TMR3L is always enabled in this mode.
0: Timer 3 disabled.
1: Timer 3 enabled.
UNUSED. Read = 0b. Write = don’t care.
T3XCLK: Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 3 Clock
Select bits (T3MH and T3ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 3 external clock selection is the system clock divided by 12.
1: Timer 3 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
Rev. 1.7
191
C8051F330/1/2/3/4/5
SFR Definition 18.14. TMR3RLL: Timer 3 Reload Register Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0x92
Bits 7–0: TMR3RLL: Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 18.15. TMR3RLH: Timer 3 Reload Register High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0x93
Bits 7–0: TMR3RLH: Timer 3 Reload Register High Byte.
The TMR3RLH holds the high byte of the reload value for Timer 3.
SFR Definition 18.16. TMR3L: Timer 3 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x94
Bits 7–0: TMR3L: Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8-bit mode,
TMR3L contains the 8-bit low byte timer value.
SFR Definition 18.17. TMR3H Timer 3 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x95
Bits 7–0: TMR3H: Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In 8-bit
mode, TMR3H contains the 8-bit high byte timer value.
192
Rev. 1.7
C8051F330/1/2/3/4/5
19. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “14.1. Priority
Crossbar Decoder” on page 125 for details on configuring the Crossbar). The counter/timer is driven by
a programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in Section “19.2. Capture/Compare
Modules” on page 195). The external oscillator clock option is ideal for real-time clock (RTC) functionality,
allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The PCA block diagram is shown in Figure 19.1
Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 19.3 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
PCA
CLOCK
MUX
16-Bit Counter/Timer
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2 / WDT
CEX2
CEX1
CEX0
ECI
Crossbar
Port I/O
Figure 19.1. PCA Block Diagram
Rev. 1.7
193
C8051F330/1/2/3/4/5
19.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 19.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the
CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle
mode.
Table 19.1. PCA Timebase Input Options
CPS2
0
0
0
CPS1
0
0
1
CPS0
0
1
0
0
1
1
1
1
0
0
0
1
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
System clock
External oscillator source divided by 8*
*Note: External oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0M D
C
I
D
L
W
D
T
E
W
D
L
C
K
C
P
S
2
C
P
S
1
PC A0CN
C E
P C
S F
0
C C
F R
C
C
F
2
C
C
F
1
C
C
F
0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
Tim er 0 Overflow
ECI
SYSCLK
External Clock/8
000
001
010
0
011
1
PCA0H
PCA0L
O verflow
CF
100
101
To PCA M odules
Figure 19.2. PCA Counter/Timer Block Diagram
194
To PCA Interrupt System
Rev. 1.7
C8051F330/1/2/3/4/5
19.2. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit
Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation.
Table 19.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA capture/compare module’s operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's
CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. See
Figure 19.3 for details on the PCA interrupt configuration.
Table 19.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
PWM16 ECOM
CAPP CAPN
MAT
TOG
PWM
ECCF
X
X
1
0
0
0
0
X
X
X
0
1
0
0
0
X
X
X
1
1
0
0
0
X
X
X
X
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
X
X
X
0
1
1
0
0
0
0
1
1
1
X
X
X
X
X
Operation Mode
Capture triggered by positive edge
on CEXn
Capture triggered by negative
edge on CEXn
Capture triggered by transition on
CEXn
Software Timer
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator
16-Bit Pulse Width Modulator
Note: X = Don’t Care.
(for n = 0 to 2)
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
PCA0CN
CC
FR
CCC
CCC
FFF
2 1 0
PCA0MD
C WW
I DD
DT L
LEC
K
CCCE
PPPC
SSSF
2 1 0
0
PCA Counter/
Timer Overflow
1
ECCF0
EPCA0
0
PCA Module 0
(CCF0)
1
EA
0
0
1
1
Interrupt
Priority
Decoder
ECCF1
0
PCA Module 1
(CCF1)
1
ECCF2
PCA Module 2
(CCF2)
0
1
Figure 19.3. PCA Interrupt Block Diagram
Rev. 1.7
195
C8051F330/1/2/3/4/5
19.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
PCA Interrupt
PCA0CPMn
P EC
WCA
MOP
1 MP
6 n n
n
CMT P E
A AOWC
P TGMC
Nn n n F
n
n
Crossbar
CEXn
C
C
F
1
C
C
F
0
x 0 0 x
0
Port I/O
C
C
F
2
(to CCFn)
x 0
PCA0CN
CC
FR
1
PCA0CPLn
PCA0CPHn
Capture
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 19.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
196
Rev. 1.7
C8051F330/1/2/3/4/5
19.2.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit
is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must
be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software
Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA Interrupt
ENB
1
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0
PCA0CN
PCA0CPLn
CC
FR
PCA0CPHn
CCC
CCC
FFF
2 1 0
0 0 x
Enable
16-bit Comparator
PCA
Timebase
PCA0L
Match
0
1
PCA0H
Figure 19.5. PCA Software Timer Mode Diagram
Rev. 1.7
197
C8051F330/1/2/3/4/5
19.2.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the HighSpeed Output mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MPN n n n F
6 n n n
n
n
ENB
1
x
0 0
0 x
PCA Interrupt
PCA0CN
PCA0CPLn
Enable
CC
FR
PCA0CPHn
16-bit Comparator
Match
CC
CC
F F
2 1
C
C
F
0
0
1
TOGn
Toggle
PCA
Timebase
0 CEXn
1
PCA0L
Crossbar
PCA0H
Figure 19.6. PCA High-Speed Output Mode Diagram
198
Rev. 1.7
Port I/O
C8051F330/1/2/3/4/5
19.2.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 19.3.
F PCA
F CEXn = ---------------------------------------2  PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 19.3. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register.
Write to
PCA0CPLn
0
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
ENB
1
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0 0
PCA0CPLn
8-bit Adder
PCA0CPHn
Adder
Enable
TOGn
Toggle
x
Enable
PCA Timebase
8-bit
Comparator
match
0 CEXn
1
Crossbar
Port I/O
PCA0L
Figure 19.7. PCA Frequency Output Mode
Rev. 1.7
199
C8051F330/1/2/3/4/5
19.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be
reset (see Figure 19.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,
PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high byte
(PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register
enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 19.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
256 – PCA0CPHn -
DutyCycle = -------------------------------------------------256
Equation 19.4. 8-Bit PWM Duty Cycle
Using Equation 19.4, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
Write to
PCA0CPLn
0
PCA0CPHn
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 x 0
PCA0CPLn
x
Enable
8-bit
Comparator
match
S
R
PCA Timebase
SET
CLR
Q
CEXn
Q
PCA0L
Overflow
Figure 19.8. PCA 8-Bit PWM Mode Diagram
200
Rev. 1.7
Crossbar
Port I/O
C8051F330/1/2/3/4/5
19.2.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted
low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn
register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help
synchronize the capture/compare register writes. The duty cycle for 16-Bit PWM Mode is given by
Equation 19.5.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
65536 – PCA0CPn DutyCycle = ---------------------------------------------------65536
Equation 19.5. 16-Bit PWM Duty Cycle
Using Equation 19.5, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P ECCMT P E
WC A A A OWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
1
0 0 x 0
PCA0CPHn
PCA0CPLn
x
Enable
16-bit Comparator
match
S
R
PCA Timebase
PCA0H
SET
CLR
Q
CEXn
Crossbar
Port I/O
Q
PCA0L
Overflow
Figure 19.9. PCA 16-Bit PWM Mode
19.3. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Module 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled.
Rev. 1.7
201
C8051F330/1/2/3/4/5
19.3.1. Watchdog Timer Operation
While the WDT is enabled:
•
•
•
•
•
•
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 19.10).
PCA0MD
CWW
I DD
DT L
L E C
K
CCCE
PPPC
SSSF
2 1 0
PCA0CPH2
Enable
PCA0CPL2
Write to
PCA0CPH2
8-bit Adder
8-bit
Comparator
PCA0H
Match
Reset
PCA0L Overflow
Adder
Enable
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled
202
Rev. 1.7
C8051F330/1/2/3/4/5
Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 19.6, where PCA0L is the value of the PCA0L register
at the time of the update.
Offset =  256  PCA0CPL2  +  256 – PCA0L 
Equation 19.6. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
19.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
•
•
•
•
•
•
Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL2 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to ‘1’.
Write a value to PCA0CPH2 to reload the WDT.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 19.6, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 19.4 lists some example timeout intervals for typical system clocks.
Rev. 1.7
203
C8051F330/1/2/3/4/5
Table 19.4. Watchdog Timer Timeout Intervals1
System Clock (Hz)
24,500,000
24,500,000
24,500,000
18,432,000
18,432,000
18,432,000
11,059,200
11,059,200
11,059,200
3,062,5002
PCA0CPL2
255
128
32
255
128
32
255
128
32
255
Timeout Interval (ms)
32.1
16.2
4.1
42.7
21.5
5.5
71.1
35.8
9.2
257
3,062,5002
128
129.5
2
32
255
128
32
33.1
24576
12384
3168
3,062,500
32,000
32,000
32,000
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
19.5. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
204
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 19.1. PCA0CN: PCA Control
R/W
R/W
R
R
R
R/W
R/W
R/W
Reset Value
CF
CR
-
-
-
CCF2
CCF1
CCF0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xD8
Bit7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
Bit6:
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Bits5–3: UNUSED. Read = 000b, Write = don't care.
Bit2:
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit1:
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit0:
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Rev. 1.7
205
C8051F330/1/2/3/4/5
SFR Definition 19.2. PCA0MD: PCA Mode
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Reset Value
CIDL
WDTE
WDLCK
—
CPS2
CPS1
CPS0
ECF
01000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xD9
Bit7:
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Bit6:
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
Bit5:
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Bit4:
UNUSED. Read = 0b, Write = don't care.
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter.
CPS2
0
0
0
CPS1
0
0
1
CPS0
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8*
Reserved
Reserved
*Note: External oscillator source divided by 8 is synchronized with the system clock.
Bit0:
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Note: When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
206
Rev. 1.7
C8051F330/1/2/3/4/5
SFR Definition 19.3. PCA0CPMn: PCA Capture/Compare Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
PWM16n
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: PCA0CPM0: 0xDA, PCA0CPM1: 0xDB, PCA0CPM2: 0xDC
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PWM16n: 16-bit Pulse Width Modulation Enable.
This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1).
0: 8-bit PWM selected.
1: 16-bit PWM selected.
ECOMn: Comparator Function Enable.
This bit enables/disables the comparator function for PCA module n.
0: Disabled.
1: Enabled.
CAPPn: Capture Positive Function Enable.
This bit enables/disables the positive edge capture for PCA module n.
0: Disabled.
1: Enabled.
CAPNn: Capture Negative Function Enable.
This bit enables/disables the negative edge capture for PCA module n.
0: Disabled.
1: Enabled.
MATn: Match Function Enable.
This bit enables/disables the match function for PCA module n. When enabled, matches of
the PCA counter with a module's capture/compare register cause the CCFn bit in PCA0MD
register to be set to logic 1.
0: Disabled.
1: Enabled.
TOGn: Toggle Function Enable.
This bit enables/disables the toggle function for PCA module n. When enabled, matches of
the PCA counter with a module's capture/compare register cause the logic level on the
CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency
Output Mode.
0: Disabled.
1: Enabled.
PWMn: Pulse Width Modulation Mode Enable.
This bit enables/disables the PWM function for PCA module n. When enabled, a pulse width
modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is cleared; 16-bit
mode is used if PWM16n is set to logic 1. If the TOGn bit is also set, the module operates in
Frequency Output Mode.
0: Disabled.
1: Enabled.
ECCFn: Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Rev. 1.7
207
C8051F330/1/2/3/4/5
SFR Definition 19.4. PCA0L: PCA Counter/Timer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xF9
Bits 7–0: PCA0L: PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
SFR Definition 19.5. PCA0H: PCA Counter/Timer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
SFR Address: 0xFA
Bits 7–0: PCA0H: PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
SFR Definition 19.6. PCA0CPLn: PCA Capture Module Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address: PCA0CPL0: 0xFB, PCA0CPL1: 0xE9, PCA0CPL2: 0xEB
Bits7–0: PCA0CPLn: PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
SFR Definition 19.7. PCA0CPHn: PCA Capture Module High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: PCA0CPH0: 0xFC, PCA0CPH1: 0xEA, PCA0CPH2: 0xEC
Bits7–0: PCA0CPHn: PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
208
Rev. 1.7
C8051F330/1/2/3/4/5
20. C2 Interface
C8051F330/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash
programming and in-system debugging with the production part installed in the end application. The C2
interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information
between the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
20.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 20.1. C2ADD: C2 Address
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0: The C2ADD register is accessed via the C2 interface to select the target Data register for
C2 Data Read and Data Write commands.
Address
0x00
0x01
Description
Selects the Device ID register for Data Read instructions
Selects the Revision ID register for Data Read instructions
Selects the C2 Flash Programming Control register for Data
Read/Write instructions
Selects the C2 Flash Programming Data register for Data
Read/Write instructions
0x02
0xB4
C2 Register Definition 20.2. DEVICEID: C2 Device ID
Reset Value
00001010
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
This read-only register returns the 8-bit device ID: 0x0A (C8051F330/1/2/3/4/5).
Rev. 1.7
209
C8051F330/1/2/3/4/5
C2 Register Definition 20.3. REVID: C2 Revision ID
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
This read-only register returns the 8-bit revision ID: 0x00 (Revision A).
C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control
Reset Value
00000000
Bit7
Bits7–0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
FPCTL: Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2 Flash
programming, the following codes must be written in order: 0x02, 0x01. Note that once C2
Flash programming is enabled, a system reset must be issued to resume normal operation.
C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0: FPDAT: C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code
0x06
0x07
0x08
0x03
210
Command
Flash Block Read
Flash Block Write
Flash Page Erase
Device Erase
Rev. 1.7
C8051F330/1/2/3/4/5
20.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D (P2.0) pins. In most applications, external resistors are required to isolate C2 interface traffic from the user application. A typical isolation configuration is shown in Figure 20.1.
C8051Fxxx
/Reset (a)
C2CK
Input (b)
C2D
Output (c)
C2 Interface Master
Figure 20.1. Typical C2 Pin Sharing
The configuration in Figure 20.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
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DOCUMENT CHANGE LIST
Revision 1.3 to Revision 1.4
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Removed references to C8051F330D throughout the data sheet because the 'F330D device is functionally identical to the C8051F330 device (these two part numbers differ by package type only).
Updated titles of Chapters 5, 6, and 7 to show supported devices.
Updated Table 1.1, “Product Selection Guide,” on page 18.
- Added ordering part number information for lead-free parts.
Added Table 3.2, “Index to Electrical Characteristics Tables,” on page 34
Added Table 11.2, “Flash Security Summary,” on page 106 for clarity, replacing the Flash security summaries text.
Revision 1.4 to Revision 1.5
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Updated Table 3.1 - Added supply current data from characterization.
Updated Table 5.1 - Added MIN/MAX numbers for ADC Offset and Full Scale Error.
Fixed SFR Definition 8.2 - Typo in bit descriptions - “2-0” changed to “3-0”.
Fixed SFR Definition 9.4 - Text at bottom of figure was cut off.
Added Section “11.4. Flash Write and Erase Guidelines” on page 107.
Fixed Section “12. External RAM” on page 111, paragraph 2 - Typo in description - “upper 6-bits”
changed to “upper 7 bits”.
Fixed text in Section “19.3.2. Watchdog Timer Usage” on page 203 to read “256 PCA clock cycles,
or 3072 system clock cycles”.
Changed Table 19.4, Note 2 to refer to SYSCLK reset frequency = Internal Oscillator / 8.
Fixed Equation 19.6, “Watchdog Timer Offset in PCA Clocks,” - Typo in equation - “PCA0CPL4”
changed to “PCA0CPL2”.
Revision 1.5 to Revision 1.6
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Updated package drawings.
Revision 1.6 to Revision 1.7
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212
Removed PDIP package information.
Rev. 1.7
C8051F330/1/2/3/4/5
NOTES:
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