FDB14AN06LA0 / FDP14AN06LA0
N-Channel PowerTrench® MOSFET
60V, 60A, 14.6mΩ
Features
Applications
• r DS(ON) = 12.8mΩ (Typ.), VGS = 5V, ID = 60A
• Motor / Body Load Control
• Qg(tot) = 24nC (Typ.), VGS = 5V
• ABS Systems
• Low Miller Charge
• Powertrain Management
• Low QRR Body Diode
• Injection Systems
• UIS Capability (Single Pulse and Repetitive Pulse)
• DC-DC converters and Off-line UPS
• Qualified to AEC Q101
• Distributed Power Architectures and VRMs
Formerly developmental type 83557
• Primary Switch for 12V and 24V systems
D
DRAIN
(FLANGE)
SOURCE
GATE
DRAIN
G
GATE
SOURCE
TO-220AB
FDP SERIES
TO-263AB
FDB SERIES
DRAIN
(FLANGE)
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
60
Units
V
VGS
Gate to Source Voltage
±20
V
Drain Current
ID
Continuous (TC = 25oC, VGS = 10V)
67
A
Continuous (TC = 25oC, VGS = 5V)
60
A
10
A
Continuous (TA = 25oC, VGS = 5V, RθJA = 43oC/W)
Pulsed
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Figure 4
A
46
mJ
Power dissipation
125
W
Derate above 25oC
0.83
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-220,TO-263
1.2
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-220,TO-263 (Note 2)
62
o
C/W
RθJA
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
o
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2004 Fairchild Semiconductor Corporation
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
January 2004
Device Marking
FDB14AN06LA0
Device
FDB14AN06LA0
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
FDP14AN06LA0
FDP14AN06LA0
TO-220AB
Tube
N/A
50 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
60
-
-
V
-
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
-
3
V
V DS = 50V
VGS = 0V
TC = 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
ID = 67A, VGS = 10V
-
0.0102 0.0116
ID = 60A, VGS = 5V
-
0.0128 0.0146
ID = 60A, VGS = 5V,
TJ = 175oC
-
0.028
0.033
-
2900
-
-
270
-
pF
-
115
-
pF
24
31
nC
-
3.0
3.9
nC
-
12
-
nC
-
9.1
-
nC
-
7.9
-
nC
ns
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 5V
VGS = 0V to 5V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 1V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
V DS = 25V, VGS = 0V,
f = 1MHz
VDD = 30V
ID = 60A
Ig = 1.0mA
pF
Switching Characteristics (VGS = 5V)
tON
Turn-On Time
-
-
276
td(ON)
Turn-On Delay Time
-
15
-
ns
tr
Rise Time
-
169
-
ns
td(OFF)
Turn-Off Delay Time
-
24
-
ns
tf
Fall Time
-
50
-
ns
tOFF
Turn-Off Time
-
-
109
ns
V
V DD = 30V, ID = 60A
VGS = 5V, RGS = 5.1Ω
Drain-Source Diode Characteristics
ISD = 60A
-
-
1.25
ISD = 30A
-
-
1.0
V
Reverse Recovery Time
ISD = 60A, dISD/dt = 100A/µs
-
-
33
ns
Reverse Recovered Charge
ISD = 60A, dISD/dt = 100A/µs
-
-
29
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 40µH, I AS = 48A.
2: Pulse width = 100s.
©2004 Fairchild Semiconductor Corporation
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
Package Marking and Ordering Information
1.2
80
VGS = 10V
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
60
VGS = 5V
40
20
0.2
0
0
25
50
75
100
150
125
0
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TC = 25oC
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
VGS = 10V
150
VGS = 5V
100
50
10-5
10-4
10-3
10-2
10 -1
100
101
t , PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2004 Fairchild Semiconductor Corporation
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
Typical Characteristics TC = 25°C unless otherwise noted
1000
500
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10µs
100
100µs
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
DC
1
SINGLE PULSE
TJ = MAX RATED
TC = 25o C
100
STARTING TJ = 25o C
10
STARTING TJ = 150oC
1
0.1
1
10
0.001
100
0.01
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
1
10
Figure 6. Unclamped Inductive Switching
Capability
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
125
ID, DRAIN CURRENT (A)
125
100
75
TJ = 25oC
50
TJ = 175oC
VGS = 5V
TC = 25oC
VGS = 10V
100
VGS = 4V
75
50
25
25
TJ = -55oC
0
2.0
VGS = 3V
0
2.5
3.0
3.5
4.0
4.5
0
5.0
0.5
VGS , GATE TO SOURCE VOLTAGE (V)
1.0
1.5
2.0
2.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
13
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE(mΩ)
100
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
150
ID , DRAIN CURRENT (A)
0.1
tAV, TIME IN AVALANCHE (ms)
12
VGS = 5V
11
10
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
VGS = 5V, ID = 60A
9
0
20
40
60
80
ID, DRAIN CURRENT (A)
Figure 9. Drain to Source On Resistance vs Drain
Current
©2004 Fairchild Semiconductor Corporation
0.5
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
Typical Characteristics TC = 25°C unless otherwise noted
1.4
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.0
0.8
0.6
0.4
0.2
1.1
1.0
0.9
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (o C)
200
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
5000
10
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 30V
C, CAPACITANCE (pF)
CISS = CGS + CGD
1000
COSS ≅ C DS + C GD
CRSS = CGD
100
VGS = 0V, f = 1MHz
50
0.1
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 60A
ID = 10A
2
0
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2004 Fairchild Semiconductor Corporation
60
0
10
20
30
Qg, GATE CHARGE (nC)
40
50
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
Typical Characteristics TC = 25°C unless otherwise noted
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
IAS
+
RG
REQUIRED PEAK IAS
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS
VGS = 5V
+
Qgs2
VDD
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2004 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
Test Circuits and Waveforms
(T
–T )
JM
A
P D M = ----------------------------R θ JA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (o C/W)
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2 )
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
R
θ JA
128
( 1.69 + Area )
= 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
©2004 Fairchild Semiconductor Corporation
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
Thermal Resistance vs. Mounting Pad Area
.SUBCKT FDP14AN06LA0 2 1 3 ;
Ca 12 8 1.8e-9
Cb 15 14 1.8e-9
Cin 6 8 3e-9
rev January 2004
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
5
51
EVTHRES
+ 19 8
+
LGATE
GATE
1
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
Ebreak 11 7 17 18 64.8
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
Lgate 1 9 7.4e-9
Ldrain 2 5 1.00e-9
Lsource 3 7 3e-9
LSOURCE
CIN
8
7
SOURCE
3
RSOURCE
RLSOURCE
RLgate 1 9 74
RLdrain 2 5 10
RLsource 3 7 30
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
14
13
S1B
CA
15
17
18
RVTEMP
S2B
13
CB
6
8
5
8
EDS
-
19
VBAT
+
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 4.1e-3
Rgate 9 20 2.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 4e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RBREAK
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),3))}
.MODEL DbodyMOD D (IS=1.7e-11 RS=2.8e-3 N=1.05 TRS1=1.5e-3 TRS2=1e-6
+ CJO=1e-9 TT=1.9e-8 M=0.58 IKF=15.00 XTI=3)
.model dbreakmod d (RS=1e-1 TRS1=1.12e-3 TRS2=1.25e-6)
.MODEL DplcapMOD D (CJO=8e-10 IS=1e-30 N=10 M=0.57)
.MODEL MmedMOD NMOS (VTO=1.96 KP=8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.7)
.MODEL MstroMOD NMOS (VTO=2.42 KP=105 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.6 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1)
.MODEL RbreakMOD RES (TC1=9.2e-4 TC2=-3.55e-7)
.MODEL RdrainMOD RES (TC1=1e-2 TC2=3e-5)
.MODEL RSLCMOD RES (TC1=2.8e-3 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.7e-3 TC2=-9.5e-6)
.MODEL RvtempMOD RES (TC1=-2.3e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2004 Fairchild Semiconductor Corporation
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
PSPICE Electrical Model
REV January 2004
template FDP14AN06LA0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.7e-11,rs=2.8e-3,nl=1.05,trs1=1.5e-3,trs2=1e-6,cjo=1e-9,tt=1.9e-8,m=0.58,ikf=15.00,xti=3)
dp..model dbreakmod = (rs=1e-1,trs1=1.12e-3,trs2=1.25e-6)
dp..model dplcapmod = (cjo=8e-10,isl=10e-30,nl=10,m=0.57)
m..model mmedmod = (type=_n,vto=1.96,kp=8,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.42,kp=105,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.6,kp=0.04,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
DPLCAP
5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2.5,voff=-0.5) 10
RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2.5)
RSLC1
51
c.ca n12 n8 = 1.8e-9
RSLC2
c.cb n15 n14 = 1.8e-9
ISCL
c.cin n6 n8 = 3e-9
spe.ebreak n11 n7 n17 n18 = 64.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
EVTEMP
RGATE +
18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
DRAIN
2
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 7.4e-9
l.ldrain n2 n5 = 1.00e-9
l.lsource n3 n7 = 3e-9
S2A
14
13
13
8
S1B
CA
res.rlgate n1 n9 = 74
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 30
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=9.2e-4,tc2=-3.5e-7
res.rdrain n50 n16 = 4.1e-3, tc1=1e-2,tc2=3e-5
res.rgate n9 n20 = 2.7
res.rslc1 n5 n51 = 1e-6, tc1=2.8e-3,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4e-3, tc1=4.0e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.7e-3,tc2=-9.5e-6
res.rvtemp n18 n19 = 1, tc1=-2.3e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/200))** 3))
}
©2004 Fairchild Semiconductor Corporation
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
SABER Electrical Model
th
JUNCTION
REV January 2004
FDP14AN06LA0T
CTHERM1 TH 6 2.5e-3
CTHERM2 6 5 3e-3
CTHERM3 5 4 4e-3
CTHERM4 4 3 7e-3
CTHERM5 3 2 8.2e-3
CTHERM6 2 TL 5e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 4.2e-2
RTHERM2 6 5 8.4e-2
RTHERM3 5 4 1.04e-1
RTHERM4 4 3 1.14e-1
RTHERM5 3 2 2.74e-1
RTHERM6 2 TL 3.44e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDP14AN06LA0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =2.5e-3
ctherm.ctherm2 6 5 =3e-3
ctherm.ctherm3 5 4 =4e-3
ctherm.ctherm4 4 3 =7e-3
ctherm.ctherm5 3 2 =8.2e-3
ctherm.ctherm6 2 tl =5e-2
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
rtherm.rtherm1 th 6 =4.2e-2
rtherm.rtherm2 6 5 =8.4e-2
rtherm.rtherm3 5 4 =1.04e-1
rtherm.rtherm4 4 3 =1.14e-1
rtherm.rtherm5 3 2 =2.74e-1
rtherm.rtherm6 2 tl =3.44e-1
}
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2004 Fairchild Semiconductor Corporation
CASE
FDB14AN06LA0 / FDP14AN06LA0 Rev. B
FDB14AN06LA0 / FDP14AN06LA0
SPICE Thermal Model
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Rev. I7