Features • 3.0V to 3.6V Operating Range • Advanced, High-speed, Electrically-erasable Programmable Logic Device • • • • • • • • • • • • – Superset of 22V10 – Enhanced Logic Flexibility – Architecturally Compatible with ATV750B and ATV750 Software and Hardware D- or T-type Flip-flop Product Term or Direct Input Pin Clocking 15 ns Maximum Pin-to-pin Delay with 3V Operation Highest Density Programmable Logic Available in 24-pin Package – Advanced Electrically-erasable Technology – Reprogrammable – 100% Tested Increased Logic Flexibility – 42 Array Inputs, 20 Sum Terms and 20 Flip-flops Enhanced Output Logic Flexibility – All 20 Flip-flops Feed Back Internally – 10 Flip-flops are also Available as Outputs Programmable Pin-keeper Circuits Dual-in-line and Surface Mount Package in Standard Pinouts Commercial and Industrial Temperature Ranges 20-year Data Retention 2000V ESD Protection 1000 Erase/Write Cycles High-speed Complex Programmable Logic Device ATF750LVC Block Diagram (OE PRODUCT TERMS) PROGRAMMABLE INTERCONNECT AND COMBINATORIAL LOGIC ARRAY 12 INPUT PINS LOGIC OPTION 4 TO 8 PRODUCT TERMS 10 I/O PINS OUTPUT OPTION (UP T0 20 FLIP-FLOPS) (CLOCK PIN) Description The Atmel “750” architecture is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. The ATF750LVC is a high-performance Clock IN Logic Inputs I/O Bi-directional Buffers GND Ground VCC Note: 3V Supply For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN PLCC IN IN CLK/IN VCC * VCC I/O I/O CLK DIP/SOIC/TSSOP IN IN IN GND * IN IN IN 4 3 2 1 28 27 26 Function 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 Pin Name (continued) IN IN GND GND * IN I/O I/O Pin Configurations I/O I/O I/O GND * I/O I/O I/O Rev. 1447D–03/01 1 CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. Each of the ATF750LVC’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flipflops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 4.6V for pulses of less than 20 ns. Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +4.6V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. DC and AC Operating Conditions 3.3V Operation Commercial Industrial Operating Temperature (Ambient) 0°C - 70°C -40°C - +85°C VCC Power Supply 3.0 - 3.6V 3.0 -=3.6V 2 ATF750LVC ATF750LVC Clock Mux CKMUX CKi CLOCK PRODUCT TERM CLK PIN TO LOGIC CELL SELECT Output Options Bus-friendly Pin-keeper Input and I/Os All input and I/O pins on the ATF750LVC(L) have programmable “pin-keeper” circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. Please refer to the software compiler table for more details. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os. Table 1. Software Compiler Mode Selection Input Diagram VCC INPUT 100K ESD PROTECTION CIRCUIT PROGRAMMABLE OPTION I/O Diagram VCC OE Synario Wincupl Pin-keeper Circuit ATF750LVC V750C Disabled ATF750LVC (PPK) V750CPPK Enabled DATA I/O VCC 100K PROGRAMMABLE OPTION 3 DC Characteristics Symbol Parameter Condition ILI Input Load Current ILO Max Units VIN = -0.1V to VCC + 1V 10 µA Output Leakage Current VOUT = -0.1V to VCC + 0.1V 10 µA ICC Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open IOS(1)(2) Output Short Circuit Current VOUT = 0.5V VIL Input Low Voltage 3.0 ≤ VCC ≤ 3.6V VIH Input High Voltage VOL Output Low Voltage VOH Notes: VIN = VIH or VIL, VCC = Min Output High Voltage VIN = VIH or VIL, VCC = Min Min Typ Com. 65 90 mA Ind. 70 100 mA -120 mA -0.6 0.8 V 2.0 VCC + 0.75 V C-15 IOL = 16 mA Com., Ind. 0.5 V IOL = 12 mA Mil. 0.5 V IOL = 24 mA Com. 0.8 V IOH = -2.0 mA 2.4 V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. This test is performed at initial characterisation only. Input Test Waveforms and Measurement Levels Output Test Load VCC 316 Ω 348 Ω tR, tF < 3 ns (10% to 90%) 4 ATF750LVC ATF750LVC AC Waveforms, Product Term Clock(1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics, Product Term Clock(1) -15 Symbol Parameter tPD Max Units Input or Feedback to Non-registered Output 15 ns tEA Input to Output Enable 15 ns tER Input to Output Disable 15 ns tCO Clock to Output 5 12 ns tCF Clock to Feedback 5 9 ns tS Input Setup Time 8 ns tSF Feedback Setup Time 7 ns tH Hold Time 5 ns tP Clock Period 14 ns tW Clock Width 7 ns fMAX Min External Feedback 1/(tS + tCO) 50 MHz Internal Feedback 1/(tSF + tCF) 62 MHz No Feedback 1/(tP) 71 MHz tAW Asynchronous Reset Width 15 ns tAR Asynchronous Reset Recovery Time 15 ns tAP Asynchronous Reset to Registered Output Reset tSP Setup Time, Synchronous Preset Note: 15 8 ns ns 1. See ordering information for valid part numbers. 5 AC Waveforms, Input Pin Clock(1) Notes: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics, Input Pin Clock -15 Symbol Parameter tPD Max Units Input or Feedback to Non-registered Output 15 ns tEA Input to Output Enable 15 ns tER Input to Output Disable 15 ns tCOS Clock to Output 0 10 ns tCFS Clock to Feedback 0 5.5 ns tSS Input Setup Time 8 ns tSFS Feedback Setup Time 7 ns tHS Hold Time 0 ns tPS Clock Period 12 ns tWS Clock Width 6 ns fMAXS Min External Feedback 1/(tSS + tCOS) 55 MHz Internal Feedback 1/(tSFS + tCFS) 80 MHz No Feedback 1/(tPS) 83 MHz tAW Asynchronous Reset Width 15 ns tARS Asynchronous Reset Recovery Time 15 ns tAP Asynchronous Reset to Registered Output Reset tSPS Setup Time, Synchronous Preset 6 ATF750LVC 15 11 ns ns ATF750LVC Functional Logic Diagram ATF750LVC, Upper Half 7 Functional Logic Diagram ATF750LVC, Lower Half 8 ATF750LVC ATF750LVC Using the ATF750LVC’s Many Advanced Features Synchronous Preset and Asynchronous Reset The ATF750LVC’s advanced flexibility packs more usable gates into 24-pins than any other logic device. The ATF750LVCs start with the popular 22V10 architecture, and add several enhanced features: • Selectable D- and T-type Registers Each ATF750LVC flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. • Selectable Asynchronous Clocks Each of the ATF750LVC’s flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. • A Full Bank of Ten More Registers The ATF750LVC provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term. • Independent I/O Pin and Feedback Paths Each I/O pin on the ATF750LVC has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O’s output enable, facilitates true bi-directional I/O design. One synchronous preset line is provided for all 20 registers in the ATF750LVC. The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flipflops are reset when the input signals received force the internal resets high. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF750LVC fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during verify. The security fuse should be programmed last, as its effect is immediate. 9 OUTPUT SINK CURRENT VS SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C) 0.0 24.0 -1.0 23.0 -2.0 22.0 IOL (mA) IOH (mA) OUTPUT SOURCE CURRENT VS SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C) -3.0 -4.0 -5.0 21.0 20.0 19.0 18.0 -6.0 17.0 -7.0 16.0 -8.0 3.00 3.25 3.30 3.50 3.00 3.60 3.25 3.30 3.50 3.60 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) INPUT CURRENT VS INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) INPUT CLAMP CURRENT VS INPUT VOLTAGE (VCC = 3.3V, T A = 25°C) 0.0 15.0 INPUT CURRENT (mA) INPUT CURRENT (µA) -10.0 10.0 5.0 0.0 -5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40.0 -50.0 -60.0 SUPPLY CURRENT VS SUPPLY VOLTAGE (T A = 25°C) 70.0 60.0 50.0 40.0 30.0 3.0 3.3 SUPPLY VOLTAGE (V) ATF750LVC 0.0 -0.2 -0.4 -0.6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) ICC (mA) -30.0 -70.0 -10.0 10 -20.0 3.6 -0.8 -1.0 ATF750LVC OUTPUT SOURCE SINK CURRENT VS OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) OUTPUT SOURCE CURRENT VS OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 80.0 0.0 70.0 -10.0 60.0 IOL (mA) IOH (mA) -20.0 -30.0 -40.0 50.0 40.0 30.0 -50.0 20.0 -60.0 10.0 0.0 -70.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 VOL (V) VOH (V) SUPPLY CURRENT VS INPUT FREQUENCY (VCC = 5.00V, TA = 25°C) ICC (mA) 80 40 0 0 5 10 15 20 50 75 100 FREQUENCY (MHz) 11 ATF750LVC Ordering Information tPD (ns) tCOS (ns) Ext. fMAXS (MHz) 15 10 55 Note: Ordering Code Package Operation Range ATF750LVC-15JC ATF750LVC-15PC ATF750LVC-15SC ATF750LVC-15XC(1) 28J 24P3 24S 24X(1) Commercial (0°C to 70°C) ATF750LVC-15JI ATF750LVC-15PI ATF750LVC-15SI ATF750LVC-15X(1)I 28J 24P3 24S 24X(1) Industrial (-40°C to 85°C) 1. Special order only; TSSOP package requires special thermal management. Using “C” Product for Industrial Because the VCC conditions are the same for commercial and industrial for 3.3V products, and there is only 15°C difference at the high end of the temperature range, there is very little risk in using “C” devices for industrial applications. Just de-rate ICC by 15%. Package Type 28J 28-Lead, Plastic J-leaded Chip Carrier (PLCC) 24P3 24-lead, 0.300’ Wide, Plastic Dual Inline Package (PDIP) 24S 24-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC) 24X* 24-lead, 0.173” Wide, Thin Shrink Small Outline (TSSOP) 12 ATF750LVC ATF750LVC Packaging Information 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AB 24P3, 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AF .045(1.14) X 45° PIN NO. 1 IDENTIFY .045(1.14) X 30° - 45° .456(11.6) SQ .450(11.4) .032(.813) .026(.660) .495(12.6) SQ .485(12.3) .050(1.27) TYP .300(7.62) REF SQ 1.27(32.3) 1.25(31.7) PIN 1 .012(.305) .008(.203) .266(6.76) .250(6.35) .430(10.9) SQ .390(9.91) .021(.533) .013(.330) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .022(.559) X 45° MAX (3X) .090(2.29) MAX 1.100(27.94) REF .200(5.06) MAX .005(.127) MIN SEATING PLANE .070(1.78) .020(.508) .023(.584) .014(.356) .151(3.84) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .040(1.02) .325(8.26) .300(7.62) .012(.305) .008(.203) 0 REF 15 .400(10.2) MAX 24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) 24X, 24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP) Dimensions in Millimeters and (Inches)* .020(.508) .013(.330) .299(7.60) .420(10.7) .291(7.39) .393(9.98) PIN 1 ID .050(1.27) BSC .616(15.6) .598(15.2) .105(2.67) .092(2.34) .012(.305) .003(.076) .013(.330) .009(.229) 0 REF 8 .050(1.27) .015(.381) *Controlling dimension: millimeters 13 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1447D–03/01/xM