DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE21RD4AEFA-6 (256M words × 72 bits, 2 Ranks) Features The EBE21RD4AEFA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA on the module board. • 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) • Power supply: VDD = 1.8V ± 0.1V • Data rate: 667Mbps (max.) • SSTL_18 compatible I/O • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Four internal banks for concurrent operation (components) • Burst length: 4, 8 • /CAS latency (CL): 3, 4, 5 • Auto precharge option for each burst access • Auto refresh and self refresh modes • Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation • 1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD) L EO Description Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. t uc od Pr This Product became EOL in November, 2006. Document No. E0739E11 (Ver. 1.1) Date Published February 2006 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2005-2006 EBE21RD4AEFA-6 Ordering Information Data rate Mbps (max.) Part number EBE21RD4AEFA-6E-E 667 Component 1 JEDEC speed bin* (CL-tRCD-tRP) Package 240-pin DIMM (lead-free) DDR2-667 (5-5-5) Contact pad Mounted devices Gold EDE5104AESK-6E-E Notes: 1. Module /CAS latency = component CL + 1. Pin Configurations Front side 1 pin EO 121 pin 64 pin 65 pin 120 pin 184 pin 185 pin 240 pin Back side Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 61 A4 121 VSS 181 VDD 2 VSS 62 VDD 122 DQ4 182 A3 3 DQ0 63 A2 123 DQ5 183 A1 4 DQ1 64 VDD 124 VSS 184 VDD 5 VSS 65 VSS 125 DQS9 185 CK0 6 /DQS0 66 VSS 126 /DQS9 186 /CK0 7 DQS0 67 VDD 127 VSS 187 VDD 8 VSS 68 NC/Par_In 9 DQ2 69 10 DQ3 70 11 VSS 71 12 DQ8 72 13 DQ9 73 14 VSS 74 15 /DQS1 75 VDD 16 DQS1 76 /CS1 17 VSS 77 ODT1 18 /RESET 78 VDD 19 NC 79 VSS 20 VSS 80 DQ32 21 DQ10 81 DQ33 22 DQ11 82 23 VSS 24 DQ16 25 L Pin No. 188 A0 129 128 DQ7 189 VDD A10 130 VSS 190 BA1 BA0 131 DQ12 191 VDD VDD 132 DQ13 192 /RAS /WE 133 VSS 193 /CS0 /CAS 134 DQS10 194 VDD 135 /DQS10 195 ODT0 136 VSS 196 A13 137 NC 197 VDD 138 NC 198 VSS 139 VSS 199 DQ36 140 DQ14 200 DQ37 141 DQ15 201 VSS VSS 142 VSS 202 DQS13 83 /DQS4 143 DQ20 203 /DQS13 84 DQS4 144 DQ21 204 VSS DQ17 85 VSS 145 VSS 205 DQ38 26 VSS 86 DQ34 146 DQS11 206 DQ39 27 /DQS2 87 DQ35 147 /DQS11 207 28 DQS2 88 VSS 148 VSS 208 29 VSS 89 DQ40 149 DQ22 209 2 t Data Sheet E0739E11 (Ver. 1.1) uc od Pr DQ6 VDD VSS DQ44 DQ45 EBE21RD4AEFA-6 Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 30 DQ18 90 DQ41 150 DQ23 210 VSS 31 DQ19 91 VSS 151 VSS 211 DQS14 32 VSS 92 /DQS5 152 DQ28 212 /DQS14 33 DQ24 93 DQS5 153 DQ29 213 VSS 34 DQ25 94 VSS 154 VSS 214 DQ46 35 VSS 95 DQ42 155 DQS12 215 DQ47 36 /DQS3 96 DQ43 156 /DQS12 216 VSS 37 DQS3 97 VSS 157 VSS 217 DQ52 38 VSS 98 DQ48 158 DQ30 218 DQ53 39 DQ26 99 DQ49 159 DQ31 219 VSS EO 40 DQ27 100 VSS 160 VSS 220 NC 41 VSS 101 SA2 161 CB4 221 NC 42 CB0 102 NC 162 CB5 222 VSS 43 CB1 103 VSS 163 VSS 223 DQS15 44 VSS 104 /DQS6 164 DQS17 224 /DQS15 45 /DQS8 105 DQS6 165 /DQS17 225 VSS DQS8 106 VSS 166 VSS 226 DQ54 47 VSS 107 DQ50 167 CB6 227 DQ55 48 CB2 DQ51 168 CB7 228 VSS L 46 108 49 CB3 109 VSS 169 VSS 229 DQ60 50 VSS 110 DQ56 170 VDD 230 DQ61 51 VDD 111 DQ57 171 CKE1 231 VSS 52 CKE0 112 53 VDD 113 54 NC 114 55 NC/Err_Out 115 56 VDD 116 57 A11 117 58 A7 118 VSS 59 VDD 119 SDA 60 A5 120 SCL 172 VDD 232 DQS16 173 NC 233 /DQS16 DQS7 174 NC 234 VSS Pr VSS /DQS7 VSS 175 VDD 235 DQ62 DQ58 176 A12 236 DQ63 DQ59 177 A9 237 VSS od 178 VDD 238 VDDSPD 179 A8 239 SA0 180 A6 240 SA1 t uc Data Sheet E0739E11 (Ver. 1.1) 3 EBE21RD4AEFA-6 Pin Description Pin name Function A0 to A13 Address input Row address Column address A10 (AP) Auto precharge BA0, BA1 Bank select address DQ0 to DQ63 Data input/output A0 to A13 A0 to A9, A11 Check bit (Data input/output) /RAS Row address strobe command /CAS Column address strobe command /WE Write enable /CS0, /CS1 Chip select CKE0, CKE1 Clock enable CK0 Clock input /CK0 Differential clock input DQS0 to DQS17, /DQS0 to /DQS17 Input and output data strobe EO CB0 to CB7 SCL Clock input for serial PD SDA Data input/output for serial PD VDD VDDSPD VREF L SA0 to SA2 VSS Power for internal circuit Power for serial EEPROM Input reference voltage Ground /RESET ODT control Reset pin (forces register and PLL inputs low) * 2 Err_Out* Pr ODT0, ODT1 Par_In* Serial address input 1 Parity bit for the address and control bus 2 NC Parity error found on the address and control bus No connection t uc od Notes: 1. Reset pin is connected to both OE of PLL and reset to register. 2. NC/Err_Out (Pin No. 55) and NC/Par_In (Pin No. 68) are for optional function to check address and command parity. Data Sheet E0739E11 (Ver. 1.1) 4 EBE21RD4AEFA-6 Serial PD Matrix*1 Byte No. Function described 0 1 Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 80H 128 bytes 0 0 0 0 1 0 0 0 08H 256 bytes 2 Memory type 0 0 0 0 1 0 0 0 08H DDR2 SDRAM 3 Number of row address 0 0 0 0 1 1 1 0 0EH 14 4 Number of column address 0 0 0 0 1 0 1 1 0BH 11 5 Number of DIMM ranks 0 1 1 0 0 0 0 1 61H 2 6 Module data width 0 1 0 0 1 0 0 0 48H 72 7 Module data width continuation 0 0 0 0 0 0 0 00H 0 Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H SSTL 1.8V 9 DDR SDRAM cycle time, CL = 5 0 0 1 1 0 0 0 0 30H 3.0ns* 10 SDRAM access from clock (tAC) 0 1 0 0 0 1 0 1 45H 0.45ns* 11 DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC 12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs EO 0 8 Primary SDRAM width 0 0 0 0 0 1 0 0 04H ×4 14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04H ×4 Reserved 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 1 1 0 0 0CH 4,8 0 0 0 0 0 1 0 0 04H 4 0 0 1 1 1 0 0 0 38H 3, 4, 5 15 16 17 18 L 13 Pr SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency 1 1 DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1 01H 4.00mm max. 20 DIMM type information 0 0 0 0 0 0 0 1 01H Registered 21 SDRAM module attributes 0 0 0 0 0 0 0 0 00H Normal 22 SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H Weak Driver 50Ω ODT Support 23 Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1 3DH 3.75ns* 24 Maximum data access time (tAC) from clock at CL = 4 0 1 25 Minimum clock cycle time at CL = 3 0 1 26 Maximum data access time (tAC) from clock at CL = 3 0 1 27 Minimum row precharge time (tRP) 0 0 28 Minimum row active to row active delay 0 (tRRD) 0 29 Minimum /RAS to /CAS delay (tRCD) 0 30 Minimum active to precharge time (tRAS) Module rank density 32 33 1 0 0 0 0 50H 0.5ns* 1 0 1 0 0 0 0 50H 5.0ns* 1 1 0 0 0 0 0 60H 0.6ns* 1 1 1 1 1 0 0 3CH 15ns 0 1 1 1 1 0 1EH 7.5ns 0 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 Data input setup time before clock (tDS) 0 0 0 1 0 0 Address and command setup time before clock (tIS) Address and command hold time after clock (tIH) Data Sheet E0739E11 (Ver. 1.1) 5 0 0 3CH 15ns 0 1 2DH 45ns 0 1 01H 1GB 0 0 20H 0.20ns* 1 0 0 28H 0.28ns* 1 0 0 10H t 34 0 1 uc 31 od 19 0.10ns* 1 EBE21RD4AEFA-6 Byte No. Function described 35 36 37 38 39 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments Data input hold time after clock (tDH) 0 0 0 1 1 0 0 0 18H 0.18ns* Write recovery time (tWR) 0 1 1 1 1 0 0 3CH 15ns* 0 0 1 1 1 1 0 1EH 7.5ns* 1 0 0 1 1 1 1 0 1EH 7.5ns* 1 0 0 0 0 0 0 0 00H TBD 0 Internal write to read command delay 0 (tWTR) Internal read to precharge command 0 delay (tRTP) Memory analysis probe 0 characteristics 1 1 Extension of Byte 41 and 42 0 0 0 0 0 0 0 0 00H Undefined 41 Active command period (tRC) 0 0 1 1 1 1 0 0 3CH 60ns* 42 Auto refresh to active/ Auto refresh command cycle (tRFC) 0 1 1 0 1 0 0 1 69H 105ns* 43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H 8ns* 44 Dout to DQS skew 0 0 0 1 1 0 0 0 18H 0.24ns* 1 45 Data hold skew (tQHS) 0 0 1 0 0 0 1 0 22H 0.34ns* 1 46 PLL relock time 0 0 0 0 1 1 1 1 0FH 15µs 0 0 0 0 0 0 0 0 00H EO 40 47 to 61 1 1 1 SPD Revision 0 0 0 1 0 0 1 0 12H 63 Checksum for bytes 0 to 62 0 0 0 0 1 1 1 0 0EH 64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation code 66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory 67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H 72 Manufacturing location 73 Module part number 74 Module part number 75 Module part number 76 Module part number 77 Module part number 78 Module part number 79 L 62 Rev. 1.2 (ASCII-8bit code) Pr 1 0 0 0 1 0 1 45H E 0 1 0 0 0 0 1 0 42H B 0 1 0 0 0 1 0 1 45H E 0 0 1 1 0 0 1 0 32H 2 0 0 1 1 0 0 0 1 31H 1 0 1 0 1 0 0 1 0 52H R Module part number 0 1 0 0 0 1 0 0 44H D 80 Module part number 0 0 1 1 0 1 0 0 34H 4 81 Module part number 0 1 0 0 0 0 0 1 41H A 82 Module part number 0 1 0 0 0 1 0 1 45H E 83 Module part number 0 1 0 0 0 1 1 0 46H F 84 Module part number 0 1 0 0 0 0 0 1 41H A 85 Module part number 0 0 1 0 1 1 86 Module part number 0 0 1 1 0 1 87 Module part number 0 1 0 0 0 1 88 Module part number 0 0 1 0 1 1 89 Module part number 0 1 0 0 0 1 90 Module part number 0 0 1 0 0 0 uc od 0 0 1 2DH — 1 0 36H 6 0 1 45H E 0 1 2DH — 0 1 45H E 0 0 20H (Space) t Data Sheet E0739E11 (Ver. 1.1) 6 EBE21RD4AEFA-6 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 91 Revision code 0 0 1 1 0 0 0 0 30H Initial 92 Revision code 0 0 1 0 0 0 0 0 20H (Space) 93 Manufacturing date 94 Manufacturing date 95 to 98 Module serial number 99 to 127 Manufacture specific data Year code (BCD) Week code (BCD) Notes: 1. These specifications are defined based on component specification, not module. L EO t uc od Pr Data Sheet E0739E11 (Ver. 1.1) 7 EBE21RD4AEFA-6 Block Diagram VSS /RCS1 /RCS0 DQS0 /DQS0 RS RS DM /CS 4 RS DQ0 to DQ3 DQS1 /DQS1 DQ0 to DQ3 4 DQS10 RS DQ0 to DQ3 DM /CS DQS3 RS DQ0 to DQ3 4 DQS4 RS DQ0 to DQ3 4 RS DQ0 to DQ3 DQS11 DQS12 /DQS12 4 RS D3 DQS /DQS D4 4 RS DQ0 to DQ3 DQS16 DQ0 to DQ3 CKE1 /WE /ODT0 RS RS D25 DQS17 /DQS17 RS DQ0 to DQ3 DQS /DQS DM /CS DQ0 to DQ3 D8 D26 /RST WP A0 A1 A2 /RRAS -> /RAS: SDRAMs D0 to D35 SA0 SA1 SA2 /RCAS -> /CAS: SDRAMs D0 to D35 RCKE0 -> CKE: SDRAMs D0 to D17 VDDSPD RODT1 -> ODT: SDRAMs D18 to D35 /PCK7*3 CK0 /CK0 P L L /RESET OE DM /CS DQS /DQS DQ0 to DQ3 D31 D14 DM /CS DQS /DQS DQ0 to DQ3 D32 RS DM 4 /CS DQS /DQS DQ0 to DQ3 D15 DM /CS DQS /DQS DQ0 to DQ3 D33 RS RS /CS DQS /DQS DQ0 to DQ3 D16 DM /CS DQS /DQS DQ0 to DQ3 D34 RS RS 4 RS SDA /CS DQS /DQS DQ0 to DQ3 D17 DM /CS DQS /DQS DQ0 to DQ3 D35 D0 to D35: 512M bits DDR2 SDRAM U0: 2k bits EEPROM RS: 22Ω PLL: CUA877 Register: SSTUA32866 Serial PD D0 to D35 Notes: 1. DQ wring may be changed within a nibble. 2. /CS0 connects to D/CS and /CS1 connects to /CSR on D0 to D35 VREF register1 and register2. VSS D0 to D35 /CS1 connects to D/CS and /CS0 connects to /CSR on register3 and register4. 3. /RESET, PCK7 and /PCK7 connect to all registers. PCK0 to PCK6, PCK8, PCK9 -> CK: SDRAMs D0 to D35 CKE and /ODT connect to a register. /PCK0 to /PCK6, /PCK8, /PCK9 -> /CK: SDRAMs D0 to D35 Other signals connect to two of four registers. PCK7 -> CK: register /PCK7 -> /CK: register VDD RODT0 -> ODT: SDRAMs D0 to D17 RS SDA U0 RA0 to RA13 -> A0 to A13: SDRAMs D0 to D35 /RWE -> /WE: SDRAMs D0 to D35 RS SCL RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 RCKE1 -> CKE: SDRAMs D18 to D35 D13 /CS DQS /DQS DQ0 to DQ3 DM SCL D30 RS Serial PD /RCS1 -> /CS: SDRAMs D18 to D35 R E G I S T E R RS 4 DQS /DQS CB4 to CB7 CS DQS /DQS RS DM DQ60 to DQ63 DM DQ0 to DQ3 RS DQS /DQS /RCS0 -> /CS: SDRAMs D0 to D17 RS /RESET*3 PCK7*3 D7 D29 t /ODT1 RS RS DQ0 to DQ3 /CS DQS /DQS uc /CAS CKE0 4 RS RS DM /CS DQS /DQS RS DM /CS /RAS D24 RS DQS8 DQ52 to DQ55 D12 /CS DQS /DQS DQ0 to DQ3 DQS /DQS /DQS16 RS RS 4 RS DQ0 to DQ3 DM DQ0 to DQ3 RS 4 DM /CS /CS DQS /DQS DQ0 to DQ3 DM DQ44 to DQ47 D28 RS RS DQS /DQS D6 RS DQS /DQS D23 D11 od 4 DQ0 to DQ3 DQS15 RS /DQS8 A0 to A13 DQS14 /DQS14 /CS DQS /DQS RS DM D22 DM DQ0 to DQ3 RS DQS /DQS DQ36 to DQ39 D10 /CS DQS /DQS DQ0 to DQ3 DM /DQS15 DM /CS RS DQ0 to DQ3 DM /CS DQS /DQS D5 RS DQS7 BA0 to BA1 DM /CS RS 4 4 DQS13 D27 RS DQ28 to DQ31 D21 /CS DQS /DQS DQ0 to DQ3 DQS /DQS /DQS13 RS /DQS7 RS DQ0 to DQ3 /CS DQS /DQS RS Pr DQ0 to DQ3 DM /CS /CS0*2 /CS1*2 DM /CS DQS /DQS RS 4 DM DQ20 to DQ23 D20 DM DQ0 to DQ3 RS DQS /DQS RS DQS6 /DQS6 CB0 to CB3 DQ0 to DQ3 D2 RS DQ56 to DQ59 DM /CS DQS /DQS RS DM /CS DQ48 to DQ51 D19 /DQS11 L DM /CS DQ40 to DQ43 D1 D9 RS DM DQ12 to DQ15 /CS DQS /DQS DQ0 to DQ3 DQS /DQS RS RS /DQS4 DQS5 DQ0 to DQ3 RS DM /CS /DQS5 DM /CS DQS /DQS RS /DQS3 DQ32 to DQ35 DM RS 4 DQ4 to /DQ7 RS 4 RS DQS /DQS D18 /DQS10 EO DQS2 DQ24 to DQ27 DQ0 to DQ3 RS /DQS2 DQ16 to DQ19 DM /CS DQS /DQS D0 RS RS DM /CS DQ8 to DQ11 RS DQS9 /DQS9 Data Sheet E0739E11 (Ver. 1.1) 8 EBE21RD4AEFA-6 Differential Clock Net Wiring (CK0, /CK0) 0ns (nominal) SDRAM PLL 120Ω OUT1 SDRAM 120Ω CK0 IN EO /CK0 Register 1 C 120Ω C 120Ω Register 3 120Ω OUT'N' Feedback in Register 2 L C Feedback out Register 4 Pr Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. od 4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible. t uc Data Sheet E0739E11 (Ver. 1.1) 9 EBE21RD4AEFA-6 Electrical Specifications • All voltages are referenced to VSS (GND). Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT –0.5 to +2.3 V 1 Supply voltage relative to VSS VDD –0.5 to +2.3 V Short circuit output current IOS 50 mA Power dissipation PD 18 W 1 Operating case temperature TC 0 to +95 °C 1, 2 Storage temperature Tstg –55 to +100 °C 1 EO Notes: 1 DDR2 SDRAM component specification. 2. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of EMRS (2) bit A7 is required. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Parameter Supply voltage L DC Operating Conditions (TC = 0°C to +85°C) (DDR2 SDRAM Component Specification) Symbol min. typ. max. Unit Notes VDD, VDDQ 1.7 1.8 1.9 V 4 VSS 0 0 0 V VDDSPD 1.7 — 3.6 V Pr VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 2 Termination voltage VTT VREF − 0.04 VREF VREF + 0.04 V 3 DC input logic high VIH (DC) VREF + 0.125 VDDQ + 0.3V V DC input low VIL (DC) −0.3 VREF – 0.125 V AC input logic high VIH (AC) VREF + 0.200 V AC input low VIL (AC) VREF – 0.200 V od Input reference voltage Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ must be equal to VDD. t uc Data Sheet E0739E11 (Ver. 1.1) 10 EBE21RD4AEFA-6 DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V) Parameter Symbol Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Grade IDD0 3970 IDD1 4320 EO Precharge power-down standby current Precharge quiet standby current IDD2P 970 IDD2Q 1510 L Idle standby current IDD2N mA mA one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open; tCK = tCK (IDD); Fast PDN Exit CKE is L; MRS(12) = 0 Other control and address bus inputs are STABLE; Slow PDN Exit Data bus inputs are MRS(12) = 1 FLOATING all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 2050 mA IDD3P-S 1510 mA IDD3N 3160 IDD4R 5440 mA mA all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING t uc IDD4W 5620 od Operating current (Burst write operating) Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Pr Operating current (Burst read operating) 1870 Unit IDD3P-F Active power-down standby current Active standby current max Data Sheet E0739E11 (Ver. 1.1) 11 EBE21RD4AEFA-6 Parameter Symbol Auto-refresh current Self-refresh current IDD5 max 6790 IDD6 310 EO Operating current (Bank interleaving) Grade IDD7 7730 Unit Test condition mA tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA Self Refresh Mode; CK and /CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING mA all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 × tCK (IDD); CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W; Notes: 1. 2. 3. 4. L IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN ≤ VIL (AC) (max.) H is defined as VIN ≥ VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions. Pr od AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized. DDR2-667 Parameter 5-5-5 CL(IDD) 5 15 tRC(IDD) 60 tRRD(IDD) 7.5 tCK(IDD) 3 tRAS(min.)(IDD) 45 tRAS(max.)(IDD) 70000 tRP(IDD) 15 tRFC(IDD) 105 tCK ns ns ns uc tRCD(IDD) Unit ns ns ns ns ns t Data Sheet E0739E11 (Ver. 1.1) 12 EBE21RD4AEFA-6 DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) (DDR2 SDRAM Component Specification) Parameter Symbol Value Unit Notes Input leakage current ILI 2 µA VDD ≥ VIN ≥ VSS Output leakage current ILO 5 µA VDDQ ≥ VOUT ≥ VSS VTT + 0.603 V 5 VTT − 0.603 V 5 Output timing measurement reference level VOTR 0.5 × VDDQ V 1 Output minimum sink DC current IOL +13.4 mA 3, 4, 5 Output minimum source DC current IOH −13.4 mA 2, 4, 5 Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load EO Notes: 1. 2. 3. 4. 5. The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18Ω at TC = 25°C, VDD = VDDQ = 1.8V. DC Characteristics 3 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) L (DDR2 SDRAM Component Specification) Parameter min. max. AC differential input voltage VID (AC) 0.5 VDDQ + 0.6 V 1, 2 AC differential cross point voltage VIX (AC) 0.5 × VDDQ − 0.175 0.5 × VDDQ + 0.175 V 2 AC differential cross point voltage VOX (AC) 0.5 × VDDQ − 0.125 0.5 × VDDQ + 0.125 V 3 Pr Symbol Unit Note od Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as /CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) − VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross. VDDQ VTR Crossing point VID uc VIX or VOX VCP VSSQ Differential Signal Levels*1, 2 t Data Sheet E0739E11 (Ver. 1.1) 13 EBE21RD4AEFA-6 ODT DC Electrical Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) (DDR2 SDRAM Component Specification) Parameter Symbol min typ max Unit Notes Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω Rtt1(eff) 60 75 90 Ω 1 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω Rtt2(eff) 120 150 180 Ω 1 Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω Rtt3(eff) 40 50 60 Ω 1 Deviation of VM with respect to VDDQ/2 ∆VM −6 +6 % 1 Note: 1. Test condition for Rtt measurements. EO Measurement Definition for Rtt(eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), and VDDQ values defined in SSTL_18. Rtt(eff) = VIH(AC) − VIL(AC) I(VIH(AC)) − I(VIL(AC)) Measurement Definition for ∆VM Measure voltage (VM) at test pin (midpoint) with no load. L ∆VM = 2 × VM VDDQ − 1 × 100% OCD Default Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) (DDR2 SDRAM Component Specification) Output impedance Pull-up and pull-down mismatch Output slew rate Pr Parameter min typ max Unit Notes 12.6 18 23.4 Ω 1 0 4 Ω 1, 2 1.5 5 V/ns 3, 4 Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V) Parameter Pins min. Input capacitance CI1 Address, /RAS, /CAS, /WE, /CS, CKE, ODT 2.5 Input capacitance CI2 CK, /CK 2 Data and DQS input/output capacitance CO DQ, DQS, /DQS, CB 2.5 Notes: 1. Register component specification. 2. PLL component specification. 3. DDR2 SDRAM component specification. Data Sheet E0739E11 (Ver. 1.1) 14 max. Unit Notes 3.5 pF 1 3 pF 2 3.5 pF 3 t Symbol uc od Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. EBE21RD4AEFA-6 AC Characteristics (TC = 0°C to +85°C , VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V) (DDR2 SDRAM Component Specification) -6E Frequency (Mbps) 667 Parameter Symbol min. max. Unit /CAS latency CL 5 5 tCK Active to read or write command delay tRCD 15 ns Precharge command period tRP 15 ns Active to active/auto refresh command time tRC 60 ns DQ output access time from CK, /CK tAC −450 +450 ps Notes tDQSCK −400 +400 ps CK high-level width tCH 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 tCK CK half period tHP min. (tCL, tCH) ps Clock cycle time tCK 3000 8000 ps DQ and DM input hold time tDH 175 ps 5 DQ and DM input setup time tDS 100 ps 4 Control and Address input pulse width for each input tIPW 0.6 tCK DQ and DM input pulse width for each input tDIPW 0.35 tCK Data-out high-impedance time from CK,/CK tHZ tAC max. ps Data-out low-impedance time from CK,/CK tLZ tAC min. tAC max. ps DQS-DQ skew for DQS and associated DQ signals tDQSQ 240 ps DQ hold skew factor tQHS 340 ps tQH tHP – tQHS ps L EO DQS output access time from CK, /CK Pr DQ/DQS output hold time from DQS Write command to first DQS latching transition tDQSS WL − 0.25 WL + 0.25 tCK DQS input high pulse width tDQSH 0.35 tCK tDQSL 0.35 tCK tDSS 0.2 tCK DQS input low pulse width DQS falling edge to CK setup time od 0.2 tCK tMRD 2 tCK Write postamble tWPST 0.4 0.6 tCK Write preamble tWPRE 0.35 tCK Address and control input hold time tIH 275 ps 5 4 DQS falling edge hold time from CK tDSH Mode register set command cycle time tIS 200 ps Read preamble tRPRE 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 tCK Active to precharge command tRAS 45 70000 ns Active to auto-precharge delay tRAP tRCD min. ns Active bank A to active bank B command period tRRD 7.5 ns Write recovery time tWR 15 ns Auto precharge write recovery + precharge time tDAL (tWR/tCK)+ (tRP/tCK) tCK Internal write to read command delay tWTR 7.5 ns Internal read to precharge command delay tRTP 7.5 ns 15 1 t Data Sheet E0739E11 (Ver. 1.1) uc Address and control input setup time EBE21RD4AEFA-6 -6E Frequency (Mbps) 667 Parameter Symbol min. max. Unit Notes Exit self refresh to a non-read command tXSNR tRFC + 10 ns Exit self refresh to a read command tXSRD 200 tCK Exit precharge power down to any non-read command tXP 2 tCK Exit active power down to read command tXARD 2 tCK 3 Exit active power down to read command (slow exit/low power mode) tXARDS 7− AL tCK 2, 3 3 tCK Output impedance test driver delay tOIT 0 12 ns Auto refresh to active/auto refresh command time tRFC 105 ns Average periodic refresh interval (0°C ≤ TC ≤ +85°C) tREFI 7.8 µs tREFI 3.9 µs tDELAY tIS + tCK + tIH ns EO CKE minimum pulse width (high and low pulse width) tCKE (+85°C < TC ≤ +95°C) Minimum time clocks remains ON after CKE asynchronously drops low For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test. L Notes: 1. 2. 3. 4. CK /DQS Pr DQS /CK tDS tDH tDS tIS tDH tIH tIS tIH Input Waveform Timing 1 (tDS, tDH) od VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS Input Waveform Timing 2 (tIS, tIH) t uc Data Sheet E0739E11 (Ver. 1.1) 16 EBE21RD4AEFA-6 ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification) Parameter Symbol min max Unit ODT turn-on delay tAOND 2 2 tCK ODT turn-on tAON tAC(min) tAC(max) + 700 ps ODT turn-on (power down mode) tAONPD tAC(min) + 2000 2tCK + tAC(max) + 1000 ps ODT turn-off delay tAOFD 2.5 2.5 tCK ODT turn-off tAOF tAC(min) tAC(max) + 600 ps ODT turn-off (power down mode) tAOFPD tAC(min) + 2000 2.5tCK + tAC(max) + 1000 ps ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK Notes 1 2 EO Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. AC Input Test Conditions Symbol Value Unit Notes Input reference voltage VREF 0.5 × VDDQ V 1 Input signal maximum peak to peak swing VSWING(max.) 1.0 V 1 Input signal maximum slew rate SLEW 1.0 V/ns 2, 3 L Parameter Pr Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC) (min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions. Start of rising edge input timing Start of falling edge input timing VDDQ VIH (AC)(min.) od VIH (DC)(min.) VSWING(max.) VREF VIL (DC)(max.) VIL (AC)(max.) Falling slew = VSS ∆TR ∆TF VIH (DC)(min.) − VIL (AC)(max.) ∆TF Rising slew = VIH (AC) min. − VIL (DC)(max.) Measurement point DQ VTT RT =25 Ω Data Sheet E0739E11 (Ver. 1.1) 17 t Output Load ∆TR uc AC Input Test Signal Wave forms EBE21RD4AEFA-6 Pin Functions CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. EO /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A13 (input pins) Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9 and A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. L A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. [Bank Select Signal Table] Bank 0 BA0 BA1 L L H L Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. od Bank 1 Pr BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) H H DQ, CB (input and output pins) Data are input to and output from these pins. DQS (input and output pin) DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input). Data Sheet E0739E11 (Ver. 1.1) 18 t uc CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. EBE21RD4AEFA-6 VDD (power supply pins) 1.8V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 1.8V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. /RESET (input pin) LVCMOS reset input. When /RESET is Low, all registers are reset. EO Par_IN (Parity input pin) Parity bit for the address and control bus. Err_Out (Error output pin) Parity error found on the address and control bus. Detailed Operation Part and Timing Waveforms L Refer to the EDE5104AESK, EDE5108AESK datasheet (E0562E). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = component CL + 1 for registered type. t uc od Pr Data Sheet E0739E11 (Ver. 1.1) 19 EBE21RD4AEFA-6 Physical Outline Unit: mm 4.00 max 0.5 min 4.00 min (DATUM -A-) Component area (Front) 1 120 B A 1.27 ± 0.10 55.00 240 L FULL R 3.00 2.50 ± 0.20 Pr Detail A Detail B (DATUM -A-) 1.00 4.00 0.20 ± 0.15 4.00 Component area (Back) 30.00 121 17.80 133.35 10.00 EO 63.00 2.50 FULL R od 0.80 ± 0.05 3.80 5.00 1.50 ± 0.10 uc ECA-TS2-0093-01 t Data Sheet E0739E11 (Ver. 1.1) 20 EBE21RD4AEFA-6 CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES EO 1 PRECAUTION AGAINST ESD FOR MOS DEVICES 2 L Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES 3 od Pr No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. STATUS BEFORE INITIALIZATION OF MOS DEVICES uc Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 t Data Sheet E0739E11 (Ver. 1.1) 21 EBE21RD4AEFA-6 The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. EO [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. Pr If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 t uc od Data Sheet E0739E11 (Ver. 1.1) 22