ATMEL AT24C04B-W-11 Two-wire serial eeprom 4k (512 x 8) 8k (1024 x 8) Datasheet

Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 512 x 8 (4K), or 1024 x 8 (8K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
Write Protect Pin for Hardware Data Protection
16-byte Page (4K, 8K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-MAP (MLP 2x3), 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
• Lead-free/Halogen-free
• Die Sales: Wafer Form, Tape and Reel and Bumped Wafers
•
•
•
•
•
•
•
•
•
•
Description
The AT24C04B/08B provides 4096/8192 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 512/1024 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The AT24C04B/08B is
available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin MiniMAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is
accessed via a Two-wire serial interface. In addition, the AT24C04B/08B is available
in 1.8V (1.8V to 5.5V) version.
Table 0-1.
4K (512 x 8)
8K (1024 x 8)
AT24C04B
AT24C08B
Pin Configuration
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Two-wire
Serial EEPROM
Serial Clock Input
WP
Write Protect
NC
No Connect
GND
Ground
VCC
Power Supply
Note:
For use of 5-lead SOT23
4K: The software A2 and A1 bits in the device
address word must be set to zero to properly
communicate.
8K: The software A2 bit in the device address word
must be set to zero to properly communicate.
8-lead Ultra-Thin
Mini-MAP (MLP 2x3)
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
8-ball dBGA2
VCC
WP
SCL
SDA
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
1
GND
2
SDA
3
2 A1
6
3 A2
5
4 GND
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
VCC
WP
SCL
SDA
8
7
6
5
8-lead PDIP
5-lead SOT23
SCL
1 A0
7
Bottom View
8-lead TSSOP
A0
A1
A2
GND
8
5
WP
4
VCC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5226D–SEEPR–7/08
Absolute Maximum Ratings
Operating Temperature..................................–55°C to +125°C
*NOTICE:
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA
Figure 0-1.
Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A2
A1
A0
R/W
EN
H.V. PUMP/TIMING
COMP
LOAD
DATA RECOVERY
INC
DATA WORD
ADDR/COUNTER
Y DEC
X DEC
SCL
SDA
EEPROM
SERIAL MUX
DOUT/ACK
LOGIC
DIN
DOUT
2
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
1. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The AT24C04B uses the A2 and A1 inputs for hard wire addressing and a toal of four 4K devices
may be addressed on a single bus system. The A0 pin is a no connect and can be connected to
ground (device addressing is discussed in detail under the Device Addressing section).
The AT24C08B only uses the A2 input for hardware addressing and a total of two 8K devices
may be addressed on a single bus system. The A0 and A1 pins are no connects and can be
connected to ground (device addressing is discussed in detail under the Device Addressing
section).
Table 1-1.
Write Protect
Part of the Array Protected
WP Pin
Status
24C04B/08B
At VCC
Full Array
At GND
Normal Read/Write Operations
3
5226D–SEEPR–7/08
2. Memory Organization
AT24C04B, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K
requires an 9-bit data word address for random word addressing.
AT24C08B, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K
requires a 10-bit data word address for random word addressing.
Table 2-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Max
Units
1.8
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
2.7
5.5
V
VCC4
Supply Voltage
4.5
5.5
V
ICC
Supply Current VCC = 5.0V
READ at 100 kHz
0.4
1.0
mA
ICC
Supply Current VCC = 5.0V
WRITE at 100 kHz
2.0
3.0
mA
ISB1
Standby Current VCC = 1.8V
VIN = VCC or VSS
0.6
3.0
µA
ISB2
Standby Current VCC = 2.5V
VIN = VCC or VSS
1.4
4.0
µA
ISB3
Standby Current VCC = 2.7V
VIN = VCC or VSS
1.6
4.0
µA
ISB4
Standby Current VCC = 5.0V
VIN = VCC or VSS
8.0
18.0
µA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
µA
VIL
Input Low Level(1)
–0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
(1)
Min
Typ
VIH
Input High Level
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1 mA
0.4
V
Output Low Level VCC = 1.8V
IOL = 0.15 mA
0.2
V
VOL1
Note:
4
1. VIL min and VIH max are reference only and are not tested.
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
Table 2-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8, 2.5, 2.7
Min
Max
5.0-volt
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.2
0.4
µs
tHIGH
Clock Pulse Width High
0.6
0.4
µs
tI
Noise Suppression Time
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free before a new transmission can start
1.2
0.5
µs
tHD.STA
Start Hold Time
0.6
0.25
µs
tSU.STA
Start Setup Time
0.6
0.25
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Setup Time
100
100
ns
400
50
(1)
0.9
0.05
Max
Units
1000
kHz
40
ns
0.55
µs
tR
Inputs Rise Time
tF
Inputs Fall Time(1)
tSU.STO
Stop Setup Time
0.6
.25
µs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
Endurance(1)
5.0V, 25°C, Byte Mode
Note:
0.3
0.3
µs
300
100
ns
5
1M
5
1M
ms
Write
Cycles
1. This parameter is ensured by characterization only.
5
5226D–SEEPR–7/08
3. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5-3 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5-3 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C04B/08B features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by a stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Dummy Clock Cycles
Start bit
SCL
1
2
3
Start bit
8
Stop bit
9
SDA
6
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
4. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O®
Figure 4-1.
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tLOW
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
5. Write Cycle Timing
Figure 5-1.
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
(1)
twr
STOP
CONDITION
Note:
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5226D–SEEPR–7/08
Figure 5-2.
Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 5-3.
Start and Stop Definition
SDA
SCL
START
Figure 5-4.
STOP
Output Acknowledge
1
SCL
8
9
DATA IN
DATA OUT
START
8
ACKNOWLEDGE
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
6. Device Addressing
The 4K and 8K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8-1).
The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory
page address bit. The two device address bits must compare to their corresponding hard-wired
input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory
page addressing. The A2 must compare to its corresponding hard-wired input pin. The A1 and
A0 pins are no connect.
For the SOT23 Package Offering:
The 4K EEPROM software A2 and A1 bits in the device address word must be set to zero to
properly communicate.
The 8K EEPROM software A2 bit in the device address word must be set to zero to properly
communicate.
7. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing device, such as a microcontroller,
must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page
11).
PAGE WRITE: The 4K/8K EEPROMs are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to fifteen data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8-3 on page 11).
The data word address lower four bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero allowing the read or write sequence to continue.
9
5226D–SEEPR–7/08
8. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page to the first byte of the first page. The
address “roll over” during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input zero but does generate a following stop condition (see Figure 8-4 on
page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-5 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a zero
but does generate a following stop condition (see Figure 8-6 on page 12).
Figure 8-1.
10
Device Address
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
Figure 8-2.
Byte Write
Figure 8-3.
Page Write
Figure 8-4.
Current Address Read
Figure 8-5.
Random Read
11
5226D–SEEPR–7/08
Figure 8-6.
12
Sequential Read
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
AT24C04B Ordering Information
Ordering Code
Voltage
Package
AT24C04B-PU (Bulk form only)
1.8
8P3
AT24C04BN-SH-B(1) (NiPdAu Lead Finish)
1.8
8S1
AT24C04BN-SH-T(2) (NiPdAu Lead Finish)
1.8
8S1
1.8
8A2
AT24C04B-TH-T(2) (NiPdAu Lead Finish)
1.8
8A2
AT24C04BY6-YH-T(2) (NiPdAu Lead Finish)
1.8
8Y6
1.8
5TS1
AT24C04BU3-UU-T
1.8
8U3-1
AT24C04B-W-11(3)
1.8
Die Sale
(1)
AT24C04B-TH-B
AT24C04B-TSU-T
(NiPdAu Lead Finish)
(2)
(2)
Notes:
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
Industrial Temperature
(–40°C to 85°C)
1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y6
8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
5TS1
5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8U3-1
8-ball, die Ball Grid Array Package (dBGA2)
Options
–1.8
Low-voltage (1.8V to 5.5V)
13
5226D–SEEPR–7/08
AT24C08B Ordering Information
Ordering Code
Voltage
Package
AT24C08B-PU (Bulk form only)
1.8
8P3
AT24C08BN-SH-B(1) (NiPdAu Lead Finish)
1.8
8S1
AT24C08BN-SH-T(2) (NiPdAu Lead Finish)
1.8
8S1
1.8
8A2
AT24C08B-TH-T(2) (NiPdAu Lead Finish)
1.8
8A2
AT24C08BY6-YH-T(2) (NiPdAu Lead Finish)
1.8
8Y6
1.8
5TS1
AT24C08BU3-UU-T
1.8
8U3-1
AT24C08B-W-11(3)
1.8
Die Sale
(1)
AT24C08B-TH-B
AT24C08B-TSU-T
(NiPdAu Lead Finish)
(2)
(2)
Notes:
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
Industrial Temperature
(–40°C to 85°C)
1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y6
8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
5TS1
5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8U3-1
8-ball, die Ball Grid Array Package (dBGA2)
Options
–1.8
14
Low-voltage (1.8V to 5.5V)
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
9. Part marking scheme
9.1
8-PDIP
TOP MARK
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
|---|---|---|---|---|---|---|---|
0
4
B
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
52 = Week 52
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
9.2
WW = SEAL WEEK
02 = Week 2
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
8-SOIC
Seal Year
| Seal Week
TOP MARK
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
|---|---|---|---|---|---|---|---|
0
4
B
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
1: 2011
2: 2012
3: 2013
WW = SEAL WEEK
02 = Week 2
52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
15
5226D–SEEPR–7/08
9.3
8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
|
|---|---|---|---|
*
H
Y
W
W
|---|---|---|---|---|
0
4
B
Y = SEAL YEAR
6:
7:
8:
9:
2006
2007
2008
2009
0:
1:
2:
3:
WW = SEAL WEEK
2010
2011
2012
2013
1
02
04
::
::
=
=
:
:
Week
Week
::::
::::
2
4
:
::
50 = Week 50
|---|---|---|---|---|
52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
P
H
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
9.4
8-Ultra Thin Mini MAP
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
0
4
B
|---|---|---|
H
1
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y
X
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y =
6:
7:
8:
SEAL YEAR
2006
0: 2010
2007
1: 2011
2008
2: 2012
9: 2009
16
3: 2013
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
9.5
ULA
TOP MARK
|---|---|---|
0 4
B
|---|---|---|
Y
X
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y = BUILD YEAR
2006 = 6
2007 = 7
2008 = 8
Etc. . . .
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
9.6
SOT23
TOP MARK
Line 1 ----------->
|---|---|---|---|---|
4
B
1
B
U
|---|---|---|---|---|
*
|
XX = Device
V = Voltage Indicator
W = Write Protect Feature
U = Material Set
Pin 1 Indicator (Dot)
BOTTOM MARK
|---|---|---|---|
Y
M
T
C
|---|---|---|---|
Y = One Digit Year Code
M = Seal Month
(Use Alpha Designator A-L)
TC = Trace Code
9.7
dBGA2
TOP MARK
17
5226D–SEEPR–7/08
LINE 1------->
LINE 2------->
04BU
YMTC
|<--
Pin 1 This Corner
XXX = Device
U = Material Set
Y = One Digit Year Code
M = Seal Month (Use Alpha Designator A-L)
TC = Trace Code
18
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
10. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
b2
b3
b
4 PLCS
Side View
L
MIN
NOM
MAX
NOTE
A
–
–
0.210
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
SYMBOL
3
D1
0.005
–
–
3
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
0.150
2
e
0.100 BSC
eA
L
Notes:
5
0.300 BSC
0.115
0.130
4
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
19
5226D–SEEPR–7/08
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
Side View
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
20
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.50
3, 5
E
E1
e
D
A2
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
4.40
L
4
0.65 BSC
0.45
L1
0.60
0.75
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
21
5226D–SEEPR–7/08
8Y6 - Mini Map
D2
A
b
(8X)
E
E2
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
A2
e (6X)
A1
1.50 REF.
COMMON DIMENSIONS
(Unit of Measure = mm)
A3
SYMBOL
MIN
D
1.50
1.60
E2
-
-
1.40
A
-
-
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
L
0.20 REF
0.20
e
b
NOTE
3.00 BSC
1.40
A3
Notes:
MAX
2.00 BSC
E
D2
NOM
0.30
0.40
0.50 BSC
0.20
0.25
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
10/16/07
R
22
2325 Orchard Parkway
San Jose, CA 95131
DRAWING NO.
TITLE
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
8Y6
Dual No Lead Package (DFN) ,(MLP 2x3)
REV.
D
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
5TS1 – SOT23
e1
C
4
5
E1
C
L
E
L1
1
3
2
End View
Top View
b
A2
Seating
Plane
e
A
A1
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing
MO-193, Variation AB, for additional information.
2. Dimension D does not include mold flash, protrusions, or gate burrs.
Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end.
Dimension E1 does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.15 mm per side.
3. The package top may be smaller than the package bottom. Dimensions
D and E1 are determined at the outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. These dimensions apply to the flat section of the lead between 0.08 mm
and 0.15 mm from the lead tip.
5. Dimension "b" does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08 mm total in excess of the "b" dimension at
maximum material condition. The Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and an adjacent lead
shall not be less than 0.07 mm.
SYMBOL
MIN
NOM
MAX
A
–
–
1.10
A1
0.00
–
0.10
A2
0.70
0.90
1.00
c
0.08
–
0.20
D
2.90 BSC
NOTE
4
2, 3
E
2.80 BSC
2, 3
E1
1.60 BSC
2, 3
L1
0.60 REF
e
0.95 BSC
e1
b
1.90 BSC
0.30
–
0.50
4, 5
6/25/03
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink
Small Outline Package (SHRINK SOT)
DRAWING NO.
PO5TS1
REV.
A
23
5226D–SEEPR–7/08
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
Side View
PIN 1 BALL PAD CORNER
1
2
3
4
8
7
6
5
(d1)
d
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
Bottom View
8 SOLDER BALLS
1. Dimension “b” is measured at the maximum solder ball diameter.
This drawing is for general information only.
SYMBOL
MIN
NOM
MAX
A
0.71
0.81
0.91
A1
0.10
0.15
0.20
A2
0.40
0.45
0.50
b
0.20
0.25
0.30
D
NOTE
1.50 BSC
E
2.00 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
6/24/03
R
24
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO.
REV.
PO8U3-1
A
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
11. Revision History
Doc. Rev.
Date
Comments
5226D
7/2008
Removed ‘Preliminary’ status
5226C
2/2008
Text changes on page 4 and 9
5226B
8/2007
Updated to new template
Updated common Figures
Added Package Marking tables
5226A
6/2007
Initial document release
25
5226D–SEEPR–7/08
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Product Contact
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5226D–SEEPR–7/08
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