Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 DRV13x Audio-Balanced Line Drivers 1 Features 3 Description • • • • • • • • • The DRV134 and DRV135 are differential output amplifiers that convert a single-ended input to a balanced output pair. These balanced audio drivers consist of high performance op amps with on-chip precision resistors. They are fully specified for high performance audio applications and have excellent ac specifications, including low distortion (0.0005% at 1 kHz) and high slew rate (15 V/µs). 1 • Balanced Output Low Distortion: 0.0005% at f = 1 kHz Wide Output Swing: 17Vrms into 600 Ω High Capacitive Load Drive High Slew Rate: 15 V/µs Wide Supply Range: ±4.5 V to ±18 V Low Quiescent Current: ±5.2 mA 8-Pin DIP, SO-8, and SOL-16 Packages Companion to Audio Differential Line Receivers: INA134 and INA137 Improved Replacement for SSM2142 The on-chip resistors are laser-trimmed for accurate gain and optimum output common-mode rejection. Wide output voltage swing and high output drive capability allow use in a wide variety of demanding applications. They easily drive the large capacitive loads associated with long audio cables. Used in combination with the INA134 or INA137 differential receivers, they offer a complete solution for transmitting analog audio signals without degradation. 2 Applications • • • • • • • • • Audio Differential Line Drivers Audio Mix Consoles Distribution Amplifiers Graphic and Parametric Equalizers Dynamic Range Processors Digital Effects Processors Telecom Systems Hi-Fi Equipment Industrial Instrumentation The DRV134 is available in 8-pin DIP and SOL-16 surface-mount packages. The DRV135 comes in a space-saving SO-8 surface-mount package. Both are specified for operation over the extended industrial temperature range, –40°C to +85°C and operate from –55°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV134 SOIC (16) 10.30 mm × 7.50 mm DRV135 SOIC (8) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic V+ 50Ω +VO A2 +Sense 10kΩ –Sense VIN A1 50Ω Gnd –VO A3 10kΩ All resistors 30kΩ unless otherwise indicated. V– 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 4 4 4 5 6 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions ...................... Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 11 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 15 9.1 Application Information............................................ 15 9.2 Typical Application ................................................. 15 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 17 11.1 Layout Guidelines ................................................. 17 11.2 Layout Examples................................................... 18 11.3 Thermal Performance ........................................... 19 12 Device and Documentation Support ................. 19 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 5 Revision History Changes from Revision A (April 2007) to Revision B • 2 Page Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 6 Pin Configuration and Functions Top View Top View 8-Pin DIP/SO-8 –VO 1 8 +VO –Sense 2 7 +Sense Gnd 3 6 V+ VIN 4 5 V– SOL-16 NC 1 16 NC NC 2 15 NC –VO 3 14 +VO –Sense 4 13 +Sense Gnd 5 12 V+ VIN 6 11 V– NC 7 10 NC NC 8 9 NC NOTE: NC - No internal connection Pin Functions PIN NAME DIP-8 and SO-8 I/O SOL-16 DESCRIPTION Gnd 3 5 – Ground +Sense 7 13 I Sensing, non-inverting input –Sense 2 4 I Sensing, inverting input V+ 6 12 – Positive supply V– 5 11 – Negative supply VIN 4 6 I Input –Vo 1 3 O Inverted, balanced differential output +Vo 8 14 O Balanced differential output NC – 1,2,7,8,9,10,15,16 – These pins should be left unconnected Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 3 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage, V+ to V– Input voltage range V– UNIT 40 V V+ Output short-circuit (to ground) Continuous Operating temperature –55 Junction temperature (1) MAX 125 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings MIN Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MAX UNIT °C –55 125 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –2000 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –500 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Tspe Specification temperature range –40 85 °C TA Operation temperature range –55 125 °C V+ Positive supply 4.5 18 18 V V– Negative supply –4.5 –18 –18 V 4 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 7.4 Electrical Characteristics At TA = +25°C, VS = ±18 V, RL = 600 Ω differential connected between +VO and –VO, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO PERFORMANCE THD+N RTO (1) RTO (1) Total Harmonic Distortion + Noise 0.001% f = 20Hz to 20kHz, VO = 10Vrms f = 1kHz, VO = 10Vrms 20 kHz BW THD+N < 1% Noise Floor Headroom 0.0005% –98 dBu 27 dBu 10 kΩ INPUT ZIN Input Impedance (2) IIN Input Current VIN = ±7.07 V –1000 ±700 1000 µA GAIN Differential Initial [(+VO) – (–VO)]/VIN VIN = ±10V Error 5.8 6 –2% ±0.1% Error vs Temperature dB 2% ±10 Single-Ended ppm/°C VIN = ±5V Initial 5.8 6 Error –2% ±0.7% Error vs Temperature Nonlinearity dB 2% ±10 ppm/°C 0.0003 % of FS OUTPUT OCMR Common-Mode Rejection, f = 1kHz See Figure 25 46 68 dB SBR Signal Balance Ratio, f = 1kHz See Figure 26 35 54 dB Output Offset Voltage VOCM (3) Offset Voltage, Common-Mode VIN = 0 –250 Offset Voltage, Common-Mode vs Temperature VOD (4) Offset Voltage, Differential VIN = 0 –10 Offset Voltage, Differential vs Temperature PSRR Offset Voltage, Differential vs Power Supply Output Voltage Swing, Positive Negative VS = ±4.5V to ±18V No Load (5) Load Capacitance, Stable Operation ISC Short-Circuit Current ±1 250 mV µV/°C 10 mV ±5 µV/°C dB 80 110 (V+) – 3 (V+) – 2.5 (V–) + 2 (V–) + 1.5 Impedance CL ±50 ±150 V Ω 50 CL Tied to Ground (each output) 1 µF ±85 mA Small-Signal Bandwidth 1.5 MHz Slew Rate 15 V/µs 2.5 µs 3 µs FREQUENCY RESPONSE SR Settling Time: 0.01% VOUT = 10V Step Overload Recovery Output Overdriven 10% POWER SUPPLY VS Rated Voltage ±18 Voltage Range IQ (1) (2) (3) (4) (5) Quiescent Current ±4.5 IO = 0 –5.5 ±5.2 V ±18 V 5.5 mA dBu = 20log (Vrms /0.7746); RTO = Referred-to-Output. Resistors are ratio matched but have ±20% absolute value. VOCM = [(+VO) + (–VO)] / 2. VOD = (+VO) – (–VO). Ensures linear operation. Includes common-mode offset. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 5 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) At TA = +25°C, VS = ±18 V, RL = 600 Ω differential connected between +VO and –VO, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE RANGE Specification Range –40 85 °C Operation Range –55 125 °C Storage Range θJA Thermal Resistance –55 125 °C 8-Pin DIP 100 °C/W SO-8 Surface mount 150 °C/W 80 °C/W SOL-16 Surface mount 7.5 Typical Characteristics At TA = 25°C, VS = ±18 V, RL = 600 Ω differential connected between +VO and –VO, unless otherwise noted. 0.01 0.01 THD+N (%) THD+N (%) A B 0.001 Differential Mode VO = 10Vrms 500 ft cable See Figure 3 for Test Circuit A: R1 = R2 = RL = ∞ (no load) B: R1 = R2 = 600Ω, RL = ∞ C: R1 = R2 = ∞, R L = 600Ω Differential Mode VO = 10Vrms No Cable See Figure 3 for Test Circuit A: R1 = R2 = RL = ∞ (no load) B: R1 = R2 = 600Ω, RL = ∞ C: R1 = R2 = ∞, R L = 600Ω A B 0.001 C C DRV134 Output DRV134 Output 0.0001 0.0001 20 100 1k 10k 20 20k 100 Figure 1. Total Harmonic Distortion + Noise vs Frequency 0.1 0.01 A B See Figure 3 for Test Circuit A: R1 = R2 = RL = ∞ (no load) B: R1 = R2 = ∞ RL = 600Ω THD+N (%) 0.01 THD+N (%) 10k 20k Figure 2. Total Harmonic Distortion + Noise vs Frequency Single-Ended Mode VO = 10Vrms –VO or +VO Grounded A: R1 = 600Ω (250 ft cable) B: R1 = ∞ (no cable) 1k Frequency (Hz) Frequency (Hz) Differential Mode VO = 10Vrms A (no cable) 0.001 0.001 B (500ft cable) INA137 Output DRV134 Output 0.0001 20 0.0001 100 1k 10k 20k 20 Frequency (Hz) 1k 10k 20k Frequency (Hz) Figure 3. Total Harmonic Distortion + Noise vs Frequency 6 100 Figure 4. System Total Harmonic Distortion + Noise vs Frequency Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 Typical Characteristics (continued) At TA = 25°C, VS = ±18 V, RL = 600 Ω differential connected between +VO and –VO, unless otherwise noted. 1 1 f = 1kHz Single-Ended Mode Differential Mode 500 ft Cable RL = 600Ω 500 ft Cable RL = 600Ω Differential Mode 0.1 500 ft Cable RL = 600Ω DIM (%) THD+N (%) 0.1 0.01 0.01 0.001 0.001 0.0001 5 10 15 20 0.0001 25 5 30 10 Figure 5. Headroom – Total Harmonic Distortion + Noise vs Output Amplitude 20 25 30 Figure 6. Dim Intermodulation Distortion vs Output Amplitude 10 0.01 No Cable, RL = ∞ 500 ft Cable, RL = 600Ω 5 Voltage Gain (dB) Differential Mode Amplitude (% of Fundamental) 15 Output Amplitude (dBu) Output Amplitude (dBu) 0.001 2nd Harmonic 0.0001 3rd Harmonic 0.00001 20 100 1k 10k 0 –5 –10 1k 20k 10k Frequency (Hz) 100k 1M 10M Frequency (Hz) Figure 7. Harmonic Distortion Products vs Frequency Figure 8. Gain vs Frequency 100 Voltage Noise (µVrms) 10k Voltage Noise (nV/√Hz) No Cable RL = ∞ BW = 30kHz No Cable RL = ∞ DRV134 Output 1k 100 10 1 0.1 10 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure 9. Output Voltage Noise Spectral Density vs Frequency Figure 10. Output Voltage Noise vs Noise Bandwidth Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 7 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) At TA = 25°C, VS = ±18 V, RL = 600 Ω differential connected between +VO and –VO, unless otherwise noted. 20 100 Output Voltage Swing (Vrms) Power Supply Rejection (dB) 120 +PSRR 80 60 –PSRR 40 20 VS = ±4.5V to ±18V 0 0.1% Distortion 12 0.01% Distortion 8 4 RL = 600Ω Diff Mode 0 10 100 1k 10k 100k 10k 1M 20k Figure 11. Power Supply Rejection vs Frequency Figure 12. Maximum Output Voltage Swing vs Frequency 18 16 THD+N ≤ 0.1% +25°C 14 Output Voltage Swing (V) 16 12 8 4 12 –55°C +125°C 10 8 –8 +25°C –10 –55°C +125°C –12 –14 –16 –18 ±4 ±6 ±8 ±10 ±12 ±14 ±16 ±18 0 ±20 Supply Voltage (V) ±40 ±60 ±80 ±100 Output Current (mA) Figure 13. Output Voltage Swing vs Supply Voltage Figure 14. Output Voltage Swing vs Output Current ±120 ±5.6 Short-Circuit Current (mA) ±5.4 Quiescent Current (mA) 80k 100k Frequency (Hz) 0 T = –55°C ±5.2 T = +25°C ±5 T = +125°C ±4.8 ±100 +ISC ±80 –ISC ±60 ±40 ±20 ±4.6 ±4 ±6 ±8 ±10 ±12 ±14 ±16 ±18 –75 –50 –25 0 25 50 75 100 125 Temperature ( °C) Supply Voltage (V) Figure 15. Quiescent Current vs Supply Voltage 8 50k Frequency (Hz) 20 Differential Output Voltage (Vrms) 16 Figure 16. Short-Circuit Current vs Temperature Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 Typical Characteristics (continued) At TA = 25°C, VS = ±18 V, RL = 600 Ω differential connected between +VO and –VO, unless otherwise noted. 45 35 Percent of Units (%) 35 30 25 20 15 10 Typical production distribution of packaged units. All package types included. 30 Percent of Units (%) Typical production distribution of packaged units. All package types included. 40 25 20 15 10 5 5 0 –250 –225 –200 –175 –150 –125 –100 –75 –50 –25 0 25 50 75 100 125 150 175 200 225 250 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 0 Differential Offset Voltage (mV) Common-Mode Offset Voltage (mV) Figure 18. Common-Mode Offset Voltage Production Distribution 50mV/div 50mV/div Figure 17. Differential Offset Voltage Production Distribution 2µs/div 2µs/div CL = 100 pF CL = 1000 pF Figure 20. Small-Signal Step Response 5V/div 5V/div Figure 19. Small-Signal Step Response 2µs/div 2µs/div CL = 100 pF CL = 1000 pF Figure 21. Large-Signal Step Response Figure 22. Large-Signal Step Response Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 9 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) At TA = 25°C, VS = ±18 V, RL = 600 Ω differential connected between +VO and –VO, unless otherwise noted. 40 100mV Step Overshoot (%) 30 20 10 0 10 100 1k 10k Load Capacitance (pF) Figure 23. Small-Signal Step Overshoot vs Load Capacitance 10 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 8 Detailed Description 8.1 Overview The DRV134 and DRV135 consist of an input inverter driving a cross- coupled differential output stage with 50 Ω series output resistors. Characterized by low differential-mode output impedance (50 Ω) and high common-mode output impedance (1.6 kΩ), the DRV134 and DRV135 are ideal for audio applications. Excellent internal design and layout techniques provide low signal distortion, high output level (27 dBu), and a low noise floor (–98 dBu). Laser trimming of thin film resistors assures excellent output common-mode rejection (OCMR) and signal balance ratio (SBR). In addition, low dc voltage offset reduces errors and minimizes load currents. The Functional Block Diagram section shows a detailed block diagram of the DRV134 and DRV135. 8.2 Functional Block Diagram V– V+ 1µF 1µF 5 6 (12) (11) DRV134 DRV135 50Ω A2 8 +VO (14) 7 (13) +Sense 10kΩ VIN 4 G = +6dB (6) 2 Gnd A1 3 50Ω A3 (5) (4) 1 (3) –Sense –VO 10kΩ All resistors 30kΩ unless otherwise indicated. 8.3 Feature Description 8.3.1 Audio Performance The DRV134 and DRV135 were designed for enhanced ac performance. Very low distortion, low noise, and wide bandwidth provide superior performance in high quality audio applications. Laser-trimmed matched resistors provide optimum output common-mode rejection (typically 68dB), especially when compared to circuits implemented with op amps and discrete precision resistors. In addition, high slew rate (15 V/μs) and fast settling time (2.5 μs to 0.01%) ensure excellent dynamic response. The DRV134 and DRV135 have excellent distortion characteristics. As shown in the distortion data provided in the Typical Characteristics section, THD+Noise is below 0.003% throughout the audio frequency range under various output conditions. Both differential and single-ended modes of operation are shown. In addition, the optional 10μF blocking capacitors used to minimize VOCM errors have virtually no effect on performance. Measurements were taken with an Audio Precision System One (with the internal 80 kHz noise filter) using the THD test circuit shown in Figure 24. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 11 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) Up to approximately 10 kHz, distortion is below the measurement limit of commonly used test equipment. Furthermore, distortion remains relatively constant over the wide output voltage swing range (approximately 2.5 V from the positive supply and 1.5 V from the negative supply). A special output stage topology yields a design with minimum distortion variation from lot-to-lot and unit-to-unit. Furthermore, the small and large signal transient response curves demonstrate the stability under load of the DRV134 and DRV135. +18V +18V 1µF VIN 4 6 1µF Test Point or +VO 7 –In DRV134 2 3 5 7 2 8 INA137 RL 1 1 +In –VO 3 R1 5 6 VOUT 4 R2 1µF 1µF –18V –18V Figure 24. Distortion Test Circuit 8.3.2 Output Common-Mode Rejection Output common-mode rejection (OCMR) is defined as the change in differential output voltage due to a change in output common-mode voltage. When measuring OCMR, VIN is grounded and a common-mode voltage, VCM, is applied to the output as shown in Figure 25. Ideally no differential mode signal (VOD) should appear. However, a small mode-conversion effect causes an error signal whose magnitude is quantified by OCMR. +18V 1µF VIN 4 6 7 8 VOD DRV134 Gnd 2 3 5 300Ω(1) +VO 1 300Ω(1) –VO 600Ω 1µF VCM = 10Vp-p –18V Figure 25. Output Common-Mode Rejection Test Circuit 8.3.3 Signal Balance Ratio Signal balance ratio (SBR) measures the symmetry of the output signals under loaded conditions. To measure SBR an input signal is applied and the outputs are summed as shown in Figure 26. VOUT should be zero since each output ideally is exactly equal and opposite. However, an error signal results from any imbalance in the outputs. This error is quantified by SBR. The impedances of the DRV134 and DRV135’s output stages are closely matched by laser trimming to minimize SBR errors. In an application, SBR also depends on the balance of the load network. 12 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 Feature Description (continued) +18V 1µF VIN = 10Vp-p 4 6 +VO 7 300Ω(1) 8 DRV134 Gnd 2 3 5 1 300Ω(1) VOUT –VO 600Ω 1µF –18V Figure 26. Signal Balance Ratio Test Circuit 8.4 Device Functional Modes 8.4.1 Differential-Output Mode In differential-output mode, the DRV134 (and DRV135 in SO-8 package) converts a single-ended, groundreferenced input to a floating differential output with +6 dB gain (G = 2). Figure 27 shows the basic connections required for operation in differential-output mode. Normally, +VO is connected to +Sense, –VO is connected to –Sense, and the outputs are taken from these junctions as shown in Figure 27. V– V+ 1µF 1µF 5 6 (12) (11) DRV134 DRV135 50Ω A2 8 +VO (14) 7 (13) +Sense 10kΩ VIN 4 G = +6dB (6) 2 Gnd 3 A1 50Ω A3 (5) –Sense (4) 1 (3) –VO 10kΩ All resistors 30kΩ unless otherwise indicated. Figure 27. Basic Connections for Differential-Output Mode Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 13 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com Device Functional Modes (continued) 8.4.2 Single-Ended Mode The DRV134 can be operated in single-ended mode without degrading output drive capability. Single-ended operation requires that the unused side of the output pair be grounded (both the VO and Sense pins) to a low impedance return path. Gain remains +6 dB. Grounding the negative outputs as shown in Figure 28 results in a non-inverted output signal (G = +2) while grounding the positive outputs gives an inverted output signal (G = –2). V+ VIN VOUT = 2VIN 6 7 4 8 DRV134 600Ω 1 2 3 5 G = +6dB V– Figure 28. Typical Single-Ended Application For best rejection of line noise and hum differential mode operation is recommended. However, single-ended performance is adequate for many applications. In general single ended performance is comparable to differential mode (see THD+N typical performance curves), but the common mode and noise rejection inherent in balanced-pair systems is lost. 14 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Decoupling capacitors placed close to the device pins are strongly recommended in applications with noisy or high impedance power supplies. For best system performance, it is recommended that a high input-impedance difference amplifier be used as the receiver. Used with the INA134 (G = 0 dB) or the INA137 (G = ±6 dB) differential line receivers, the DRV134 forms a complete solution for driving and receiving audio signals, replacing input and output coupling transformers commonly used in professional audio systems (Figure 29). When used with the INA137 (G = –6 dB) overall system gain is unity. 9.2 Typical Application 9.2.1 Cable Driving Application The DRV134 is capable of driving large signals into 600-Ω loads over long cables. Low impedance shielded audio cables such as the standard Belden 8451 or 9452 (or similar) are recommended, especially in applications where long cable lengths are required. For applications with large dc cable offset errors, a 10-µF electrolytic nonpolarized blocking capacitor at each sense pin is recommended as shown in Figure 29. DRIVER DRV134 DRV135 RECEIVER 50Ω A2 8 7 10µF(1) +VO BALANCED CABLE PAIR –VO 5 2 10kΩ VIN 4 6 2 Gnd 3 A1 50Ω A3 1 VO 10µF(1) –VO 3 1 +VO INA134, INA137 INA134 (G = 1): VO = 2VIN INA137 (G = 1/2): VO = VIN 10kΩ All resistors 30kΩ unless otherwise indicated. Figure 29. Complete Audio Driver and Receiver Circuit 9.2.1.1 Design Requirements Consider a design with the goal of differentially transmitting a single ended signal of up to 22.2 dBu through 500 ft of cable with no load at the receiving side. The signal at the end of the cable should have no more than 0.002 percent of total harmonic distortion plus noise (THD+N) at 10 kHz and less than 0.0005 percent of THD+N for frequencies between 20 Hz and 1 kHz. The system is required to put out a single ended signal 0 dB with respect to the input signal and accommodate inputs with peak to RMS ratios of up to 1.5 for the maximum 22.2 dBu range established above. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 15 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 9.2.1.2 Detailed Design Procedure The dBu is a common unit of measurement for input sensitivity and output level of professional audio equipment. A 0 dBu signal dissipates 1 mW into a 600-Ω resistive load; therefore, a 0 dBu signal corresponds to approximately 0.775 VRMS. Equation 1 shows the relationship between the signal level in dBu (denoted by Lu) and the signal level in VRMS (denoted by x). § x · L u 20 log10 ¨ ¸ © 0.775 ¹ (1) For this design, the single ended input signal of 22.2 dBu corresponds to 9.98 VRMS as shown in Equation 2. VIN § Lu 0 .775¨¨ 10 20 © · ¸ ¸ ¹ 9 .98 VRMS (2) Given that the system must accommodate for 22.2 dBu signals with up to 1.5 of peak to RMS ratio, the maximum peak input signal is 14.97 VPEAK as calculated in Equation 3. VIN _ PEAK 1.5 9.98 14.97 VPEAK (3) The DRV134 is chosen to convert the single ended input signal into a differential signal and the outputs of the DRV134 will be connected to one end of the 500 ft cable. In order to prevent clipping and distortion of the input signal, the power supply rails for the DRV134 are chosen as 3 V above and below the peak calculated in Equation 3. The 3 V margin is derived from the output voltage swing specification given in the Electrical Characteristics table. The supplies selected are 18 V for V+ and –18 V for V–. Finally, the INA137 is used at the end of the 500 ft cable in order to convert the differential signal output of the DRV134 into a single ended signal that is 0 dB with respect to the input signal. Figure 30 shows the system diagram. +18V +18V 1µF VIN 4 6 1µF Test Point or +VO 7 –In DRV134 2 3 5 7 2 8 INA137 RL 1 –VO 1 +In 3 R1 5 6 VOUT 4 R2 1µF 1µF –18V –18V Figure 30. Diagram of System Based on DRV134 and INA137 16 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 Typical Application (continued) 9.2.1.3 Application Curve Figure 31 shows the performance obtained with the system depicted in Figure 30. 0.01 Differential Mode VO = 10Vrms 500 ft cable THD+N (%) See Figure 3 for Test Circuit A: R1 = R2 = RL = ∞ (no load) B: R1 = R2 = 600Ω, RL = ∞ C: R1 = R2 = ∞, R L = 600Ω A B 0.001 C DRV134 Output 0.0001 20 100 1k 10k 20k Frequency (Hz) Figure 31. Measured Performance of a System Based on DRV134 10 Power Supply Recommendations The DRV134 and DRV135 are designed to operate from an input voltage supply range between ±4.5 V and ±18 V. This input supply should be well regulated. If the input supply is located more than a few inches from the DRV134 or DRV135 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. 11 Layout 11.1 Layout Guidelines A driver/receiver balanced-pair (such as the DRV134 and INA137) rejects the voltage differences between the grounds at each end of the cable, which can be caused by ground currents, supply variations, etc. In addition to proper bypassing (as shown in Figure 32 and Figure 33), the suggestions below should be followed to achieve optimal OCMR and noise rejection. • The DRV134 input should be driven by a low impedance source such as an op amp or buffer. • As is the case for any single-ended system, the source’s common should be connected as close as possible to the DRV134’s ground. Any ground offset errors in the source will degrade system performance. • Symmetry on the outputs should be maintained. • Shielded twisted-pair cable is recommended for all applications. Physical balance in signal wiring should be maintained. Capacitive differences due to varying wire lengths may result in unequal noise pickup between the pair and degrade OCMR. Follow industry practices for proper system grounding of the cables. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 17 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com 11.2 Layout Examples Top View NC 1 16 NC NC NC -Vo +Vo -Sense +Sense DRV134 LEGEND Gnd V+ VIN V- NC NC 1 µF SMD 0603 1 µF SMD 0603 TOP layer: copper pour & traces PCB NC 8 NC 9 via to ground plane Figure 32. DRV134 Layout Example Top View -Vo 1 8 +Vo -Sense +Sense DRV135 V+ Gnd VIN 4 V- 5 1 µF SMD 0603 1 µF SMD 0603 LEGEND TOP layer: copper pour & traces PCB via to ground plane Figure 33. DRV135 Layout Example 18 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 DRV134, DRV135 www.ti.com SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 11.3 Thermal Performance The DRV134 and DRV135 have robust output drive capability and excellent performance over temperature. In most applications there is no significant difference between the DIP, SOL-16, and SO-8 packages. However, for applications with extreme temperature and load conditions, the SOL-16 (DRV134UA) or DIP (DRV134PA) packages are recommended. Under these conditions, such as loads greater than 600 Ω or very long cables, performance may be degraded in the SO-8 (DRV135UA) package. 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Audio Differential Line Receivers 0dB (G = 1), INA134 • Audio Differential Line Receivers ±6dB (G = 1/2 or 2), INA137 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DRV134 Click here Click here Click here Click here Click here DRV135 Click here Click here Click here Click here Click here 12.3 Trademarks All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 19 DRV134, DRV135 SBOS094B – JANUARY 1998 – REVISED DECEMBER 2014 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: DRV134 DRV135 PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DRV134PA ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DRV134PA DRV134PAG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DRV134PA DRV134UA ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV134UA DRV134UA/1K ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV134UA DRV134UA/1KE4 ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV134UA DRV134UAE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV134UA DRV135UA ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV 135UA DRV135UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV 135UA DRV135UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV 135UA DRV135UAG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV 135UA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2014 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV134UA/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 DRV135UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV134UA/1K SOIC DW 16 1000 367.0 367.0 38.0 DRV135UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated