Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 150 mA
Low quiescent current
IGND = 11 μA with 0 μA load
IGND = 30 μA with 150 mA load
Low shutdown current: <1 μA
Low dropout voltage
90 mV @ 150 mA load
High PSRR
70 dB @ 1 kHz at VOUT = 1.2 V
70 dB @ 10 kHz at VOUT = 1.2 V
Low noise: 40 μV rms at VOUT = 1.2 V
No noise bypass capacitor required
Output voltage accuracy: ±1%
Stable with a small 1 μF ceramic output capacitor
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
TYPICAL APPLICATION CIRCUITS
VIN = 2.3V
CIN
1µF
ON
1
VIN
2
GND
3
EN
VOUT = 1.8V
VOUT 5
COUT
1µF
NC 4
06901-001
FEATURES
OFF
NC = NO CONNECT
Figure 1. ADP121 TSOT with Fixed Output Voltage, 1.8 V
VOUT = 1.8V
VIN = 2.3V
VIN
VOUT
CIN
1µF
COUT
1µF
ON
OFF
EN
GND
06901-002
Data Sheet
150 mA, Low Quiescent Current,
CMOS Linear Regulator
ADP121
Figure 2. ADP121 WLCSP with Fixed Output Voltage, 1.8 V
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Post regulation
GENERAL DESCRIPTION
The ADP121 is a quiescent current, low dropout, linear regulator
that operates from 2.3 V to 5.5 V and provides up to 150 mA of
output current. The low 135 mV dropout voltage at 150 mA
load improves efficiency and allows operation over a wide
input voltage range. The low 30 μA of quiescent current at full
load makes the ADP121 ideal for battery-operated portable
equipment.
The ADP121 is available in output voltages ranging from 1.2 V
to 3.3 V. The parts are optimized for stable operation with small
1 μF ceramic output capacitors. The ADP121 delivers good
transient performance with minimal board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP121 is available
in a tiny 5-lead TSOT and 4-ball 0.4 mm pitch halide-free
WLCSP packages and utilizes the smallest footprint solution to
meet a variety of portable applications.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
ADP121
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 11
Typical Application Circuits............................................................ 1
Applications Information .............................................................. 12
General Description ......................................................................... 1
Capacitor Selection .................................................................... 12
Revision History ............................................................................... 2
Undervoltage Lockout ............................................................... 13
Specifications..................................................................................... 3
Enable Feature ............................................................................ 13
Recommended Specifications: Input and Output Capacitors 4
Current Limit and Thermal Overload Protection ................. 14
Absolute Maximum Ratings............................................................ 5
Thermal Considerations............................................................ 14
Thermal Data ................................................................................ 5
PCB Layout Considerations ...................................................... 17
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 18
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 19
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
8/12—Rev. F to Rev. G
Change to Ordering Guide .............................................................19
7/12—Rev. E to Rev. F
Updated Outline Dimensions ........................................................18
Change to Ordering Guide .............................................................19
8/11—Rev. D to Rev. E
Changes to Figure 22 ........................................................................ 9
Changes to Ordering Guide .......................................................... 19
1/10—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 19
11/09—Rev. B to Rev. C
Changes to Figure 1, Figure 2, and General Description
Section ................................................................................................ 1
Changes to Table 3.............................................................................5
Changes to Figure 46 Caption and Figure 47 Caption .............. 17
Changes to Ordering Guide .......................................................... 19
9/09—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
3/09—Rev. 0 to Rev. A
Changes to Features and General Description Sections ..............1
Changes to Input and Output Capacitor Parameter .....................4
Changes to Figure 17 to Figure 20...................................................9
Changes to Figure 49...................................................................... 17
Added Figure 50 ............................................................................. 17
Changes to Ordering Guide .......................................................... 19
7/08—Revision 0: Initial Version
Rev. G | Page 2 of 20
Data Sheet
ADP121
SPECIFICATIONS
VIN = (VOUT + 0.5 V) or 2.3 V, whichever is greater; EN = VIN; IOUT = 10 mA; CIN = COUT = 1 µF; TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol
VIN
IGND
SHUTDOWN CURRENT
IGND-SD
FIXED OUTPUT VOLTAGE ACCURACY
VOUT
REGULATION
Line Regulation
Load Regulation 1
DROPOUT VOLTAGE 2
TSOT
∆VOUT/∆VIN
∆VOUT/∆IOUT
VDROPOUT
WLCSP
3
START-UP TIME
CURRENT-LIMIT THRESHOLD 4
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
OUTPUT NOISE
TSTART-UP
ILIMIT
Conditions
TJ = −40°C to +125°C
IOUT = 0 µA
IOUT = 0 µA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +125°C
IOUT = 10 mA
100 µA < IOUT < 150 mA,
VIN = (VOUT + 0.5 V) to 5.5 V
100 µA < IOUT < 150 mA,
VIN = (VOUT + 0.5 V) to 5.5 V
TJ = −40°C to +125°C
Min
2.3
VIN = (VOUT + 0.5 V) to 5.5 V, IOUT = 1 mA
TJ = −40°C to +125°C
IOUT = 1 mA to 150 mA
IOUT = 1 mA to 150 mA
TJ = −40°C to +125°C
VOUT = 3.3 V
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
VOUT = 3.3 V
TJ rising
VIH
VIL
VI-LEAKAGE
2.3 V ≤ VIN ≤ 5.5 V
2.3 V ≤ VIN ≤ 5.5 V
EN = VIN or GND
EN = VIN or GND, TJ = −40°C to +125°C
UVLO
UVLORISE
UVLOFALL
UVLOHYS
OUTNOISE
−1
−2
1.5
+1
+2
Unit
V
µA
µA
µA
µA
µA
µA
µA
µA
%
%
Max
5.5
−3
+3
%
−0.03
+0.03
%/V
0.005
%/mA
%/mA
11
21
15
29
30
40
0.1
0.001
8
12
120
180
6
9
90
135
160
TSSD
TSSD-HYS
Typ
120
225
350
150
15
°C
°C
1.2
0.4
0.05
2.25
Rev. G | Page 3 of 20
V
V
µA
1
1.5
10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.2 V
mV
mV
mV
mV
mV
mV
mV
mV
µs
mA
120
65
52
40
V
V
mV
µV rms
µV rms
µV rms
ADP121
Parameter
POWER SUPPLY REJECTION RATIO
Data Sheet
Symbol
PSRR
Conditions
10 kHz, VIN = 5 V, VOUT = 3.3 V
10 kHz, VIN = 5 V, VOUT = 2.5 V
10 kHz, VIN = 5 V, VOUT = 1.2 V
Min
Typ
60
66
70
Max
Unit
dB
dB
dB
1
Based on an end-point calculation using 1 mA and 100 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
2
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITORS
Table 2.
Parameter
INPUT AND OUTPUT CAPACITOR 1
Minimum Input and Output Capacitance
Capacitor ESR
1
Symbol
Conditions
Min
CMIN
RESR
TA = −40°C to +125°C
TA = −40°C to +125°C
0.70
0.001
Typ
Max
Unit
1
µF
Ω
The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. G | Page 4 of 20
Data Sheet
ADP121
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to VIN
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP121 can be damaged when the junction
temperature limits are exceeded. Monitoring the ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. TJ of the device is dependent on
the ambient temperature (TA), the power dissipation of the
device (PD), and the junction-to-ambient thermal resistance of
the package (θJA). TJ is calculated from TA and PD using the
following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance, θJA, is based on
modeling and calculation using a four-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4” × 3”, circuit
board. Refer to JESD 51-7 and JESD 51-9 for detailed
information on the board construction. For additional
information, see AN-617 Application Note, MicroCSPTM
Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
measured in °C/W. ΨJB is based on modeling and calculation
using a four-layer board. The JESD51-12 Guidelines for Reporting
and Using Package Thermal Information states that thermal
characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in realworld applications. Maximum TJ is calculated from the board
temperature (TB) and PD using the following formula:
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball 0.4 mm Pitch WLCSP
ESD CAUTION
Rev. G | Page 5 of 20
θJA
170
260
ΨJB
43
58
Unit
°C/W
°C/W
ADP121
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
5
VOUT
A
TOP VIEW
GND 2
(Not to Scale)
VIN
VOUT
TOP VIEW
(Not to Scale)
4
NC = NO CONNECT
NC
06901-003
EN 3
2
B
Figure 3. 5-Lead TSOT Pin Configuration
EN
GND
06901-004
VIN 1
1
Figure 4. 4-Ball WLCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSOT WLCSP
1
A1
2
B2
3
B1
Mnemonic
VIN
GND
EN
4
5
NC
VOUT
N/A
A2
Description
Regulator Input Supply. Bypass VIN to GND with a 1 µF or larger capacitor.
Ground.
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
No Connect. Not connected internally.
Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
Rev. G | Page 6 of 20
Data Sheet
ADP121
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
1.804
40
VOUT = 1.8V
VIN = 2.3V
GROUND CURRENT (µA)
1.800
1.796
1.794
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
1.790
1.788
= 10µA
= 100µA
= 1mA
= 10mA
= 100mA
= 150mA
25
20
15
25°C
85°C
0
06901-005
–5°C
125°C
TJ (°C)
–40°C
85°C
125°C
35
VOUT = 1.8V
VIN = 2.3V
TA = 25°C
GROUND CURRENT (µA)
30
1.802
1.800
1.798
1.796
VOUT = 1.8V
VIN = 2.3V
TA = 25°C
25
20
15
10
5
0.01
0.1
1
ILOAD (mA)
10
100
1000
0
0.001
06901-006
1.794
0.001
Figure 6. Output Voltage vs. Load Current
0.1
1
ILOAD (mA)
10
100
1000
Figure 9. Ground Current vs. Load Current
1.806
35
1.804
1.802
= 10µA
= 100µA
= 1mA
= 10mA
= 50mA
= 100mA
VOUT = 1.8V
TA = 25°C
30
GROUND CURRENT (µA)
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
VOUT = 1.8V
TA = 25°C
1.800
1.798
1.796
25
20
15
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
10
5
2.7
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
06901-007
1.794
2.3
0.01
06901-009
VOUT (V)
25°C
Figure 8. Ground Current vs. Junction Temperature
1.806
VOUT (V)
–5°C
TJ (°C)
Figure 5. Output Voltage vs. Junction Temperature
1.804
= 10µA
= 100µA
= 1mA
= 10mA
= 100mA
= 150mA
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
10
5
1.786
–40°C
30
0
2.3
2.7
3.1
3.5
3.9
VIN (V)
4.3
4.7
= 10µA
= 100µA
= 1mA
= 10mA
= 100mA
= 150mA
5.1
Figure 10. Ground Current vs. Input Voltage
Figure 7. Output Voltage vs. Input Voltage
Rev. G | Page 7 of 20
5.5
06901-010
VOUT (V)
1.798
1.792
VOUT = 1.8V
VIN = 2.3V
35
06901-008
1.802
ADP121
Data Sheet
0.35
140
0.25
120
100
VDROPOUT (mV)
0.30
0.20
0.15
80
60
VOUT = 2.5V
0.10
40
0.05
20
VOUT = 3.3V
–25
0
25
50
75
TEMPERATURE (°C)
100
125
0
1
10
100
06901-012
0
–50
06901-011
SHUTDOWN CURRENT (µA)
TA = 25°C
VIN = 2.30
VIN = 2.50
VIN = 3.00
VIN = 3.50
VIN = 4.20
VIN = 5.50
1000
ILOAD (mA)
Figure 14. Dropout Voltage vs. Load Current, WLCSP
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
3.35
VOUT = 3.3V
TA = 25°C
180
TA = 25°C
3.30
160
140
100
3.20
80
VOUT @ 1mA
VOUT @ 10mA
VOUT @ 20mA
VOUT @ 50mA
VOUT @ 100mA
VOUT @ 150mA
3.15
VOUT = 2.5V
60
VOUT = 3.3V
3.10
40
20
1
10
100
1000
ILOAD (mA)
3.05
3.20
06901-018
0
3.25
3.30
3.35
3.40
VIN (V)
3.45
3.50
3.35
60
VOUT = 3.3V
TA = 25°C
VOUT = 3.3V
TA = 25°C
3.30
3.20
VOUT @ 1mA
VOUT @ 10mA
VOUT @ 20mA
VOUT @ 50mA
VOUT @ 100mA
VOUT @ 150mA
3.10
3.25
3.30
3.35
3.40
VIN (V)
3.45
3.50
3.55
30
20
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 20mA
10
3.60
06901-019
3.15
40
Figure 13. Output Voltage vs. Input Voltage (In Dropout), TSOT
0
3.20
3.25
3.30
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 150mA
3.35
3.40
VIN (V)
3.45
3.50
3.55
3.60
Figure 16. Ground Current vs. Input Voltage (In Dropout)
Rev. G | Page 8 of 20
06901-020
GROUND CURRENT (µA)
50
3.25
VOUT (V)
3.60
Figure 15. Output Voltage vs. Input Voltage (In Dropout), WLCSP
Figure 12. Dropout Voltage vs. Load Current, TSOT
3.05
3.20
3.55
06901-013
VOUT (V)
VDROPOUT (mV)
3.25
120
Data Sheet
ADP121
0
0
3.3V/150mA
3.3V/100µA
VRIPPLE = 50mV
VIN = 5V
VOUT = 1.2V
COUT = 1µF
–10
–20
1.8V/150mA
1.8V/100µA
–20
150mA
100mA
10mA
1mA
100µA
0µA
–40
–50
–40
PSRR (dB)
–30
PSRR (dB)
1.2V/150mA
1.2V/100µA
–60
–60
–80
–70
–80
–100
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–120
10
06901-014
–100
10
Figure 17. Power Supply Rejection Ratio vs. Frequency
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 20. Power Supply Rejection Ratio vs. Frequency at Various Output
Voltages and Load Currents
0
10
VRIPPLE = 50mV
VIN = 5V
VOUT = 1.8V
COUT = 1µF
–20
1.2V
1.8V
3.3V
150mA
100mA
10mA
1mA
100µA
0µA
–30
NOISE (µV/√Hz)
–10
PSRR (dB)
100
06901-017
–90
–40
–50
–60
–70
1
0.1
–80
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
10
06901-015
100
Figure 18. Power Supply Rejection Ratio vs. Frequency
1k
FREQUENCY (Hz)
10k
100k
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 µF
70
0
150mA
100mA
10mA
1mA
100µA
0µA
–30
60
50
OUTNOISE (µV rms)
–20
–40
–50
–60
40
30
20
–70
3.3V
2.5V
1.8V
1.5V
1.2V
–80
10
–90
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 19. Power Supply Rejection Ratio vs. Frequency
10M
0
0.001
06901-016
–100
10
0.01
0.1
1
ILOAD (mA)
10
100
1000
06901-022
VRIPPLE = 50mV
VIN = 5V
VOUT = 3.3V
COUT = 1µF
–10
PSRR (dB)
100
06901-021
–90
–100
10
Figure 22. Output Noise vs. Load Current and Output Voltage, VIN = 5 V, COUT = 1 μF
Rev. G | Page 9 of 20
Data Sheet
1mA TO 150mA LOAD STEP,
2.5A/µs
VIN
ILOAD
(1V/DIV)
(150mA/DIV)
ADP121
4V TO 5V INPUT VOLTAGE STEP,
2V/µs
VOUT = 1.8V,
CIN = COUT = 1µF
(1V/DIV)
ILOAD
(40µs/DIV)
(10mV/DIV)
VOUT
VIN = 5V
VOUT = 1.8V
06901-037
(4µs/DIV)
06901-025
(150mA/DIV)
(50mV/DIV)
VOUT = 1.8V,
CIN = COUT = 1µF
Figure 25. Line Transient Response, Load Current = 150 mA
Figure 23. Load Transient Response, CIN = COUT = 1 μF
1mA TO 150mA LOAD STEP,
2.5A/µs
VOUT
VIN
4V TO 5V INPUT VOLTAGE STEP,
2V/µs
VOUT
(10µs/DIV)
Figure 26. Line Transient Response, Load Current = 1 mA
Figure 24. Load Transient Response, CIN = COUT = 4.7 μF
Rev. G | Page 10 of 20
06901-038
(40µs/DIV)
(10mV/DIV)
VIN = 5V
VOUT = 1.8V
06901-024
(50mV/DIV)
VOUT
Data Sheet
ADP121
THEORY OF OPERATION
The ADP121 is a low quiescent current, low dropout linear
regulator that operates from 2.3 V to 5.5 V and provides up
to 150 mA of output current. Drawing a low 30 μA quiescent
current (typical) at full load makes the ADP121 ideal for batteryoperated portable equipment. Shutdown current consumption
is typically 100 nA.
Optimized for use with small 1 µF ceramic capacitors,
the ADP121 provides excellent transient performance.
VIN
VOUT
R1
EN
The ADP121 is available in output voltages ranging from 1.2 V to
3.3 V. The ADP121 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is
high, VOUT turns on; when EN is low, VOUT turns off. For
automatic startup, EN can be tied to VIN.
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
SHUTDOWN
0.8V REFERENCE
R2
06901-023
GND
Internally, the ADP121 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the
reference voltage with the feedback voltage from the output and
amplifies the difference. If the feedback voltage is lower than
the reference voltage, the gate of the PMOS device is pulled
lower, allowing more current to flow and increasing the output
voltage. If the feedback voltage is higher than the reference
voltage, the gate of the PMOS device is pulled higher, allowing
less current to flow and decreasing the output voltage.
Figure 27. Internal Block Diagram
Rev. G | Page 11 of 20
ADP121
Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input Bypass Capacitor
Output Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance is encountered. If output
capacitance greater than 1 µF is required, the input capacitor
should be increased to match it.
The ADP121 is designed for operation with small, space-saving
ceramic capacitors, but functions with most commonly used
capacitors as long as care is taken with the effective series resistance
(ESR) value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum of 0.70 µF capacitance with an
ESR of 1 Ω or less is recommended to ensure stability of the
ADP121. The transient response to changes in the load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP121 to
large changes in the load current. Figure 28 and Figure 29 show
the transient responses for output capacitance values of 1 µF and
4.7 µF, respectively.
(150mA/DIV)
ILOAD
1mA TO 150mA LOAD STEP,
2.5A/µs
VOUT = 1.8V,
CIN = COUT = 1µF
VOUT
(400ns/DIV)
Any good quality ceramic capacitor can be used with the
ADP121, as long as it meets the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior
over temperature and applied voltage. Capacitors must have an
adequate dielectric to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recomm ended. Y5V and Z5U dielectrics are not
recommended, due to their poor temperature and dc bias
characteristics.
Figure 30 depicts the capacitance vs. voltage bias characteristic
of an 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating.
1.2
06901-039
(50mV/DIV)
CH1 MEAN
115.7mA
Input and Output Capacitor Properties
1.0
CAPACITANCE (µF)
Figure 28. Output Transient Response, COUT = 1 µF
ILOAD
(150mA/DIV)
1mA TO 150mA LOAD STEP,
2.5A/µs
0.8
0.6
0.4
0
(50mV/DIV)
0
VOUT
2
4
6
VOLTAGE (V)
8
(400ns/DIV)
06901-040
Figure 30. Capacitance vs. Voltage Bias Characteristic
VOUT = 1.8V,
CIN = COUT = 4.7µF
Figure 29. Output Transient Response, COUT = 4.7 µF
Rev. G | Page 12 of 20
10
06901-036
0.2
Data Sheet
ADP121
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric. TOL is assumed to be 10%, and
CBIAS is 0.94 μF at 1.8 V from the graph in Figure 30.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
The active/inactive thresholds of the EN pin are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 32 shows typical EN active/inactive
thresholds when the input voltage varies from 2.3 V to 5.5 V.
1.10
1.05
1.00
EN ACTIVE
0.95
0.90
0.85
EN INACTIVE
0.80
0.75
To guarantee the performance of the ADP121, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
0.70
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
VIN (V)
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
UNDERVOLTAGE LOCKOUT
The ADP121 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.2 V. This ensures that the inputs of the
ADP121 and the output behave in a predictable manner during
power-up.
ENABLE FEATURE
The ADP121 utilizes an internal soft start to limit the inrush
current when the output is enabled. The start-up time for the
1.8 V option is approximately 120 µs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. The start-up time is somewhat dependant on the
output voltage setting and increases slightly as the output
voltage increases.
6
EN
5
4
VOLTS (V)
The ADP121 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. Figure 31 shows a
rising voltage on EN crossing the active threshold, and then
VOUT turns on. When a falling voltage on EN crosses the
inactive threshold, VOUT turns off.
VIN = 5V
VOUT = 1.8V
CIN = COUT = 1µF
ILOAD = 100mA
VOUT
3
3.3V
2
1.8V
1
1.2V
0
0
20
40
60
80
100 120
TIME (µs)
140
160
Figure 33. Typical Start-Up Time
40ms/DIV
Figure 31. ADP121 Typical EN Pin Operation
Rev. G | Page 13 of 20
180
200
06901-041
EN
06901-026
500mV/DIV
06901-027
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
As shown in Figure 31, the EN pin has built in hysteresis. This
prevents on/off oscillations that may occur due to noise on the
EN pin as it passes through the threshold points.
TYPICAL EN THRESHOLDS (V)
Equation 1 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, component tolerance, and voltage.
ADP121
Data Sheet
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP121 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP121 is designed to current limit when the
output load reaches 225 mA (typical). When the output load
exceeds 225 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is built-in, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C, the output is turned on again and output current is
restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP121 current limits, so that only 225 mA is conducted into the short. If self-heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts 225 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and
150°C causes a current oscillation between 225 mA and 0 mA
that continues as long as the short remains at the output.
dissipation in the power device, and thermal resistances between
the junction-and-ambient air (θJA). The θJA number is dependent
on the package assembly compounds used and the amount of
copper to which the GND pins of the package are soldered on the
PCB. Table 6 shows typical θJA values for various PCB copper
sizes and Table 7 shows the typical ΨJB values for the ADP121.
Table 6. Typical θJA Values
Copper Size (mm2)
01
50
100
300
500
1
TSOT (°C/W)
170
152
146
134
131
WLCSP (°C/W)
260
159
157
153
151
Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
TSOT (°C/W)
42.8
WLCSP (°C/W)
58.4
The junction temperature of the ADP121 can be calculated
from the following equation:
TJ = TA + (PD × θJA)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so junction temperatures do not exceed 125°C.
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
THERMAL CONSIDERATIONS
Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to
In most applications, the ADP121 does not dissipate a lot of heat
due to high efficiency. However, in applications with a high
ambient temperature and high supply voltage to an output voltage
differential, the heat dissipated in the package is large enough
that it can cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown
in Equation 2.
(2)
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(3)
(4)
As shown in Equation 4, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, there exists a minimum copper size requirement for
the PCB to ensure that the junction temperature does not rise
above 125°C. Figure 34 to Figure 47 show junction temperature
calculations for different ambient temperatures, load currents,
VIN-to-VOUT differentials, and areas of PCB copper.
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, can be used to estimate the
junction temperature rise. TJ is calculated from TB and PD using
the formula
To guarantee reliable operation, the junction temperature of the
ADP121 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user needs to
be aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
Rev. G | Page 14 of 20
TJ = TB + (PD × ΨJB)
(5)
Data Sheet
ADP121
140
140
MAX JUNCTION TEMPERATURE
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
80
60
40
20
0
0.5
Figure 34. TSOT, 500 mm2 of PCB Copper, TA = 25°C
JUNCTION TEMPERATURE, TJ (°C)
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
ILOAD = 50mA
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
60
40
20
1.0
= 1mA
= 10mA
= 25mA
= 50mA
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
140
MAX JUNCTION TEMPERATURE
= 1mA
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
JUNCTION TEMPERATURE, TJ (°C)
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
40
20
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
120
100
80
60
40
20
0
0.5
06901-030
JUNCTION TEMPERATURE, TJ (°C)
ILOAD
ILOAD
ILOAD
ILOAD
Figure 38. TSOT, 100 mm2 of PCB Copper, TA = 50°C
60
0
0.5
4.5
80
MAX JUNCTION TEMPERATURE
80
4.0
100
0
0.5
140
100
3.5
120
Figure 35. TSOT, 100 mm2 of PCB Copper, TA = 25°C
120
2.0
2.5
3.0
VIN – VOUT (V)
MAX JUNCTION TEMPERATURE
06901-029
JUNCTION TEMPERATURE, TJ (°C)
80
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
140
MAX JUNCTION TEMPERATURE
100
1.0
= 1mA
= 10mA
= 25mA
= 50mA
Figure 37. TSOT, 500 mm2 of PCB Copper, TA = 50°C
140
120
ILOAD
ILOAD
ILOAD
ILOAD
06901-031
60
100
06901-032
80
= 1mA
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
120
Figure 36. TSOT, 0 mm2 of PCB Copper, TA = 25°C
ILOAD
ILOAD
ILOAD
ILOAD
1.0
= 1mA
= 10mA
= 25mA
= 50mA
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
Figure 39. TSOT, 0 mm2 of PCB Copper, TA = 50°C
Rev. G | Page 15 of 20
4.5
06901-033
100
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
JUNCTION TEMPERATURE, TJ (°C)
120
06901-028
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
ADP121
Data Sheet
140
140
100
80
= 1mA
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
120
100
80
60
40
ILOAD
ILOAD
ILOAD
ILOAD
20
0
0.5
Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
140
MAX JUNCTION TEMPERATURE
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
100
80
60
40
0
0.5
Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C
140
JUNCTION TEMPERATURE, TJ (°C)
80
60
40
1.5
ILOAD = 50mA
ILOAD = 75mA
2.0
2.5
3.0
VIN – VOUT (V)
ILOAD = 100mA
ILOAD = 150mA
3.5
4.0
4.5
3.5
4.0
4.5
120
100
80
60
40
20
0
0.5
06901-044
1.0
2.0
2.5
3.0
VIN – VOUT (V)
MAX JUNCTION
TEMPERATURE
100
0
0.5
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
140
MAX JUNCTION
TEMPERATURE
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 25mA
1.0
= 1mA
= 10mA
= 25mA
= 50mA
Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C
120
20
ILOAD
ILOAD
ILOAD
ILOAD
20
06901-046
100
= 1mA
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
120
Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C
ILOAD
ILOAD
ILOAD
ILOAD
1.0
= 1mA
= 10mA
= 25mA
= 50mA
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C
Rev. G | Page 16 of 20
4.5
06901-047
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
120
06901-043
JUNCTION TEMPERATURE, TJ (°C)
1.5
ILOAD = 75mA
ILOAD = 100mA
ILOAD = 150mA
Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C
140
JUNCTION TEMPERATURE, TJ (°C)
1.0
= 1mA
= 10mA
= 25mA
= 50mA
06901-045
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
120
06901-042
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
Data Sheet
ADP121
140
GND
GND
ANALOG DEVICES
ADP121-xx-EVALZ
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
120
100
C1
60
40
20
C2
U1
80
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= 1mA
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
J1
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
VOUT
06901-048
VIN
Figure 46. TSOT, 100 mm2 of PCB Copper, Board Temperature = 85°C
GND
EN
GND
Figure 48. Example of TSOT PCB Layout
100
80
60
40
20
0
0.5
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= 1mA
= 10mA
= 25mA
= 50mA
= 75mA
= 100mA
= 150mA
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
3.5
4.0
4.5
06901-049
JUNCTION TEMPERATURE, TJ (°C)
MAX JUNCTION TEMPERATURE
120
06901-034
140
Figure 47. WLCSP, 100 mm2 of PCB Copper, Board Temperature = 85°C
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP121. However,
as can be seen from Table 6 and Table 7, a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
06901-050
PCB LAYOUT CONSIDERATIONS
Figure 49. Example of WLCSP PCB Layout—Top Side
06901-051
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use 0402 or 0603 size capacitors and
resistors to achieve the smallest possible footprint solution on
boards where area is limited.
Figure 50. Example of WLCSP PCB Layout—Bottom Side
Rev. G | Page 17 of 20
ADP121
Data Sheet
OUTLINE DIMENSIONS
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
0.95 BSC
1.90
BSC
*0.90 MAX
0.70 MIN
0.10 MAX
0.50
0.30
0.20
0.08
8°
4°
0°
SEATING
PLANE
0.60
0.45
0.30
100708-A
*1.00 MAX
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 51. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
0.860
0.820 SQ
0.780
2
1
A
BALL A1
IDENTIFIER
B
0.40
REF
TOP VIEW
BOTTOM VIEW
(BALL SIDE DOWN)
0.660
0.600
0.540
END VIEW
(BALL SIDE UP)
0.381
0.356
0.331
SEATING
PLANE
0.280
0.260
0.240
0.230
0.200
0.170
Figure 52. 4-Ball Wafer Level Chip Scale- Package [WLCSP]
(CB-4-2)
Dimensions show in millimeters
Rev. | Page 18 of 20
07-10-2012-A
COPLANARITY
0.05
Data Sheet
ADP121
ORDERING GUIDE
Model1
ADP121-AUJZ12R7
ADP121-AUJZ15R7
ADP121-AUJZ18R7
ADP121-AUJZ20R7
ADP121-AUJZ25R7
ADP121-AUJZ28R7
ADP121-AUJZ30R7
ADP121-AUJZ33R7
ADP121-ACBZ12R7
ADP121-ACBZ15R7
ADP121-ACBZ165R7
ADP121-ACBZ18R7
ADP121-ACBZ188R7
ADP121-ACBZ20R7
ADP121-ACBZ25R7
ADP121-ACBZ28R7
ADP121-ACBZ30R7
ADP121-ACBZ33R7
ADP121CB-1.2-EVALZ
ADP121CB-1.5-EVALZ
ADP121CB-1.8-EVALZ
ADP121CB-2.0-EVALZ
ADP121CB-2.5-EVALZ
ADP121CB-2.8-EVALZ
ADP121CB-3.0-EVALZ
ADP121CB-3.3-EVALZ
ADP121UJZ-REDYKIT
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output
Voltage (V)2
1.2
1.5
1.8
2.0
2.5
2.8
3.0
3.3
1.2
1.5
1.65
1.8
1.875
2.0
2.5
2.8
3.0
3.3
1.2
1.5
1.8
2.0
2.5
2.8
3.0
3.3
Package Description
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
4-Ball WLCSP
ADP121 1.2 V Output Evaluation Board
ADP121 1.5 V Output Evaluation Board
ADP121-1 1.8 V Output Evaluation Board
ADP121-1 2.0 V Output Evaluation Board
ADP121-1 2.5 V Output Evaluation Board
ADP121-1 2.8 V Output Evaluation Board
ADP121-1 3.0 V Output Evaluation Board
ADP121-1 3.3 V Output Evaluation Board
Evaluation Board Kit
1
Z = RoHS Compliant Part.
For additional voltage options, contact your local Analog Devices, Inc., sales or distribution representative.
3
The WLCSP package option is halide free.
2
Rev. G | Page 19 of 20
Package
Option3
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
CB-4-2
Branding
LC0
LC1
LC7
LC9
LCA
LA3
LA4
LA5
LC0
LC1
LC4
LC7
LC8
LC9
LCA
LCD
LCF
LCG
ADP121
Data Sheet
NOTES
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06901-0-8/12(G)
Rev. G | Page 20 of 20