OBSOLETE DS90CF583, DS90CF584 www.ti.com SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz Check for Samples: DS90CF583, DS90CF584 FEATURES DESCRIPTION • • • • • • • • • • • • • The DS90CF583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data sDS90CF563MTD is no longer available.treams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF584 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CONTROL) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers. 1 2 20 to 65 MHz Shift Clk Support Up to 227 Mbytes/s Bandwidth Cable Size is Reduced to Save Cost 290 mV Swing LVDS Devices for Low EMI Low Power CMOS Design (< 550 mW typ) Power-down Mode Saves Power (< 0.25 mW) PLL Requires No External Components Low Profile 56-Lead TSSOP Package Falling Edge Data Strobe Compatible with TIA/EIA-644 LVDS Standard Single Pixel Per Clock XGA (1024 x 768) Supports VGA, SVGA, XGA and Higher 1.8 Gbps Throughput This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. BLOCK DIAGRAM Figure 1. See Package Number DGG0056A Figure 2. See Package Number DGG0056A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996–2013, Texas Instruments Incorporated OBSOLETE DS90CF583, DS90CF584 SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 www.ti.com APPLICATION These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 OBSOLETE DS90CF583, DS90CF584 www.ti.com SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.3V to +6V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec) Maximum Power Dissipation @ 25°C +260°C DGG0056A (TSSOP) Package: DS90CF583 Package Derating: 1.63W DS90CF584 1.61W DS90CF583 12.5 mW/°C above +25°C DS90CF584 12.4 mW/°C above +25°C This device does not meet 2000V ESD rating (3). (1) (2) (3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation. ESD Rating: HBM (1.5 kΩ, 100 pF) PLL VCC ≥ 1000V All other pins ≥ 2000V EIAJ (0Ω, 200 pF) ≥ 150V Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC) 4.75 5.0 5.25 V Operating Free Air Temperature (TA) −10 +25 +70 °C Receiver Input Range 0 Supply Noise Voltage (VCC) 2.4 V 100 mVP-P Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units VCC V 0.8 V CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VIL Low Level Input Voltage VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.1 0.3 V VCL Input Clamp Voltage ICL = −18 mA −0.7 9 −1.5 V IIN Input Current VIN = VCC, GND, 2.5V or 0.4V ±5.1 IOS Output Short Circuit Current VOUT = 0V GND 3.8 4.9 V ±10 μA −120 mA 450 mV 35 mV 1.37 5 V 35 mV 1.6 V LVDS DRIVER DC SPECIFICATIONS VOD Differential Output Voltage ΔVOD Change in VOD between RL = 100Ω 250 290 Complementary Output States VCM Common Mode Voltage ΔVCM Change in VCM between 1.1 1.25 Complementary Output States VOH High Level Output Voltage VOL Low Level Output Voltage IOS Output Short Circuit Current 1.3 0.9 VOUT = 0V, RL = 100Ω Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 1.01 −2.9 V −5 Submit Documentation Feedback mA 3 OBSOLETE DS90CF583, DS90CF584 SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol IOZ Parameter Conditions Output TRI-STATE Current Min Power Down = 0V, VOUT = 0V or VCC Typ Max Units ±1 ±10 μA +100 mV LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V −100 VIN = +2.4V mV VCC = 5.5V VIN = 0V ±10 μA ±10 μA TRANSMITTER SUPPLY CURRENT ICCTW ICCTG ICCTZ Transmitter Supply Current, RL = 100Ω, CL = 5 pF, f = 32.5 MHz 49 63 mA Worst Case Worst Case Pattern f = 37.5 MHz 51 64 mA (Figure 3, Figure 5) f = 65 MHz 70 84 mA Transmitter Supply Current, RL = 100Ω, CL = 5 pF, f = 32.5 MHz 40 55 mA 16 Grayscale 16 Grayscale Pattern f = 37.5 MHz 41 55 mA (Figure 4, Figure 5) f = 65 MHz 55 67 mA 1 25 μA 64 77 mA Transmitter Supply Current, Power Down = Low Power Down RECEIVER SUPPLY CURRENT ICCRW ICCRG ICCRZ Receiver Supply Current, CL = 8 pF, f = 32.5 MHz Worst Case Worst Case Pattern f = 37.5 MHz 70 85 mA (Figure 3, Figure 6) f = 65 MHz 110 140 mA Receiver Supply Current, CL = 8 pF, f = 32.5 MHz 35 55 mA 16 Grayscale 16 Grayscale Pattern f = 37.5 MHz 37 55 mA (Figure 4, Figure 6) f = 65 MHz 55 67 mA 1 10 μA Receiver Supply Current, Power Down = Low Power Down Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Typ Max Units LLHT Symbol LVDS Low-to-High Transition Time (Figure 5) Parameter 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 5) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 7) 8 ns TCCS TxOUT Channel-to-Channel Skew 350 ps TCCD TxCLK IN to TxCLK OUT Delay @ 25°C, VCC = 5.0V 8.5 ns (1) Min (Figure 8) 3.5 (Figure 11) TCIP TxCLK IN Period (Figure 9) TCIH TxCLK IN High Time (Figure 9) TCIL TxCLK IN Low Time (Figure 9) TSTC TxIN Setup to TxCLK IN (Figure 9 ) THTC TxIN Hold to TxCLK IN (Figure 9) TPDD Transmitter Powerdown Delay (Figure 20) 100 ns TPLLS Transmitter Phase Lock Loop Set (Figure 13) 10 ms TPPos0 Transmitter Output Pulse Position 0 (Figure 15) −0.30 0 0.30 ns TPPos1 Transmitter Output Pulse Position 1 1.70 1/7 Tclk 2.50 ns TPPos2 Transmitter Output Pulse Position 2 3.60 2/7 Tclk 4.50 ns TPPos3 Transmitter Output Pulse Position 3 5.90 3/7 Tclk 6.75 ns (1) 4 f = 65 MHz 15 T 50 ns 0.35T 0.5T 0.65T ns 0.35T 0.5T 0.65T ns 5 3.5 ns 2.5 1.5 ns This limit based on bench characterization. Submit Documentation Feedback Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 OBSOLETE DS90CF583, DS90CF584 www.ti.com SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 Transmitter Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units TPPos4 Transmitter Output Pulse Position 4 8.30 4/7 Tclk 9.00 ns TPPos5 Transmitter Output Pulse Position 5 10.40 5/7 Tclk 11.10 ns TPPos6 Transmitter Output Pulse Position 6 12.70 6/7 Tclk 13.40 ns Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time (Figure 6) 2.5 4.0 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 6) 2.0 3.5 ns RCOP RxCLK OUT Period 15 T 50 ns RCOH RxCLK OUT High Time f = 65 MHz 7.8 9 ns RCOL RxCLK OUT Low Time f = 65 MHz 3.8 5 ns RSRC RxOUT Setup to RxCLK OUT f = 65 MHz 2.5 4.2 ns RHRC RxOUT Hold to RxCLK OUT f = 65 MHz 4.0 5.2 ns RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 5.0V 6.4 10.7 ns 10 ms 1 μs (Figure 12) RPLLS Receiver Phase Lock Loop Set (Figure 14) (1) RSKM RxIN Skew Margin RPDD Receiver Powerdown (Figure 19) (1) (Figure 16) VCC = 5V, TA =25°C 600 ps Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle) AC Timing Diagrams Figure 3. “Worst Case” Test Pattern Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 Submit Documentation Feedback 5 OBSOLETE DS90CF583, DS90CF584 SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 www.ti.com (1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. (2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. (3) Figure 3 and Figure 4 show a falling edge data strobe (TxCLK IN/RxCLK OUT). (4) Recommended pin to signal mapping. Customer may choose to define differently. Figure 4. “16 Grayscale” Test Pattern Figure 5. DS90CF583 (Transmitter) LVDS Output Load and Transition Times Figure 6. DS90CF584 (Receiver) CMOS/TTL Output Load and Transition Times 6 Submit Documentation Feedback Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 OBSOLETE DS90CF583, DS90CF584 www.ti.com SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 Figure 7. DS90CF583 (Transmitter) Input Clock Transition Time Note:Measurements at Vdiff = 0V Note: TCSS measured between earliest and latest LVDS edges. Note: TxCLK Differential High→Low Edge Figure 8. DS90CF583 (Transmitter) Channel-to-Channel Skew and Pulse Width Figure 9. DS90CF583 (Transmitter) Setup/Hold and High/Low Times Figure 10. DS90CF584 (Receiver) Clock In to Clock Out Delay Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 Submit Documentation Feedback 7 OBSOLETE DS90CF583, DS90CF584 SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 www.ti.com Figure 11. DS90CF583 (Transmitter) Clock In to Clock Out Delay Figure 12. DS90CF584 (Receiver) Clock In to Clock Out Delay Figure 13. DS90CF583 (Transmitter) Phase Lock Loop Set Time Figure 14. DS90CF584 (Receiver) Phase Lock Loop Set Time 8 Submit Documentation Feedback Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 OBSOLETE DS90CF583, DS90CF584 www.ti.com SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 Figure 15. Receiver LVDS Input Pulse Position Measurement SW—Setup and Hold Time (Internal Data Sampling Window) TCCS—Transmitter Output Skew RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) Cable Skew—typically 10 ps–40 ps per foot Figure 16. Receiver LVDS Input Skew Margin Figure 17. Seven Bits of LVDS in One Clock Cycle Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 Submit Documentation Feedback 9 OBSOLETE DS90CF583, DS90CF584 SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 www.ti.com Figure 18. Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF583) Figure 19. Receiver Powerdown Delay Figure 20. Transmitter Powerdown Delay DS90CF583 Pin Descriptions—FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL) TxOUT+ O 4 Positive LVDS differential data output TxOUT− O 4 Negative LVDS differential data output FPSHIFT IN I 1 TTL level clock input. The falling edge acts as data strobe TxCLK OUT+ O 1 Positive LVDS differential clock output TxCLK OUT− O 1 Negative LVDS differential clock output PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down VCC I 4 Power supply pins for TTL inputs 10 Description Submit Documentation Feedback Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 OBSOLETE DS90CF583, DS90CF584 www.ti.com SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 DS90CF583 Pin Descriptions—FPD Link Transmitter (continued) I/O No. GND Pin Name I 5 Ground pins for TTL inputs Description PLL VCC I 1 Power supply pin for PLL PLL GND I 2 Ground pins for PLL LVDS VCC I 1 Power supply pin for LVDS outputs LVDS GND I 3 Ground pins for LVDS outputs I/O No. RxIN+ I 4 Positive LVDS differential data inputs RxIN− I 4 Negative LVDS differential data inputs RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL) RxCLK IN+ I 1 Positive LVDS differential clock input RxCLK IN− I 1 Negative LVDS differential clock input FPSHIFT OUT O 1 TTL level clock output. The falling edge acts as data strobe PWR DOWN I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state VCC I 4 Power supply pins for TTL outputs GND I 5 Ground pins for TTL outputs PLL VCC I 1 Power supply for PLL PLL GND I 2 Ground pin for PLL LVDS VCC I 1 Power supply pin for LVDS inputs LVDS GND I 3 Ground pins for LVDS inputs DS90CF584 Pin Descriptions—FPD Link Receiver Pin Name Description Connection Diagram Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 Submit Documentation Feedback 11 OBSOLETE DS90CF583, DS90CF584 SNLS108B – NOVEMBER 1996 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 1996–2013, Texas Instruments Incorporated Product Folder Links: DS90CF583 DS90CF584 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated