Cypress CY62157ESL 8-mbit (512k x 16) static ram automatic power down when deselected Datasheet

CY62157ESL MoBL
8-Mbit (512K x 16) Static RAM
Features
■
Very high speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical Standby current: 2 A
❐ Maximum Standby current: 8 A
■
Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE HIGH or both BHE and
BLE are HIGH). The input or output pins (I/O0 through I/O15) are
placed in a high impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), both the Byte
High Enable and the Byte Low Enable are disabled (BHE, BLE
HIGH), or during an active write operation (CE LOW and WE
LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A18). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18).
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP) II
package
Functional Description
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL) in portable
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Logic Block Diagram
ROW DECODER
SENSE AMPS
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
512K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Cypress Semiconductor Corporation
Document #: 001-43141 Rev. *C
•
198 Champion Court
A17
A18
A16
A15
BLE
A14
BHE
A11
A12
A13
CE
Power Down
Circuit
•
BHE
WE
CE
OE
BLE
San Jose, CA 95134-1709
•
408-943-2600
Revised June 29, 2011
CY62157ESL MoBL
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document #: 001-43141 Rev. *C
Ordering Information ...................................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
CY62157ESL MoBL
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
Product Portfolio
Power Dissipation
Product
CY62157ESL
Range
Industrial
VCC Range (V) [1]
2.2 V–3.6 V and 4.5 V–5.5 V
Speed
(ns)
45
Operating ICC, (mA)
f = 1MHz
f = fmax
Standby, ISB2
(A)
Typ[2]
Max
Typ [2]
Max
Typ [2]
Max
1.8
3
18
25
2
8
Notes
1. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
Document #: 001-43141 Rev. *C
Page 3 of 16
CY62157ESL MoBL
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................–65 °C to +150 °C
Ambient Temperature with
Power Applied ...........................................–55 °C to +125 °C
Supply Voltage to Ground Potential ............... –0.5 V to 6.0 V
DC Voltage Applied to Outputs
in High-Z State[3, 4] .........................................–0.5 V to 6.0 V
Static Discharge Voltage .......................................... >2001 V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Device
CY62157ESL
Ambient
Temperature
Range
VCC[5]
Industrial –40 °C to +85 °C
DC Input Voltage[3, 4] ......................................–0.5 V to 6.0 V
2.2 V–3.6 V,
and 4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
45 ns
Parameter
VOH
VOL
VIH
VIL
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Test Conditions
Min
Typ[6]
Max
Unit
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
–
–
V
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
–
–
2.2 < VCC < 2.7
IOL = 0.1 mA
–
–
0.4
2.7 < VCC < 3.6
IOL = 2.1 mA
–
–
0.4
4.5 < VCC < 5.5
IOL = 2.1 mA
–
–
0.4
2.2 < VCC < 2.7
1.8
–
VCC + 0.3
2.7 < VCC < 3.6
2.2
–
VCC + 0.3
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
2.2 < VCC < 2.7
–0.3
–
0.6
2.7 < VCC < 3.6
–0.3
–
0.8
4.5 < VCC < 5.5
–0.5
–
0.8
GND < VI < VCC
–1
–
+1
V
V
V
A
IIX
Input leakage current
IOZ
Output leakage current GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC operating supply
current
–
18
25
mA
–
1.8
3
–
2
8
A
–
2
8
A
ISB1[7]
ISB2[7]
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA,
CMOS levels
Automatic CE power
CE > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
down current — CMOS f = fmax (address and data only),
inputs
f = 0 (OE, BHE, BLE and WE), VCC = VCC(max)
Automatic CE power
CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
down current — CMOS f = 0, VCC = VCC(max)
inputs
Notes
3. VIL (min) = –2.0 V for pulse durations less than 20 ns.
4. VIH (max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
7. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1/ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 001-43141 Rev. *C
Page 4 of 16
CY62157ESL MoBL
Capacitance
Parameter[8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
TSOP II
Unit
77
C/W
13
C/W
Thermal Resistance
Parameter[8]
Description
Test Conditions
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
Figure 2. AC Test Loads and Waveforms
R1
VCC
VCC
OUTPUT
10%
GND
R2 Rise Time = 1 V/ns
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
Parameters
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800

R2
15385
1554
990

RTH
8000
645
639

VTH
1.20
1.75
1.77
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-43141 Rev. *C
Page 5 of 16
CY62157ESL MoBL
Data Retention Characteristics
Over the Operating Range
Min
Typ[9]
Max
Unit
1.5
–
–
V
VCC = 1.5 V
–
2
5
A
VCC = 2.0 V
–
2
8
Chip deselect to data
retention time
0
–
–
ns
Operation recovery time
45
–
–
ns
Parameter
Description
VDR
VCC for data retention
ICCDR[10]
Data retention current
tCDR
[11]
tR [12]
Conditions
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
CE or
BHE.BLE
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
[13]
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
10. 10Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1/ISB2 / ICCDR spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 001-43141 Rev. *C
Page 6 of 16
CY62157ESL MoBL
Switching Characteristics
Over the Operating Range
Parameter[14]
Description
45 ns
Unit
Min
Max
45
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
OE LOW to
LOW-Z[15]
5
–
ns
tHZOE
OE HIGH to
High-Z[15, 16]
–
18
ns
tLZCE
CE LOW to Low-Z[15]
10
–
ns
–
18
ns
tLZOE
High-Z[15, 16]
tHZCE
CE HIGH to
tPU
CE LOW to power up
0
–
ns
tPD
CE HIGH to power down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
45
ns
BLE/BHE LOW to
Low-Z[15, 17]
5
–
ns
BLE/BHE HIGH to
HIGH-Z[15, 16]
–
18
ns
tLZBE
tHZBE
Write Cycle[18]
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
ns
tHA
Address hold from write end
0
–
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
tHZWE
tLZWE
0
–
ns
WE LOW to
High-Z[15, 16]
–
18
ns
WE HIGH to
Low-Z[15]
10
–
ns
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0
to 3 V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
17. If both byte enables are toggled together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-43141 Rev. *C
Page 7 of 16
CY62157ESL MoBL
Switching Waveforms
Figure 4. Read Cycle No.1: Address Transition Controlled. [19, 20]
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled [20, 21]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
ICC
50%
50%
ISB
Notes
19. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE, BHE, BLE transition LOW.
Document #: 001-43141 Rev. *C
Page 8 of 16
CY62157ESL MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled [22, 23, 24]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 25
tHD
DATAIN
tHZOE
Figure 7. Write Cycle 2: CE Controlled [22, 23, 24]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 25
tHZOE
Notes
22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-43141 Rev. *C
Page 9 of 16
CY62157ESL MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle 3: WE controlled, OE LOW [26, 27, 28]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
NOTE 29
tHD
DATAIN
tLZWE
tHZWE
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [26, 27, 28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 29
tSD
tHD
DATAIN
tLZWE
Notes
26. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
27. Data I/O is high impedance if OE = VIH.
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
29. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-43141 Rev. *C
Page 10 of 16
CY62157ESL MoBL
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High-Z
Deselect/power down
Standby (ISB)
X[30]
X
X
H
H
High-Z
Deselect/power down
Standby (ISB)
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
L
High-Z
Output disabled
Active (ICC)
L
H
H
L
H
High-Z
Output disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Note
30. The ‘X’ (Don’t care) state for the Chip enable in the truth table refers to the logic state (either HIGH or LOW). Intermediate voltage levels on this pin is not permitted.
Document #: 001-43141 Rev. *C
Page 11 of 16
CY62157ESL MoBL
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
CY62157ESL-45ZSXI
Package Type
51-85087 44-pin thin small outline package type II (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 5
7
E SL
-
45
xxx
I
Temperature Range
ZSX = 44-pin TSOP II (Pb-free)
45 = Speed Grade
Separator
SL = Voltage range (3 V typical; 5 V typical)
E = Process Technology 90 nm
Buswidth = × 16
Density = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document #: 001-43141 Rev. *C
Page 12 of 16
CY62157ESL MoBL
Package Diagram
Figure 10. 44-Pin TSOP II, 51-85087
PIN 1 I.D.
11.938 (0.470)
11.735 (0.462)
10.262 (0.404)
10.058 (0.396)
1
22
Z Z Z
Z X Z
AA
44
23
BOTTOM VIEW
TOP VIEW
0.800 BSC
(0.0315)
0.400(0.016)
0.300 (0.012)
EJECTOR MARK
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
BASE PLANE
10.262 (0.404)
10.058 (0.396)
0.10 (.004)
18.517 (0.729)
18.313 (0.721)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
0.210 (0.0083)
0.120 (0.0047)
0°-5°
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
DIMENSION IN MM (INCH)
MAX
MIN.
51-85087-*C
Document #: 001-43141 Rev. *C
Page 13 of 16
CY62157ESL MoBL
Acronyms
Acronym
Description
BHE
byte high enable
BLE
byte low enable
CE
chip enable
CMOS
complementary metal oxide semiconductor
I/O
input/output
OE
output enable
SRAM
static random access memory
TSOP
thin small outline package
WE
write enable
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
A
microamperes
mA
milliamperes
MHz
megahertz
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Document #: 001-43141 Rev. *C
Page 14 of 16
CY62157ESL MoBL
Document History Page
Document Title: CY62157ESL MoBL 8-Mbit (512K x 16) Static RAM
Document Number: 001-43141
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
1875228
See ECN
*A
2943752
06/03/2010
VKN
*B
3109266
12/13/2010
PRAS
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*C
3295175
06/29/2011
RAME
Remove reference to AN1064 SRAM system guidelines.
Added ISB1 and ICCDR to footnotes 7 and 10. Added footnote 8 for Capacitance
and Thermal Resistance section.
Updated Ordering Code Definitions.
Added Document Conventions.
Updated Table of Contents.
Document #: 001-43141 Rev. *C
VKN/AESA New Data Sheet
Added Contents
Added footnote for the ISB2 parameter in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagram
Added Sales, Solutions, and Legal Information
Page 15 of 16
CY62157ESL MoBL
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2008–2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-43141 Rev. *C
Revised June 29, 2011
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