TI1 DS90UB925QSQ/NOPB 5 to 85 mhz 24-bit color fpd-link iii serializer with bidirectional control channel Datasheet

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DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
DS90UB925Q-Q1 5 to 85 MHz 24-Bit Color FPD-Link III Serializer
With Bidirectional Control Channel
1 Features
3 Description
•
The DS90UB925Q-Q1 serializer, in conjunction with
the DS90UB926Q-Q1 deserializer, provides a
complete digital interface for concurrent transmission
of high-speed video, audio, and control data for
automotive display and image sensing applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bidirectional Control Interface Channel Interface
with I2C Compatible Serial Control Bus
Supports High Definition (720 p) Digital Video
Format
RGB888 + VS, HS, DE and I2S Audio Supported
Supports Two 10–bit Camera Video Streams
5 – 85MHz PCLK Supported
Single 3.3 V Operation with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect Up to 10 Meters
Parallel LVCMOS Video Inputs
DC-Balanced and Scrambled Data with
Embedded Clock
Supports Repeater Application
Internal Pattern Generation
Low Power Modes Minimize Power Dissipation
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
>8kV HBM and ISO 10605 ESD Rating
Backward Compatible to FPD-Link II
The DS90UB925Q-Q1 serializer embeds the clock,
DC scrambles & balances the data payload, and level
shifts the signals to high-speed low voltage
differential signaling. Up to 24 data bits are serialized
along the video control signals.
Serial transmission is optimized by a user selectable
de-emphasis. EMI is minimized by the use of low
voltage differential signaling, data scrambling and
randomization and spread spectrum clocking
compatibility.
2 Applications
•
•
•
•
The chipset is ideally suited for automotive videodisplay systems with HD formats and automotive
vision systems with megapixel resolutions. The
DS90UB925Q-Q1
incorporates
an
embedded
bidirectional control channel and low latency GPIO
controls. This chipset translates a parallel interface
into a single pair high-speed serialized interface. The
serial bus scheme, FPD-Link III, supports full duplex
of high-speed video data transmission and
bidirectional control communication over a single
differential link. Consolidation of video data and
control over a single differential pair reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
Automotive Display for Navigation
Rear Seat Entertainment Systems
Automotive Driver Assistance
Automotive Megapixel Camera Systems
Device Information(1)
PART NUMBER
DS90UB925Q-Q1
PACKAGE
WQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Digital Display Interface
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
DOUT+
SCL
SDA
IDx
RIN+
DOUT-
RIN100: STP Cable
DS90UB925Q-Q1
Serializer
PDB
I2S AUDIO
(STEREO)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
3
MODE_SEL
INTB
DAP
PDB
OSS_SEL
OEN
MODE_SEL
DS90UB926Q-Q1
Deserializer
SCL
SDA
IDx
LOCK
PASS
3
INTB_IN
RGB Display
720p
24-bit color depth
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
7
Absolute Maximum Ratings ..................................... 7
Handling Ratings....................................................... 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
DC Electrical Characteristics .................................... 8
AC Electrical Characteristics................................... 10
Recommended Timing for the Serial Control Bus .. 11
Switching Characteristics ........................................ 13
Typical Charateristics ............................................. 14
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 22
7.5 Programming .......................................................... 25
7.6 Register Maps ........................................................ 27
8
Application and Implementation ........................ 38
8.1 Application Information............................................ 38
8.2 Typical Application .................................................. 38
9
Power Supply Recommendations...................... 41
9.1 Power Up Requirements and PDB Pin ................... 41
9.2 CML Interconnect Guidelines.................................. 41
10 Layout................................................................... 42
10.1 Layout Guidelines ................................................. 42
10.2 Layout Example .................................................... 43
11 Device and Documentation Support ................. 45
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
45
45
45
45
12 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Added data sheet flow and layout to conform with new TI standards. Added the following sections: Handling
Ratings, Device Functional Modes; Programming; Power Supply Recommendations; Layout; Device and
Documentation Support; Mechanical, Packaging and Ordering Information.......................................................................... 1
•
Added Device Information table ............................................................................................................................................. 1
•
Fixed typo for GPIO configuration ........................................................................................................................................ 19
•
Removed two MODE_SEL modes: I2S Channel B, and Backward Compatible.................................................................. 23
•
Removed IDx addresses 0x22, 0x24, 0x2E, 0x30, 0x32, 0x34............................................................................................ 26
•
Changed suggested resistor values for IDx addresses 0x1E, 0x20, 0x26, 0x28, 0x2A....................................................... 26
Changes from Revision B (August 2012) to Revision C
•
Page
Changed layout of National datasheet to TI format................................................................................................................ 1
Changes from Revision A (July 2012) to Revision B
Page
•
Added typical charateristic graphics ..................................................................................................................................... 14
•
Added” Note: frequency range = 15 - 65MHz when LFMODE = 0 and frequency range = 5 - <15MHz when
LFMODE = 1.” under Functional Description. ...................................................................................................................... 16
•
Reformatted Table 2 and added clarification to notes.......................................................................................................... 19
•
Added clarification to notes on Table 6, address 0x04[3:0] (backwards compatible and LFMODE registers). .................. 27
2
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Changes from Original (March 2012) to Revision A
Page
•
Converted to hybrid TI format................................................................................................................................................. 1
•
Corrected typo in SCL from pin 6 to pin 8. ............................................................................................................................. 4
•
Corrected typo in SDA from pin 7 to pin 9.............................................................................................................................. 4
•
Added to Absolute Maximum Rating section, note (3): The maximum limit (VDDIO +0.3V) does not apply to the PDB
pin during the transition to the power down state (PDB transitioning from HIGH to LOW).................................................... 7
•
Deleted derate from Maximum Power Dissipation Capacity at 25°C. .................................................................................... 7
•
Added "Note: BIST is not available in backwards compatible mode." ................................................................................. 20
•
Corrected typo in Table 4 "I2S Channel B (18-bit Mode)" from L to H ............................................................................... 23
•
Corrected typo in Table 5 Ideal VR2(V) from 2.475 to 1.475. .............................................................................................. 26
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SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
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5 Pin Configuration and Functions
DIN8 / G0 / GPIO2
DIN7 / R7
DIN6 / R6
DIN5 / R5
INTB
VDDIO
DIN4 / R4
DIN3 / R3
DIN2 / R2
DIN1 / R1 / GPIO1
DIN0 / R0 / GPIO0
35
34
33
32
31
30
29
28
27
26
25
DIN9 / G1 / GPIO3
36
DS90UB925Q-Q1
48 Pin WQFN
Top View
G2 / DIN10
37
24
MODE_SEL
G3 / DIN11
38
23
CMF
G4 / DIN12
39
22
VDD33
G5 / DIN13
40
21
PDB
20
DOUT+
19
DOUT-
18
RES1
G6 / DIN14
41
G7 / DIN15
42
GPO_REG4 / B0 / DIN16
43
I2S_DB / GPO_REG5 / B1 / DIN17
44
17
CAPHS12
B2 / DIN18
45
16
NC
DS90UB925Q-Q1
TOP VIEW
DAP = GND
11
12
GPO_REG7 / I2S_WC
9
10
SDA
PCLK
GPO_REG6 / I2S_DA
7
8
SCL
6
CAPL12
5
DE
IDx
I2S_CLK / GPO_REG8
3
13
4
48
VS
B5 / DIN21
HS
CAPP12
2
RES0
14
B7 / DIN23
15
47
1
46
B4 / DIN20
B6 / DIN22
B3 / DIN19
Pin Functions
PIN NAME
PIN #
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
DIN[23:0] /
R[7:0],
G[7:0],
B[7:0]
25, 26, 27, 28,
29, 32, 33, 34,
35, 36, 37, 38,
39, 40, 41, 42,
43, 44, 45, 46,
47, 48, 1, 2
I, LVCMOS
w/ pull down
Parallel Interface Data Input Pins
Leave open if unused
DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as GPIO1
DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as GPIO3
DIN16 / B0 can optionally be used as GPIO4 and DIN17 / B1 can optionally be used as
GPIO5
HS
3
I, LVCMOS
w/ pull down
Horizontal Sync Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
VS
4
I, LVCMOS
w/ pull down
Vertical Sync Input Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
4
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Pin Functions (continued)
PIN NAME
PIN #
I/O, TYPE
DESCRIPTION
DE
5
I, LVCMOS
w/ pull down
Data Enable Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
PCLK
10
I, LVCMOS
w/ pull down
Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6.
13, 12, 11
I, LVCMOS
w/ pull down
Digital Audio Interface Data Input Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
I2S_CLK,
I2S_WC,
I2S_DA
OPTIONAL PARALLEL INTERFACE
I2S_DB
44
I, LVCMOS
w/ pull down
GPIO[3:0]
36, 35, 26, 25
GPO_REG[
8:4]
13, 12, 11, 44, O, LVCMOS
43
w/ pull down
Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by
MODE_SEL pin or configuration register
Leave open if unused
I2S_DB can optionally be used as DIN17 or GPO_REG5.
I/O, LVCMOS General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or
w/ pull down configuration register. See Table 6.
Leave open if unused.
Shared with DIN9, DIN8, DIN1 and DIN0
General Purpose Outputs and set by configuration register. See Table 6.
Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or DIN17, DIN16.
CONTROL
PDB
21
I, LVCMOS
w/ pull-down
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to Power Up Requirements and PDB Pin section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL
24
I, Analog
Device Configuration Select. See Table 4.
IDx
6
I, Analog
I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 19.
SCL
8
I/O, LVCMOS I2C Clock Input / Output Interface
Open Drain Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA
9
I/O, LVCMOS I2C Data Input / Output Interface
Open Drain Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
31
O, LVCMOS
Open Drain
I2C
STATUS
INTB
Interrupt
INTB = H, normal
INTB = L, Interrupt request
Recommended pull-up: 4.7kΩ to VDDIO
FPD-LINK III SERIAL INTERFACE
DOUT+
20
O, LVDS
True Output
The output must be AC-coupled with a 0.1µF capacitor.
DOUT-
19
O, LVDS
Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
CMF
23
Analog
Common Mode Filter.
Connect 0.1µF to GND
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Pin Functions (continued)
PIN NAME
PIN #
POWER AND GROUND
I/O, TYPE
DESCRIPTION
(1)
VDD33
22
Power
Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND
VDDIO
30
Power
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPHS12,
CAPP12
CAPL12
17, 14
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
7
CAP
Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
OTHERS
NC
RES[1:0]
(1)
6
16
NC
18, 15
GND
Do not connect.
Reserved. Tie to Ground.
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
MIN
MAX
UNIT
Supply Voltage – VDD33
-0.3
+4.0
V
Supply Voltage – VDDIO
-0.3
+4.0
V
LVCMOS I/O Voltage (3)
-0.3
VDDIO + 0.3
V
Serializer Output Voltage
-0.3
+2.75
V
+150
°C
Junction Temperature
(1)
(2)
(3)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from
HIGH to LOW).
6.2 Handling Ratings
Tstg
Storage temperature range
Human body model (HBM), per AEC Q100-002
V(ESD)
Electrostatic discharge
ESD Rating (IEC 61000-4-2,
powered-up only)
RD= 330Ω, CS = 150pF
ESD Rating (ISO 10605)
RD= 330Ω, CS = 150pF/330pF
RD= 2KΩ, CS = 150pF/330pF
(1)
(1)
MIN
MAX
UNIT
-65
+150
°C
±8
±8
Charged device model (CDM), per AEC Q100-011
±1.25
±1.25
Machine Model (MM)
±250
±250
Air Discharge
(DOUT+, DOUT-)
±15
±15
Contact Discharge
(DOUT+, DOUT-)
±8
±8
Air Discharge
(DOUT+, DOUT-)
±15
±15
Contact Discharge
(DOUT+, DOUT-)
±8
±8
kV
V
kV
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
Supply Voltage (VDD33)
3.0
3.3
3.6
UNIT
V
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
OR
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
PCLK Frequency
5
Supply Noise
85
MHz
100
mVP-P
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6.4 Thermal Information
WQFN
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
35
RθJC(top)
Junction-to-case (top) thermal resistance
5.2
RθJB
Junction-to-board thermal resistance
5.5
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
5.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
(1)
UNIT
48 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
(2) (3)
TYP
MAX
UNIT
2.0
VDDIO
V
GND
0.8
V
LVCMOS I/O DC SPECIFICATIONS
VIH
High Level Input
Voltage
VDDIO = 3.0 to 3.6V
VIL
Low Level Input
Voltage
VDDIO = 3.0 to 3.6V
IIN
Input Current
VIN = 0V or VDDIO = 3.0 to 3.6V
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIN
Input Current
VDDIO = 1.71 to 1.89V
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
VIN = 0V or
VDDIO
VDDIO = 3.0
to 3.6V
DIN[23:0], HS,
VS, DE, PCLK,
I2S_CLK,
I2S_WC,
I2S_DA, I2S_DB
VDDIO
V
GND
0.8
V
GND
0.35*
VDDIO
V
VDDIO = 1.71
to 1.89V
−10
±1
+10
μA
VDDIO = 3.0 to
3.6V
2.4
VDDIO
V
VDDIO - 0.45
VDDIO
V
GND
0.4
V
GND
0.35
V
Output Short Circuit
Current
VOUT = 0V
IOZ
TRI-STATE® Output
Current
VOUT = 0V or VDDIO, PDB = L,
8
0.65*
VDDIO
μA
IOS
(3)
V
+10
IOL = +4mA
(2)
μA
VDDIO
±1
±1
Low Level Output
Voltage
(1)
+10
2.0
−10
IOH = −4mA
VOL
−10
VDDIO = 3.0 to 3.6V
High Level Output
Voltage
VOH
PDB
VDDIO = 1.71
to 1.89V
VDDIO = 3.0 to
3.6V
VDDIO = 1.71
to 1.89V
GPIO[3:0],
GPO_REG[8:4]
−50
−10
mA
+10
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25 °C, and at the Recommended Operating Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
1160
1250
1340
mVp-p
1
50
FPD-LINK III CML DRIVER DC SPECIFICATIONS
VODp-p
Differential Output
Voltage
(DOUT+) – (DOUT-)
ΔVOD
Output Voltage
Unbalance
VOS
Offset Voltage –
Single-ended
ΔVOS
Offset Voltage
Unbalance
Single-ended
IOS
Output Short Circuit
Current
RT
Internal Termination
Resistor - Single
ended
RL = 100Ω,
See Figure 1
2.50.25*VODp-p
RL = 100Ω,
See Figure 1
mV
V
(TYP)
DOUT+, DOUT-
1
50
−38
DOUT+/- = 0V, PDB = L or H
40
mV
mA
52
62
Ω
SERIAL CONTROL BUS
VIH
Input High Level
SDA and SCL
0.7*
VDD33
VDD33
V
VIL
Input Low Level
Voltage
SDA and SCL
GND
0.3*
VDD33
V
VHY
Input Hysteresis
>50
VOL
SDA, IOL = 1.25 mA
Iin
SDA or SCL, VIN = VDD33 or GND
Cin
Input Capacitance
mV
0
0.36
V
-10
10
µA
SDA or SCL
<5
pF
SUPPLY CURRENT
IDD1
IDDIO1
IDDS1
IDDIOS1
Supply Current
(includes load current)
RL = 100Ω, f = 85MHz
Checker Board
Pattern,
See Figure 2
Supply Current
Remote Auto Power
Down Mode
0x01[7] = 1,
deserializer is
powered down
Supply Current Power
Down
PDB = L, All
LVCMOS inputs
are floating or
tied to GND
IDDS2
IDDIOS2
VDD33= 3.6V
VDDIO = 3.6V
VDDIO = 1.89V
VDD33 = 3.6V
VDDIO = 3.6V
VDDIO = 1.89V
VDD33 = 3.6V
VDDIO = 3.6V
VDDIO = 1.89V
VDD33
VDDIO
VDD33
VDDIO
VDD33
VDDIO
148
170
90
180
mA
μA
1
1.6
mA
1.2
2.4
mA
65
150
μA
55
150
μA
1
2
mA
65
150
μA
50
150
μA
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6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(2) (3)
MIN
TYP
MAX
UNIT
GPIO BIT RATE
Forward Channel Bit Rate
BR
Back Channel Bit Rate
See (4)
(5)
See (4)
(5)
f = 5 – 85
MHz
GPIO[3:0]
0.25* f
Mbps
75
kbps
RECOMMENDED TIMING FOR PCLK
tTCP
PCLK Period
tCIH
PCLK Input High Time
tCIL
PCLK Input Low Time
tCLKT
PCLK Input Transition Time,
See Figure 3 (4) (5)
tIJIT
PCLK Input Jitter Tolerance,
Bit Error Rate ≤10–10
(1)
(2)
(3)
(4)
(5)
(6)
(7)
10
f / 40 < Jitter Freq < f / 20 (4)
(7)
PCLK
(6)
11.76
T
200
ns
0.4*T
0.5*T
0.6*T
ns
0.4*T
0.5*T
0.6*T
ns
f = 5 MHz
4.0
ns
f = 85 MHz
0.5
ns
f=5–
78MHz
0.4
0.6
UI
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25 °C, and at the Recommended Operating Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
Jitter Frequency is specified in conjunction with DS90UB926 PLL bandwidth.
UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.
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6.7 Recommended Timing for the Serial Control Bus
Over 3.3V supply and temperature ranges unless otherwise specified.
MIN
fSCL
MAX
UNIT
Standard Mode
0
100
kHz
Fast Mode
0
400
kHz
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Hold time for a start or a
repeated start condition,
See Figure 8
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Set Up time for a start or a
repeated start condition,
See Figure 8
Standard Mode
4.7
µs
Fast Mode
0.6
µs
Data Hold Time,
See Figure 8
Standard Mode
0
0.615
3.45
µs
Fast Mode
0
0.615
0.9
µs
Data Set Up Time,
See Figure 8
Standard Mode
250
0.56
Fast Mode
100
0.56
Set Up Time for STOP
Condition,
See Figure 8
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Bus Free Time
Between STOP and START,
See Figure 8
Standard Mode
4.7
µs
tBUF
Fast Mode
1.3
µs
tr
SCL and SDA Rise Time,
See Figure 8
Standard Mode
430
1000
ns
Fast Mode
430
300
ns
tf
SCL and SDA Fall Time,
See Figure 8
Standard Mode
20
300
ns
Fast mode
20
300
ns
tsp
input Filter
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
tSU;STO
SCL Low Period
SCL High Period
ns
ns
50
DIN[23:0], 30
HS,VS,DE,
I2S
PARALLEL-TO-SERIAL
tLOW
SCL Clock Frequency
TYP
DOUT+
Differential probe
0.1 PF
D
100:
DOUT-
ns
Input Impedance û 100
k:
CL ú 0.5 pF
BW û 3.5 GHz
0.1 PF
SCOPE
BW û 4 GHz
PCLK
DOUT-
Single Ended
VOD
VODVOD+
DOUT+
|
VOS
0V
VOD+
Differential
(DOUT+) - (DOUT-)
0V
VOD-
Figure 1. Serializer VOD DC Output
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VDDIO
PCLK
GND
VDDIO
DIN[n] (odd),
VS, HS
GND
VDDIO
DIN[n] (even),
DE
GND
Figure 2. Checkboard Data Pattern
80%
VDDIO
80%
PCLK
20%
20%
0V
t CLKT
t CLKT
Figure 3. Serializer Input Clock Transition Time
Differential
Signal
80%
80%
20%
20%
tLHT
Vdiff = 0V
tHLT
Figure 4. Serializer CML Output Load and Transition Time
tTCP
VDDIO/2
PCLK
tDIS
VDDIO/2
VDDIO/2
tDIH
VDDIO
DIN[23:0],
HS,VS,DE
VDDIO/2
Setup
Hold
0V
Figure 5. Serializer Setup and Hold Times
PDB
PCLK
1/2 VDDIO
"X"
active
tPLD
DOUT
(Diff.)
Driver OFF, VOD = 0V
Driver On
Figure 6. Serializer Lock Time
12
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tDJIT
tDJIT
VOD (+)
DOUT
(Diff.)
EYE OPENING
0V
VOD (-)
tBIT (1 UI)
Figure 7. Serializer CML Output Jitter
SDA
tf
tHD;STA
tLOW
tr
tf
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 8. Serial Control Bus Timing Diagram
6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tLHT
CML Output Low-to-High
Transition Time
tHLT
CML Output High-to-Low
Transition Time
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
tPLD
Serializer PLL Lock Time
tSD
Delay — Latency
tTJIT
Output Total Jitter,
Bit Error Rate ≥10-10
Figure 7 (2) (3) (4)
(1)
(2)
(3)
(4)
TEST CONDITIONS
R[7:0],
G[7:0],
B[7:0], HS,
VS, DE,
PCLK,
I2S_CLK,
I2S_WC,
I2S_DA
See Figure 5
RL = 100Ω
f = 45MHz
MIN
DOUT+,
DOUT-
See Figure 4
See Figure 6
PIN/FREQ.
(1)
TYP
MAX
UNIT
80
130
ps
80
130
ps
2.0
ns
2.0
ns
f = 15 45MHz
131*T
ns
f = 15 45MHz
145*T
ns
DOUT+,
DOUT-
0.25
0.30
UI
tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.
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CML Serializer Data Throughput
(200 mV/DIV)
6.9 Typical Charateristics
78 MHz TX
Pixel Clock
Input
(2 V/DIV)
78 MHz RX
Pixel Clock
Output
(2 V/DIV)
Time (1.25 ns/DIV)
Time (10 ns/DIV)
Note: On the rising edge of each clock period, the CML driver outputs
a low Stop bit, high Start bit, and 33 DC-scrambled data bits.
Figure 9. Serializer CML Driver Output with 78 MHz TX Pixel
Clock
14
Figure 10. Comparison of Deserializer LVCMOS RX PCLK
Output Locked to a 78 MHz TX PCLK
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7 Detailed Description
7.1 Overview
The DS90UB925Q-Q1 serializer transmits a 35-bit symbol over a single serial FPD-Link III pair operating up to
2.975 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balanced
video data and audio data which enhance signal quality to support AC coupling. The serializer is intended for use
with the DS90UB926Q-Q1 deserializer, but is also backward compatible with DS90UR906Q or DS90UR908Q
FPD-Link II deserializer.
The DS90UB925Q-Q1 serializer and DS90UB926Q-Q1 deserializer incorporate an I2C compatible interface. The
I2C compatible interface allows programming of serializer or deserializer devices from a local host controller. In
addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between
serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel
(serializer to deserializer) as well as lower speed signaling in the reverse channel (deserializer to serializer).
Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link from one
I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either side of
the serial link.
There are two operating modes available on DS90UB925Q-Q1, display mode and camera mode. In display
mode, I2C transactions originate from the host controller attached to the serializer and target either the
deserializer or an I2C slave attached to the deserializer. Transactions are detected by the I2C slave in the
serializer and forwarded to the I2C master in the deserializer. Similarly, in camera mode, I2C transactions
originate from a controller attached to the deserializer and target either the serializer or an I2C slave attached to
the serializer. Transactions are detected by the I2C slave in the deserializer and forwarded to the I2C master in
the serializer.
7.2 Functional Block Diagram
REGULATOR
PDB
MODE_SEL
INTB
SDA
SCL
IDx
Parallel to Serial
3
DC Balance Encoder
I2S_CLK
I2S_WC
I2S_DA
CMF
24
Input latch
DIN [23:0]
HS
VS
DE
PCLK
DOUT +
D
DOUT -
PLL
Timing
and
Control
DS90UB925Q-Q1
Serializer
7.3 Feature Description
7.3.1 High Speed Forward Channel Data Transfer
The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or
YUV data, sync signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 11 illustrates the
serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link.
Data is randomized, balanced and scrambled.
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Feature Description (continued)
C1
C0
Figure 11. FPD-Link III Serial Stream
The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps
maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
7.3.2 Low Speed Back Channel Data Transfer
The Low-Speed Backward Channel (LS_BC) of the DS90UB925Q-Q1 provides bidirectional communication
between the display and host processor. The information is carried back from the Deserializer to the Serializer
per serial symbol. The back channel control data is transferred over the single serial link along with the highspeed forward data, DC balance coding and embedded clock information. This architecture provides a backward
path across the serial link together with a high speed forward channel. The back channel contains the I2C, CRC
and 4 bits of standard GPIO information with 10 Mbps line rate.
7.3.3 Backward Compatible Mode
The DS90UB925Q-Q1 is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link II
deserializers at 5-65 MHz of PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating at
the line rate of 140 Mbps to 1.82 Gbps. The backward configuration mode can be set via MODE_SEL pin
(Table 4) or the configuration register (Table 6). Note: frequency range = 15 – 65MHz when LFMODE = 0 and
frequency range = 5 – <15MHz when LFMODE = 1.
7.3.4 Common Mode Filter Pin (CMF)
The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin
for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.
7.3.5 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 12.
16
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Feature Description (continued)
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 12. Video Control Signal Filter Waveform
7.3.6 EMI Reduction Features
7.3.6.1 Input SSC Tolerance (SSCT)
The DS90UB925Q-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile
up to ±2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.
7.3.7 LVCMOS VDDIO Option
1.8 V or 3.3 V Inputs and Outputs are powered from a separate VDDIO supply to offer compatibility with external
system interface signals.
NOTE
When configuring the VDDIO power supplies, all the single-ended data and control input
pins for device need to scale together with the same operating VDDIO levels.
7.3.8 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the VDDIO, where VDDIO = 3.0V to 3.6V or VDD33. To save power disable the link when the display
is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIO
have reached final levels; no external components are required. In the case of driven by the VDDIO = 3.0V to 3.6V
or VDD33 directly, a 10 kohm resistor to the VDDIO = 3.0V to 3.6V or VDD33 , and a >10uF capacitor to the ground
are required (See Figure 23).
7.3.9 Remote Auto Power Down Mode
The Serializer features a remote auto power down mode. During the power down mode of the pairing
deserializer, the Serializer enters the remote auto power down mode. In this mode, the power dissipation of the
Serializer is reduced significantly. When the Deserializer is powered up, the Serializer enters the normal power
on mode automatically. This feature is enabled through the register bit 0x01[7] Table 6.
7.3.10 Input PCLK Loss Detect
The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A
clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again,
the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registers
values are still RETAINED.
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Feature Description (continued)
7.3.11 Serial Link Fault Detect
The serial link fault detection is able to detect any of following seven (7) conditions:
1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked correctly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address
0x0C Table 6.
7.3.12 Pixel Clock Edge Select (RFB)
The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines
the edge that the data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB
is LOW (‘0’), data is latched on the Falling edge of the PCLK.
7.3.13 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency
of the serializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is
High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,
a PDB reset is required.
7.3.14 Interrupt Pin — Functional Description And Usage (INTB)
1. On DS90UB925, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UB926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UB925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an
interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read ISR register .
5. A read to ISR will clear the interrupt at the DS90UB925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN (pin 16) on the DS90UB926Q-Q1. The system is now ready to return to step (1) at next falling edge
of INTB_IN.
7.3.15 Internal Pattern Generation
The DS90UB925Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and
repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down
mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test
pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application
Note AN-2198 (SNLA132).
7.3.16 GPIO[3:0] and GPO_REG[8:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB925Q-Q1 can be used as the
general purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) application.
7.3.16.1 GPIO[3:0] Enable Sequence
See Table 1 for the GPIO enable sequencing.
18
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Feature Description (continued)
Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UB925Q-Q1 only.
DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.
Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB925Q-Q1, then write 0x05 to
address 0x1F on DS90UB926Q-Q1.
Table 1. GPIO Enable Sequencing Table
#
DESCRIPTION
DEVICE
FORWARD CHANNEL
1
Enable 18-bit
mode
DS90UB925Q-Q1
0x12 = 0x04
0x12 = 0x04
DS90UB926Q-Q1
Auto Load from DS90UB925Q-Q1
Auto Load from DS90UB925Q-Q1
2
GPIO3
DS90UB925Q-Q1
0x0F = 0x03
0x0F = 0x05
3
GPIO2
4
5
GPIO1
GPIO0
BACK CHANNEL
DS90UB926Q-Q1
0x1F = 0x05
0x1F = 0x03
DS90UB925Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UB926Q-Q1
0x1E = 0x50
0x1E = 0x30
DS90UB925Q-Q1
0x0E = 0x03
0x0E = 0x05
DS90UB926Q-Q1
0x1E = 0x05
0x1E = 0x03
DS90UB925Q-Q1
0x0D = 0x93
0x0D = 0x95
DS90UB926Q-Q1
0x1D = 0x95
0x1D = 0x93
7.3.16.2 GPO_REG[8:4] Enable Sequence
GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 2
for the GPO_REG enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UB925Q-Q1 only.
DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.
Step 2: To enable GPO_REG8 outputs an “1”, write 0x90 to address 0x11 on DS90UB925Q.
Table 2. GPO_REG Enable Sequencing Table
#
DESCRIPTION
DEVICE
LOCAL ACCESS
1
Enable 18-bit mode
DS90UB925Q-Q1
0x12 = 0x04
2
GPO_REG8
DS90UB925Q-Q1
0x11 = 0x90
“1”
0x11 = 0x10
“0”
0x11 = 0x09
“1”
0x11 = 0x01
“0”
0x10 = 0x90
“1”
0x10 = 0x10
“0”
3
4
GPO_REG7
GPO_REG6
DS90UB925Q-Q1
DS90UB925Q-Q1
LOCAL OUTPUT
5
GPO_REG5
DS90UB925Q-Q1
0x10 = 0x09
“1”
0x10 = 0x01
“0”
6
GPO_REG4
DS90UB925Q-Q1
0x0F = 0x90
“1”
0x0F = 0x10
“0”
7.3.17 I2S Transmitting
In normal 24-bit RGB operation mode, the DS90UB925Q-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC
and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data
island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must
maintain one fourth of the PCLK rate.
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7.3.17.1 Secondary I2S Channel
In I2S Channel B operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio in
addition to the 3–bit of I2S. The I2S_DB input must be synchronized to I2S_CLK and aligned with I2S_DA and
I2S_WC at the input to the serializer. This operation mode is enabled through either the MODE_SEL pin
(Table 4) or through the register bit 0x12[0] (Table 6).
Table 3 covers the range of I2S sample rates.
Table 3. Audio Interface Frequencies
SAMPLE RATE (kHz)
I2S DATA WORD SIZE (BITS)
I2S CLK (MHz)
32
16
1.024
44.1
16
1.411
48
16
1.536
96
16
3.072
192
16
6.144
32
24
1.536
44.1
24
2.117
48
24
2.304
96
24
4.608
192
24
9.216
32
32
2.048
44.1
32
2.822
48
32
3.072
96
32
6.144
192
32
12.288
7.3.18 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics. Note: BIST is not available in backwards compatible mode.
7.3.18.1 BIST Configuration and Status
The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or
configuration register (Table 6) through the deserializer. When LFMODE = 0, the pin based configuration defaults
to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can
select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the
pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to
35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 6.
7.3.18.1.1 Sample BIST Sequence
See Figure 13 for the BIST mode flow diagram.
20
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Step 1: For the DS90UB925Q-Q1 and DS90UB926Q-Q1 FPD-Link III chipset, BIST Mode is enabled via the
BISTEN pin of DS90UB926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTC
pin.
Step 2: The DS90UB925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero
pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and
BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low
for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to
determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST
is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 14 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
reducing signal condition enhancements ( Rx Equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal Mode check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 13. Bist Mode Flow Diagram
7.3.18.2 Forward Channel And Back Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero
pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to
the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with allzeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The
deserializer then outputs a SSO pattern on the RGB output pins.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as
indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The
register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the
functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in
BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.
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DES Outputs
BISTEN
(DES)
Case 1 - Pass
PCLK
(RFB = L)
ROUT[23:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
Case 2 - Fail
X = bit error(s)
DATA
(internal)
SSO
BIST
Result
Held
BIST Test
BIST Duration
Normal
Figure 14. Bist Waveforms
7.4 Device Functional Modes
7.4.1 Configuration Select (MODE_SEL)
Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pullup resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL
input (VR4) and VDD33 to select one of the other 10 possible selected modes. See Figure 15 and Table 4.
VDD33
R3
VR4
MODE_SEL
R4
SER
Figure 15. MODE_SEL Connection Diagram
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Device Functional Modes (continued)
Table 4. Configuration Select (MODE_SEL)
#
IDEAL
RATIO
VR4/VDD33
IdeAl VR4
(V)
SUGGESTED
RESISTOR R3
kΩ (1% tol)
SUGGESTED
RESISTOR R4
kΩ (1% tol)
LFMODE
REPEATER
BACKWARD
COMPATIBL
E
I2S Channel
B
(18–bit
Mode)
L
1
0
0
Open
40.2 or Any
L
L
L
2
0.164
0.541
255
49.9
L
H
L
L
3
0.221
0.729
243
69.8
L
H
L
H
4
0.285
0.941
237
95.3
H
L
L
L
5
0.359
1.185
196
110
H
L
L
H
6
0.453
1.495
169
140
H
H
L
L
7
0.539
1.779
137
158
H
H
L
H
8
0.728
2.402
90.9
243
H
L
H*
L
LFMODE:
L = frequency range is 15 – 85 MHz (Default)
H = frequency range is 5 – <15 MHz
Repeater:
L = Repeater OFF (Default)
H = Repeater ON
Backward Compatible:
L = Backward Compatible is OFF (Default)
H = Backward Compatible is ON; DES = DS90UR906Q or DS90UR916Q or DS90UR908Q
– frequency range = 15 - 65 MHz when LFMODE = 0
– frequency range = 5 - <15 MHz when LFMODE = 1
I2S Channel B:
L = I2S Channel B is OFF, Normal 24-bit RGB Mode (Default)
H = I2S Channel B is ON, 18-bit RGB Mode with I2S_DB Enabled. Note: use of GPIO(s) on unused inputs must be enabled by register.
7.4.2 Repeater Application
The DS90UB925Q-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links
to multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all
receivers in the system.
7.4.2.1 Repeater Configuration
In the repeater application, in this document, the DS90UB925Q-Q1 is referred to as the Transmitter or transmit
port (TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). Figure 16 shows the maximum
configuration supported for Repeater implementations using the DS90UB925Q-Q1 (TX) and DS90UB926Q-Q1
(RX). Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver.
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1:3 Repeater
1:3 Repeater
TX
Source
TX
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
RX
RX
TX
TX
1:3 Repeater
RX
1:3 Repeater
RX
Figure 16. Maximum Repeater Application
In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C
communications upstream or downstream to any I2C device within the system. This includes a mechanism for
assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.
At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel
RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video
blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between
receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the
Receiver and is received by the Transmitter.
Figure 17 provides more detailed block diagram of a 1:2 repeater configuration.
DS90UB925Q-Q1
Transmitter
I2C
Master
upstream
Transmitter
I2C
downstream
Receiver
or
Repeater
I2C
Slave
Parallel
LVCMOS
DS90UB926Q-Q1
Receiver
I2S Audio
DS90UB925Q-Q1
Transmitter
downstream
Receiver
or
Repeater
I2C
Slave
FPD-Link III interfaces
Figure 17. 1:2 Repeater Configuration
24
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7.4.2.2 Repeater Connections
The Repeater requires the following connections between the Receiver and each Transmitter Figure 18.
1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7 kΩ resistors.
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin – Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB925Q-Q1 INTB pin. The signal must be
pulled up to VDDIO.
DS90UB926Q-Q1
DS90UB925Q-Q1
RGB[7:0) / ROUT[23:0]
VDD33
DIN[23:0] / RGB[7:0]
DE
DE
VS
VS
HS
HS
I2S_CLK
I2S_CLK
I2S_WC
I2S_WC
I2S_DA
I2S_DA
Optional
MODE_SEL
VDD33
MODE_SEL
VDDIO
INTB_IN
Optional
INTB
VDD33
VDD33
ID[x]
VDD33
SDA
SDA
SCL
SCL
ID[x]
Figure 18. Repeater Connection Diagram
7.5 Programming
The DS90UB925Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. Multiple
serializer devices may share the serial control bus since 9 device addresses are supported. Device address is
set via R1 and R2 values on IDx pin. See Figure 19.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pull-up resistor to VDD33. For most applications a 4.7 k pull-up resistor to VDD33 may be used. The resistor value
may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven
Low.
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Programming (continued)
VDD33
R1
VDD33
VR2
HOST
or
Salve SCL
4.7k
4.7k
IDx
R2
SER
or
SCL DES
SDA
SDA
To other
Devices
Figure 19. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 9 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to
select one of the other 9 possible addresses. See Table 5.
Table 5. Serial Control Bus Addresses for IDx
#
IDEAL RATIO
VR2 / VDD33
IDEAL VR2
(V)
SUGGESTED
RESISTOR
R1 kΩ (1% tol)
SUGGESTED
RESISTOR
R2 kΩ (1% tol)
ADDRESS 7'b
ADDRESS 8'b
APPENDED
1
0
0
Open
40.2 or Any
0x0C
0x18
2
0.121
0.399
294
40.2
0x0D
0x1A
3
0.152
0.502
280
49.9
0x0E
0x1C
4
0.180
0.594
137
30.1
0x0F
0x1E
5
0.208
0.685
118
30.9
0x10
0x20
6
0.303
0.999
115
49.9
0x13
0x26
7
0.345
1.137
102
53.6
0x14
0x28
8
0.389
1.284
115
73.2
0x15
0x2A
9
0.727
2.399
90.9
243
0x1B
0x36
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 20.
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 20. Start and Stop Conditions
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To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 21 and a WRITE is shown in Figure 22.
If the Serial Bus is not required, the three pins may be left open (NC).
Register Address
Slave Address
S
A
2
A
1
A
0
0
Slave Address
a
c
k
a
c
k
A
2
S
A
1
A
0
Data
1
a
c
k
a
c
k
P
Figure 21. Serial Control Bus — Read
Register Address
Slave Address
A
2
S
A
1
A
0
0
Data
a
c
k
a
c
k
a
c
k
P
Figure 22. Serial Control Bus — Write
7.6 Register Maps
Table 6. Serial Control Bus Registers
ADD
(dec)
ADD
(hex)
REGISTER
NAME
0
0x00
I2C Device ID
1
0x01
Reset
BIT(S)
REGIST
ER
TYPE
7:1
RW
Device ID
7–bit address of Serializer
0
RW
ID Setting
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
7
RW
Remote
Auto Power
Down
Remote Auto Power Down
1: Power down when no Bidirectional Control Channel
link is detected
0: Do not power down when no Bidirectional Control
Channel link is detected
DEFAULT
(hex)
0x00
FUNCTION
6:2
DESCRIPTION
Reserved
1
RW
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
0
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
REGISTER
NAME
3
0x03
Configuration
[0]
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7
RW
0xD2
FUNCTION
Back
channel
CRC
Checker
Enable
6
Back Channel Check Enable
1: Enable
0: Disable
Reserved
5
RW
I2C Remote
Write Auto
Acknowledg
e
Automatically Acknowledge I2C Remote Write When
enabled, I2C writes to the Deserializer (or any remote
I2C Slave, if I2C PASS ALL is enabled) are
immediately acknowledged without waiting for the
Deserializer to acknowledge the write. This allows
higher throughput on the I2C bus
1: Enable
0: Disable
4
RW
Filter
Enable
HS, VS, DE two clock filter When enabled, pulses less
than two full PCLK cycles on the DE, HS, and VS
inputs will be rejected
1: Filtering enable
0: Filtering disable
3
RW
I2C Passthrough
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
2
28
DESCRIPTION
Reserved
1
RW
PCLK Auto
Switch over to internal OSC in the absence of PCLK
1: Enable auto-switch
0: Disable auto-switch
0
RW
TRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling
Clock Edge.
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
REGISTER
NAME
4
0x04
Configuration
[1]
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7
RW
0x80
FUNCTION
Failsafe
State
6
5
0x05
I2C Control
Input Failsafe State
1: Failsafe to Low
0: Failsafe to High
Reserved
RW
4
5
DESCRIPTION
CRC Error
Reset
Clear back channel CRC Error Counters
This bit is NOT self-clearing
1: Clear Counters
0: Normal Operation
RGB
DE Gate
1: Gate RGB data with DE in Backward Compatibility
mode and with Non-HDCP Deserializer
0: Pass RGB data independent of DE in Backward
Compatibility mode and Non-HDCP operation (default)
3
RW
Backward
Compatible
select by
pin or
register
control
Backward Compatible (BC) mode set by MODE_SEL
pin or register
1: BC is set by register bit. Use register bit reg_0x04[2]
to set BC Mode
0: BC is set by MODE_SEL pin.
2
RW
Backward
Compatible
Mode
Select
Backward compatible (BC) mode to DS90UR906Q or
DS90UR908Q, if reg_0x04[3] = 1
1: Backward compatible with DS90UR906Q or
DS90UR908Q
0: Backward Compatible is OFF (default)
1
RW
LFMODE
select by
pin or
register
control
Frequency range is set by MODE_SEL pin or register
1: Frequency range is set by register. Use register bit
reg_0x04[0] to set LFMODE
0: Frequency range is set by MODE_SEL pin.
0
RW
LFMODE
Frequency range select
1: PCLK range = 5MHz - <15 MHz), if reg_0x04[1] = 1
0: PCLK range = 15MHz - 85MHz (default)
7:5
0x00
Reserved
4:3
RW
SDA Output SDA output delay
Delay
Configures output delay on the SDA output. Setting this
value will increase output delay in units of 40ns.
Nominal output delay values for SCL to SDA are
00: 240ns
01: 280ns
10: 320ns
11: 360ns
2
RW
Local Write
Disable
Disable remote writes to local registers
Setting the bit to a 1 prevents remote writes to local
device registers from across the control channel. It
prevents writes to the Serializer registers from an I2C
master attached to the Deserializer.
Setting this bit does not affect remote access to I2C
slaves at the Serializer
1
RW
I2C Bus
Timer
Speedup
Speed up I2C bus watchdog timer
1: Watchdog timer expires after ~50 ms.
0: Watchdog Timer expires after ~1 s
0
RW
I2C Bus
timer
Disable
Disable I2C bus watchdog timer
When the I2C watchdog timer may be used to detect
when the I2C bus is free or hung up following an invalid
termination of a transaction.
If SDA is high and no signalling occurs for ~1 s, the I2C
bus assumes to be free. If SDA is low and no signaling
occurs, the device attempts to clear the bus by driving
9 clocks on SCL
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
6
0x06
REGISTER
NAME
DES ID
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7:1
RW
0x00
0
RW
RW
FUNCTION
DES Device 7-bit Deserializer Device ID
ID
Configures the I2C Slave ID of the remote Deserializer.
A value of 0 in this field disables I2C access to the
remote Deserializer. This field is automatically
configured by the Bidirectional Control Channel once
RX Lock has been detected. Software may overwrite
this value, but should also assert the FREEZE DEVICE
ID bit to prevent overwriting by the Bidirectional Control
Channel.
Device ID
Frozen
Freeze Deserializer Device ID
Prevents autoloading of the Deserializer Device ID by
the Bidirectional Control Channel. The ID will be frozen
at the value written.
0x00
Slave
Device ID
7-bit Remote Slave Device ID
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Deserializer. If an
I2C transaction is addressed to the Slave Device Alias
ID, the transaction will be remapped to this address
before passing the transaction across the Bidirectional
Control Channel to the Deserializer
RW
0x00
Slave
Device
Alias ID
7
0x07
Slave ID
7:1
8
0x08
Slave Alias
7:1
10
0x0A
CRC Errors
7:0
R
0x00
CRC Error
LSB
Number of back channel CRC errors – 8 least
significant bits
11
0x0B
7:0
R
0x00
CRC Error
MSB
Number of back channel CRC errors – 8 most
significant bits
12
0x0C
0
Reserved
0
30
DESCRIPTION
General Status
7-bit Remote Slave Device Alias ID
Assigns an Alias ID to an I2C Slave device attached to
the remote Deserializer. The transaction will be
remapped to the address specified in the Slave ID
register. A value of 0 in this field disables access to the
remote I2C Slave.
Reserved
7:4
0x00
Reserved
3
R
BIST CRC
Error
Back channel CRC error during BIST communication
with Deserializer.
The bit is cleared upon loss of link, restart of BIST, or
assertion of CRC ERROR RESET in register 0x04.
2
R
PCLK
Detect
PCLK Status
1: Valid PCLK detected
0: Valid PCLK not detected
1
R
DES Error
Back channel CRC error during communication with
Deserializer.
The bit is cleared upon loss of link or assertion of CRC
ERROR RESET in register 0x04.
0
R
LINK Detect LINK Status
1: Cable link detected
0: Cable link not detected (Fault Condition)
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
REGISTER
NAME
13
0x0D
Revision ID and
GPIO0
Configuration
14
0x0E
GPIO2 and
GPIO1
Configurations
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7:4
R
0xA0
3
FUNCTION
DESCRIPTION
Rev-ID
Revision ID: 1010
Production Device
RW
GPIO0
Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO
function is enabled, the local GPIO direction is Output,
and remote GPIO control is disabled.
2
RW
GPIO0
Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The
GPIO pin will be an output, and the value is received
from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RW
GPIO0
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO0
Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
7
RW
GPIO2
Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO
function is enabled, the local GPIO direction is Output,
and remote GPIO control is disabled.
6
RW
GPIO2
Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The
GPIO pin will be an output, and the value is received
from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
5
RW
GPIO2
Direction
Local GPIO Direction
1: Input
0: Output
4
RW
GPIO2
Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
3
RW
GPIO1
Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO
function is enabled, the local GPIO direction is Output,
and remote GPIO control is disabled.
2
RW
GPIO1
Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The
GPIO pin will be an output, and the value is received
from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RW
GPIO1
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO1
Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
0x00
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
REGISTER
NAME
15
0x0F
GPO_REG4
and GPIO3
Configurations
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7
RW
0x00
FUNCTION
GPO_REG
4 Output
Value
6:5
16
0x10
GPO_REG6
and
GPO_REG5
Configurations
Local GPO_REG4 output value
This value is output on the GPO pin when the GPO
function is enabled.
(The local GPO direction is Output, and remote GPO
control is disabled)
Reserved
4
RW
GPO_REG
4 Enable
GPO_REG4 function enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPIO3
Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO
function is enabled, the local GPIO direction is Output,
and remote GPIO control is disabled.
2
RW
GPIO3
Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The
GPIO pin will be an output, and the value is received
from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RW
GPIO3
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO3
Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
7
RW
GPO_REG
6 Output
Value
Local GPO_REG6 output value
This value is output on the GPO pin when the GPO
function is enabled.
(The local GPO direction is Output, and remote GPO
control is disabled)
0x00
6:5
Reserved
4
RW
GPO_REG
6 Enable
GPO_REG6 function enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPO_REG
5 Output
Value
Local GPO_REG5 output value
This value is output on the GPO pin when the GPO
function is enabled, the local GPO direction is Output,
and remote GPO control is disabled.
RW
GPO_REG
5 Enable
2:1
0
32
DESCRIPTION
Reserved
GPO_REG5 function enable
1: Enable GPO operation
0: Enable normal operation
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
REGISTER
NAME
17
0x11
GPO_REG8
and
GPO_REG7
Configurations
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7
RW
0x00
FUNCTION
GPO_REG
8 Output
Value
6:5
Reserved
RW
GPO_REG
8 Enable
GPO_REG8 function enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPO_REG
7 Output
Value
Local GPO_REG7 output value
This value is output on the GPO pin when the GPO
function is enabled, the local GPO direction is Output,
and remote GPO control is disabled.
RW
GPO_REG
7 Enable
0
19
0x12
0x13
Data Path
Control
Mode Status
Local GPO_REG8 output value
This value is output on the GPO pin when the GPO
function is enabled.
(The local GPO direction is Output, and remote GPO
control is disabled)
4
2:1
18
DESCRIPTION
Reserved
7:6
0x00
GPO_REG7 function enable
1: Enable GPO operation
0: Enable normal operation
Reserved
5
RW
DE Polarity
The bit indicates the polarity of the DE (Data Enable)
signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
4
RW
I2S
Repeater
Regen
I2S Repeater Regeneration
1: Repeater regenerate I2S from I2S pins
0: Repeater pass through I2S from video pins
3
RW
I2S
Channel B
Enable
Override
I2S Channel B Enable
1: Set I2S Channel B Enable from reg_12[0]
0: Set I2S Channel B Enable from MODE_SEL pin
2
RW
18-bit Video 18–bit video select
Select
1: Select 18-bit video mode
Note: use of GPIO(s) on unused inputs must be
enabled by register.
0: Select 24-bit video mode
1
RW
I2S
Transport
Select
I2S Transport Mode Slect
1: Enable I2S Data Forward Channel Frame Transport
0: Enable I2S Data Island Transport
0
RW
I2S
Channel B
Enable
I2S Channel B Enable
1: Enable I2S Channel B on B1 input
0: I2S Channel B disabled
7:5
0x10
Reserved
4
R
MODE_SEL MODE_SEL Status
1: MODE_SEL decode circuit is completed
0: MODE_SEL decode circuit is not completed
3
R
Low
Frequency
Mode
Low Frequency Mode Status
1: Low frequency (5 - <15 MHz)
0: Normal frequency (15 - 85 MHz)
2
R
Repeater
Mode
Repeater Mode Status
1: Repeater mode ON
0: Repeater Mode OFF
1
R
Backward
Compatible
Mode
Backward Compatible Mode Status
1: Backward compatible ON
0: Backward compatible OFF
0
R
I2S
Channel B
Mode
I2S Channel B Mode Status
1: I2S Channel B ON, 18-bit RGB mode with I2S_DB
enabled
0: I2S Channel B OFF; normal 24-bit RGB mode
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
REGISTER
NAME
20
0x14
Oscillator Clock
Source and
BIST Status
22
23
0x16
0x17
BCC Watchdog
Control
I2C Control
BIT(S)
REGIST
ER
TYPE
7:3
DEFAULT
(hex)
FUNCTION
0x00
2:1
RW
0
R
7:1
RW
0
RW
7
RW
0xFE
0x5E
Reserved
OSC Clock
Source
OSC Clock Source
(When LFMODE = 1, Oscillator = 12.5MHz ONLY)
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
BIST
Enable
Status
BIST status
1: Enabled
0: Disabled
Timer Value The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
programmed amount of time.
This field sets the Bidirectional Control Channel
Watchdog Timeout value in units of 2 ms.
This field should not be set to 0
Timer
Control
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
I2C Pass
All
I2C Control
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C Slave IDs that do not match the
Serializer I2C Slave ID.
0: Enable Forward Control Channel pass-through only
of I2C accesses to I2C Slave IDs matching either the
remote Deserializer Slave ID or the remote Slave ID.
6
34
DESCRIPTION
Reserved
5:4
RW
SDA Hold
Time
Internal SDA Hold Time
Configures the amount of internal hold time provided
for the SDA input relative to the SCL input. Units are 40
ns
3:0
RW
I2C Filter
Depth
Configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5
ns
24
0x18
SCL High Time
7:0
RW
0xA1
SCL HIGH
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL
output when the Serializer is the Master on the local
I2C bus. Units are 40 ns for the nominal oscillator clock
frequency. The default value is set to provide a
minimum 5us SCL high time with the internal oscillator
clock running at 32.5MHz rather than the nominal
25MHz.
25
0x19
SCL Low Time
7:0
RW
0xA5
SCL LOW
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL
output when the Serializer is the Master on the local
I2C bus. This value is also used as the SDA setup time
by the I2C Slave for providing data prior to releasing
SCL during accesses over the Bidirectional Control
Channel. Units are 40 ns for the nominal oscillator
clock frequency. The default value is set to provide a
minimum 5us SCL low time with the internal oscillator
clock running at 32.5MHz rather than the nominal
25MHz.
27
0x1B
BIST BC Error
7:0
R
0x00
BIST Back
Channel
CRC Error
Counter
BIST Mode Back Channel CRC Error Counter
This error counter is active only in the BIST mode. It
clears itself at the start of the BIST run.
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
100
0x64
REGISTER
NAME
Pattern
Generator
Control
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7:4
RW
0x10
FUNCTION
Pattern
Generator
Select
3:1
0
DESCRIPTION
Fixed Pattern Select
This field selects the pattern to output when in Fixed
Pattern Mode. Scaled patterns are evenly distributed
across the horizontal or vertical active regions. This
field is ignored when Auto-Scrolling Mode is enabled.
The following table shows the color selections in noninverted followed by inverted color mode
0000: Reserved
0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to
Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to
White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to
White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in
PGRS, PGGS, PGBS registers
1111: Reserved
Reserved
RW
Pattern
Generator
Enable
Pattern Generator Enable
1: Enable Pattern Generator
0: Disable Pattern Generator
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
REGISTER
NAME
101
0x65
Pattern
Generator
Configuration
BIT(S)
REGIST
ER
TYPE
7:5
DEFAULT
(hex)
FUNCTION
0x00
Reserved
4
RW
Pattern
Generator
18 Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled
patterns will have 64 levels of brightness and the R, G,
and B outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns
use 256 levels of brightness.
3
RW
Pattern
Generator
External
Clock
Select External Clock Source
1: Selects the external pixel clock when using internal
timing.
0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
2
RW
Pattern
Generator
Timing
Select
Timing Select Control
1: The Pattern Generator creates its own video timing
as configured in the Pattern Generator Total Frame
Size, Active Frame Size. Horizontal Sync Width,
Vertical Sync Width, Horizontal Back Porch, Vertical
Back Porch, and Sync Configuration registers.
0: the Pattern Generator uses external video timing
from the pixel clock, Data Enable, Horizontal Sync, and
Vertical Sync signals.
1
RW
Pattern
Generator
Color Invert
Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
0
RW
Pattern
Generator
Auto-Scroll
Enable
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the
next enabled pattern after the number of frames
specified in the Pattern Generator Frame Time (PGFT)
register.
0: The Pattern Generator retains the current pattern.
102
0x66
Pattern
Generator
Indirect Address
7:0
RW
0x00
Indirect
Address
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to
reading or writing the Pattern Generator Indirect Data
register.
See AN-2198 (SNLA132).
103
0x67
Pattern
Generator
Indirect Data
7:0
RW
0x00
Indirect
Data
When writing to indirect registers, this register contains
the data to be written. When reading from indirect
registers, this register contains the read back value.
See AN-2198 (SNLA132)
198
0xC6
ICR
7:6
5
Reserved
RW
IS_RX_INT
RW
INT Enable
R
IS RX INT
R
INT
4:1
0
199
0xC7
ISR
Global Interrupt Enable
Enables interrupt on the interrupt signal to the
controller.
Reserved
4:1
0
Interrupt on Receiver interrupt
Enables interrupt on indication from the Receiver.
Allows propagation of interrupts from downstream
devices
Reserved
7:6
5
36
DESCRIPTION
Interrupt on Receiver interrupt
Receiver has indicated an interrupt request from downstream device
Reserved
Global Interrupt
Set if any enabled interrupt is indicated
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Register Maps (continued)
Table 6. Serial Control Bus Registers (continued)
BIT(S)
REGIST
ER
TYPE
DEFAULT
(hex)
7:0
R
0x5F
ID0
First byte ID code, ‘_’
7:0
R
0x55
ID1
Second byte of ID code, ‘U’
0xF2
7:0
R
0x48
ID2
Third byte of ID code. Value will be ‘B’
243
0xF3
7:0
R
0x39
ID3
Forth byte of ID code: ‘9’
244
0xF4
7:0
R
0x32
ID4
Fifth byte of ID code: “2”
245
0xF5
7:0
R
0x35
ID5
Sixth byte of ID code: “5”
ADD
(dec)
ADD
(hex)
240
0xF0
241
0xF1
242
REGISTER
NAME
TX ID
FUNCTION
DESCRIPTION
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90UB925Q-Q1, in conjunction with the DS90UB926Q-Q1, is intended for interface between a host
(graphics processor) and a Display. It supports a 24-bit color depth (RGB888) and high definition (720p) digital
video format. It can receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three control
bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.
8.2 Typical Application
DS90UB925Q-Q1
3.3V/1.8V
VDD33
VDDIO
FB1
3.3V
C5
FB2
C4
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
CAPP12
C6
CAPL12
C7
C8
CAPHS12
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
LVCMOS
Parallel
Video
Interface
C9
C1
Serial
FPD-Link III
Interface
DOUT+
DOUTCMF
C2
C3
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
VDD33
R3
MODE_SEL
R4
PCLK
LVCMOS
Control
Interface
R5
ID[X]
SCL
SDA
INTB
PDB
C10
4.7k
R6
VDD33
4.7k
VDDIO VDD33*
HS
VS
DE
R1
R2
NC
I2S_CLK
I2S_WC
I2S_DA
RES
DAP (GND)
NOTE:
FB1-FB2: Impedance = 1 k: @ 100 MHz,
Low DC resistance (<1:)
C1-C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)
C4-C9 = 4.7 PF
C10 =>10 PF
R1 and R2 (see IDx Resistor Values Table 5)
R3 and R4 (see MODE_SEL Resistor Values Table 1)
R5 = 10 k:
R6 = 4.7 k:
* or VDDIO = 3.3V+0.3V
Figure 23. Typical Connection Diagram
38
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Typical Application (continued)
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Digital Display Interface
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
DOUT+
RIN+
DOUT-
RIN100: STP Cable
DS90UB925Q-Q1
Serializer
PDB
I2S AUDIO
(STEREO)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
3
MODE_SEL
INTB
SCL
SDA
IDx
PDB
OSS_SEL
OEN
MODE_SEL
DS90UB926Q-Q1
Deserializer
LOCK
PASS
3
I2S AUDIO
(STEREO)
MCLK
INTB_IN
SCL
SDA
IDx
DAP
RGB Display
720p
24-bit color depth
DAP
Figure 24. Typical Display System Diagram
720p
Megapixel
Image
Sensor
YUV Digital Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
D[0:n]
HS
VS
PCLK
VDD33
VDDIO
(3.3V) (1.8V or 3.3V)
0.1 PF
FPD-Link III
1 Pair/AC Coupled
0.1 PF
ROUT[0:n]
HS
VS
PCLK
RIN+
DOUT+
RIN-
DOUT-
Image
Processor
Unit
100: STP Cable
GPIO
DS90UB925Q-Q1
Serializer
MODE_SEL
INTB
PDB
SCL
SDA
IDx
PDB
OSS_SEL
OEN
MODE_SEL
INTB_IN
DS90UB926Q-Q1
Deserializer
SCL
SDA
IDx
DAP
GPIO
LOCK
PASS
DAP
Figure 25. Typical Camera Applications Diagram
8.2.1 Design Requirements
For the typical design application, use the following as input parameters.
Table 7. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDDIO
1.8 V or 3.3 V
VDD33
3.3 V
AC Coupling Capacitor for DOUT±
100 nF
PCLK Frequency
85 MHz
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8.2.2 Detailed Design Procedure
Figure 23 shows a typical application of the DS90UB925Q-Q1 serializer for an 85 MHz 24-bit Color Display
Application. The camera application has the same recommended connections. The CML outputs must have an
external 0.1 μF AC coupling capacitor on the high speed serial lines. The serializer has an internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2)
additional 1μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2)
VDDs (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is with 3.3V
LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail. A RC delay is placed on the PDB signal to
delay the enabling of the device until power is stable.
78 MHz TX Pixel Clock Input
(500 mV/DIV)
Magnitude (80 mV/DIV)
CML Serializer Data Throughput
(200 mV/DIV)
8.2.3 Application Curves
Time (100 ps/DIV)
Time (2.5 ns/DIV)
Figure 26. Serializer Eye Diagram with 78 MHz TX Pixel
Clock
40
Figure 27. Serializer CML Output with 78 MHz TX Pixel
Clock
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9 Power Supply Recommendations
9.1 Power Up Requirements and PDB Pin
The VDDs (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating
voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or VDD33, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.
This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate
power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal
description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.
In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
9.2 CML Interconnect Guidelines
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: www.ti.com/lvds.
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10 Layout
10.1 Layout Guidelines
Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML
lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohms
are typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
42
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DS90UB925Q-Q1
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SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
10.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
Figure 28. No Pullback WQFN, Single Row Reference Diagram
Table 8. No Pullback WQFN Stencil Aperture Summary
DEVICE
DS90UB925
Q-Q1
PIN
MKT Dwg PCB I/O
COUN
Pad Size
T
(mm)
48
SQA48A
PCB
PITCH
(mm)
PCB DAP
SIZE (mm)
STENCIL I/O
APERTURE
(mm)
STENCIL
DAP
Aperture
(mm)
NUMBER of
DAP
APERTURE
OPENINGS
GAP BETWEEN
DAP APERTURE
(Dim A mm)
0.5
5.1 x 5.1
0.25 x 0.7
1.1 x 1.1
16
0.2
0.25 x
0.6
Figure 29. 48-Pin WQFN Stencil Example of Via and Opening Placement
Figure 30 PCB layout example is derived from the layout design of the DS90UB925QSEVB Evaluation Board.
The graphic and layout description are used to determine both proper routing and proper solder techniques when
designing the Serializer board.
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43
DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
www.ti.com
Figure 30. DS90UB925Q-Q1 Serializer Example Layout
44
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DS90UB925Q-Q1
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SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
•
•
•
•
AN-2198 Exploring the Internal Test Pattern Generation SNLA132
AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines SNLA008
SCAN18245T Non-Inverting Transceiver with TRI-STATE Outputs SNLA035
TI Interface Website www.ti.com/lvds
AN-1187 Leadless Leadframe Package (LLP) SNOA401
Semiconductor and IC Package Thermal Metrics SPRA953
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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45
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UB925QSQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB925QSQ
DS90UB925QSQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB925QSQ
DS90UB925QSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB925QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Apr-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS90UB925QSQ/NOPB
WQFN
RHS
48
DS90UB925QSQE/NOPB
WQFN
RHS
DS90UB925QSQX/NOPB
WQFN
RHS
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Apr-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UB925QSQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS90UB925QSQE/NOPB
WQFN
RHS
48
250
213.0
191.0
55.0
DS90UB925QSQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
RHS0048A
SQA48A (Rev B)
www.ti.com
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