Sony CXD2428Q Video scan converter Datasheet

CXD2428Q
Video Scan Converter
Description
The CXD2428Q is an IC which generates control
signals and performs line interpolation calculations
for field memory (CXK1206AM/ATM) in order to
perform video signal scanning line conversion. In
addition, this IC performs the aspect conversion of
the ZOOM mode and WIDE-ZOOM mode in order to
support wide screens.
100 pin QFP (Plastic)
Features
• Video signal (NTSC/PAL) scanning line conversion function
• ZOOM function
(Function to cut top and bottom areas of 4:3 image and expand it to 16:9)
• WIDE-ZOOM function
(Function to vertically compress 4:3 image and expand it to 16:9)
• Operating frequency: 28.6MHz (typ.)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
VSS – 0.5 to +7.0
• Input voltage
VI
VSS – 0.5 to VDD +0.5
• Output voltage
VO
VSS – 0.5 to VDD +0.5
• Operating temperature
Topr
–20 to +75
• Storage temperature
Tstg
–55 to +150
Operating Conditions
Supply voltage
VDD
4.5 to 5.5
V
V
V
°C
°C
V
Applications
Liquid crystal projectors, etc.
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95442-ST
CXD2428Q
3 28 53 78
4 15 29 40 54 65 79 90
TST6
TST5
TST4
TST3
TST2
TST1
TST0
VSS7
VSS6
VSS5
VSS3
VSS4
VSS2
VSS1
VSS0
VDD3
VDD2
VDD0
VDD1
Block Diagram
6 11 14 17 18 19 51
CSD0 52
CSD1 55
12
FSL1
CSD2 56
13
FSL2
CSD3 57
93 ADCK
CSD4 58
94 ODEV
H-WRITE
CSD5 59
96 HIN
CSD6 60
98 CKI
CSD7 61
99 RYOE
CFD0 62
100 BYOE
CFD1 63
CFD2 64
21 HOUT
CFD3 66
22 HBLK
H-READ
CFD4 67
CFD5 68
45 RDCK
95 HRET
CFD6 69
89 HCR0
CFD7 70
YSD0 71
V-WRITE
91 VCR0
YSD1 72
92 WEN0
YSD2 73
97 VIN
INTERPOLATION
YSD3 74
10 VBLK
YSD4 75
20 VOUT
YSD5 76
46 REN1
YSD6 77
V-READ
47
VCR1
YSD7 80
48
HCR1
YFD0 81
49 INC1
YFD1 82
50 INC2
YFD2 83
YFD3 84
YFD4 85
COEFFICIENT
YFD5 86
SERIALINTERFACE
YFD6 87
YFD7 88
BLNK 16
1/2
–2–
YCK
RYCK
42 43 44
BYCK
YD0
YD1
YD2
YD3
YD4
YD5
YD6
33 34 35 36 37 38 39 41
YD7
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
23 24 25 26 27 30 31 32
1
SCLK
2
SCTR
5
SDAT
7
P0
8
P1
9
P2
CXD2428Q
Pin Description
Pin
No.
Symbol
I/O
Description
1
SCLK
I
Serial transfer clock
2
SCTR
I
Serial transfer control
3
VDD0
—
Power supply
4
VSS0
—
GND
5
SDAT
I
Serial transfer data
6
TST0
O
Leave open.
7
P0
I/O
I/O port
8
P1
I/O
I/O port
9
P2
I/O
I/O port
10
VBLK
O
Vertical blanking output
11
TST1
I
Fixed to high.
12
FSL1
I
Field identification selection (High: internal, Low: external)
13
FSL2
I
Field information polarity switching
14
TST2
I
Fixed to low.
15
VSS1
—
16
BLNK
I
Output data control (High: black display)
17
TST3
I
Fixed to high.
18
TST4
I
Leave open.
19
TST5
I
Leave open.
20
VOUT
O
Vertical sync signal output
21
HOUT
O
Horizontal sync signal output
22
HBLK
O
Horizontal blanking signal
23
CD7
O
B-Y/R-Y data output (MSB)
24
CD6
O
B-Y/R-Y data output
25
CD5
O
B-Y/R-Y data output
26
CD4
O
B-Y/R-Y data output
27
CD3
O
B-Y/R-Y data output
28
VDD1
—
Power supply
29
VSS2
—
GND
30
CD2
O
B-Y/R-Y data output
31
CD1
O
B-Y/R-Y data output
32
CD0
O
B-Y/R-Y data output (LSB)
33
YD7
O
Y data output (MSB)
34
YD6
O
Y data output
35
YD5
O
Y data output
36
YD4
O
Y data output
37
YD3
O
Y data output
GND
–3–
CXD2428Q
Pin
No.
Symbol
38
YD2
O
Y data output
39
YD1
O
Y data output
40
VSS3
—
GND
41
YD0
O
Y data output (LSB)
42
BYCK
O
DA converter (B-Y) clock output
43
RYCK
O
DA converter (R-Y) clock output
44
YCK
I
DA converter clock input
45
RDCK
I
Readout clock input
46
REN1
O
Readout memory enable
47
VCR1
O
Readout memory vertical clear
48
HCR1
O
Readout memory horizontal clear
49
INC1
O
Readout memory line increment
50
INC2
O
Readout memory line increment
51
TST6
I
Fixed to high.
52
CSD0
I
B-Y/R-Y lower line data input (LSB)
53
VDD2
—
Power supply
54
VSS4
—
GND
55
CSD1
I
B-Y/R-Y lower line data input
56
CSD2
I
B-Y/R-Y lower line data input
57
CSD3
I
B-Y/R-Y lower line data input
58
CSD4
I
B-Y/R-Y lower line data input
59
CSD5
I
B-Y/R-Y lower line data input
60
CSD6
I
B-Y/R-Y lower line data input
61
CSD7
I
B-Y/R-Y lower line data input (MSB)
62
CFD0
I
B-Y/R-Y upper line data input (LSB)
63
CFD1
I
B-Y/R-Y upper line data input
64
CFD2
I
B-Y/R-Y upper line data input
65
VSS5
—
66
CFD3
I
B-Y/R-Y upper line data input
67
CFD4
I
B-Y/R-Y upper line data input
68
CFD5
I
B-Y/R-Y upper line data input
69
CFD6
I
B-Y/R-Y upper line data input
70
CFD7
I
B-Y/R-Y upper line data input (MSB)
71
YSD0
I
Y lower line data input (LSB)
72
YSD1
I
Y lower line data input
73
YSD2
I
Y lower line data input
74
YSD3
I
Y lower line data input
I/O
Description
GND
–4–
CXD2428Q
Pin
No.
Symbol
75
YSD4
I
Y lower line data input
76
YSD5
I
Y lower line data input
77
YSD6
I
Y lower line data input
78
VDD3
—
Power supply
79
VSS6
—
GND
80
YSD7
I
Y lower line data input (MSB)
81
YFD0
I
Y upper line data input (LSB)
82
YFD1
I
Y upper line data input
83
YFD2
I
Y upper line data input
84
YFD3
I
Y upper line data input
85
YFD4
I
Y upper line data input
86
YFD5
I
Y upper line data input
87
YFD6
I
Y upper line data input
88
YFD7
I
Y upper line data input (MSB)
89
HCR0
O
Write memory horizontal clear
90
VSS7
—
GND
91
VCR0
O
Write memory vertical clear
92
WEN0
O
Write memory enable
93
ADCK
O
AD converter clock
94
ODEV
I
Field information input
95
HRET
O
Phase comparison output
96
HIN
I
Horizontal sync signal input
97
VIN
I
Vertical sync signal input
98
CKI
I
Write clock input
99
RYOE
O
AD converter (R-Y) enable
100
BYOE
O
AD converter (B-Y) enable
I/O
Description
–5–
CXD2428Q
Electrical Characteristics
DC Characteristic
Item
Input, output voltage
Input voltage 1
Input voltage 2
Output voltage 1
Output voltage 2
Output voltage 3
Input leak current
Output leak current
(VDD = 5.0V ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
Symbol
VI, VO
Min.
Typ.
Vss
VIH
V
0.2VDD
IOH = –2mA
VDD – 0.8
IOL = 4mA
IOH = –4mA
0.4
VDD – 0.8
IOL = 8mA
VOH1
VDD
0.8VDD
VIL
VOH1
Unit
0.3VDD
VIH
VOH1
Max.
0.7VDD
VIL
IOH = –6mA
0.4
VDD – 0.8
Applicable pin
V
∗1
V
∗2
V
∗3
V
∗4
V
IOL = 12mA
∗5
0.4
µA
10
µA
∗6
ILI1
VIN = VSS or VDD
–10
ILI2
VIN = VSS
–40
–100
–240
µA
∗7
ILI3
VIN = VDD
40
100
240
µA
∗8
ILI4
VIN = VSS or VDD
–40
40
µA
∗9
ILZ
VIN = VSS or VDD
–40
40
µA
∗10
Current consumption IDD
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
∗9
∗10
Conditions
VDD = 5.0V
70
All input pins other than ∗2
Pins 1, 2, 5, 96 and 97
All output pins other than ∗4 and ∗5
Pins 10, 22, 42, 43, 46 to 50, 89, 91, 92 and 93
Pins 20 and 21
All input pins other than ∗7, ∗8 and ∗9
Pins 11, 12, 19 and 51
Pins 13, 14, 16, 17 and 18
Pins 7, 8 and 9
Pin 6
–6–
mA
CXD2428Q
I/O Pin Capacitance
Item
(VDD = VI = 0V, f = 1MHz)
Symbol
Min.
Typ.
Max.
Unit
Input pin capacitance
CIN
9
pF
Output pin capacitance
COUT
11
pF
Input/output pin capacitance
CI/O
11
pF
Serial Block AC Characteristics
tw1
SCLK
tw1
ts1
th1
SDAT
ts0
th0
SCTL
(VDD = 5.0V ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
Symbol
Item
Min.
Max.
ts1
Setup time of SDAT in relation to the rise of SCLK
100ns
th1
Hold time of SDAT in relation to the rise of SCLK
100ns
tw1
SCLK pulse width
100ns
ts0
Setup time of SCTL in relation to the rise of SCLK
100ns
2tw1
th0
Hold time of SCTL in relation to the rise of SCLK
100ns
2tw1
–7–
CXD2428Q
AC Characteristics
CKI
RDCK
tpd max
tpd min
Output
invalid
Input
ts2
th2
(VDD = 5.0V ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
1) Output block
Item
tpd min
tpd max
Delay of ADCK in relation to CKI
3ns
28ns
Delay of HCR0, VCR0 and WEN0 in relation to CKI
10ns
70ns
Delay of REN1, VCR1, HCR1, INC1 and INC2 in relation to RDCK
6ns
32ns
Delay of HOUT in relation to RDCK
5ns
30ns
Delay of VOUT in relation to RDCK
7ns
45ns
Delay of RYCK and BYCK in relation to YCK
1ns
22ns
Delay of YD0 to YD7 and CD0 to CD7 in relation to RDCK
5ns
38ns
Delay of HRET in relation to CKI
5ns
32ns
Delay of BYOE and RYOE in relation to CKI
2ns
25ns
ts2
th2
Setup and hold time of CSD0 to CSD7, CFD0 to CFD7, YSD0 to
YSD7 and YFD0 to YFD7 in relation to RDCK
9ns
3ns
Setup and hold time of HIN in relation to CKI
3ns
3ns
Setup and hold time of VIN in relation to CKI
0ns
20ns
Setup and hold time of YCK in relation to CKI
20ns
2ns
2) Input block
Item
–8–
Condition
Load 25pF
Load 20pF
CXD2428Q
Description of Operation
1. CXD2428Q Control System
The operation timing of this IC is controlled by serial data.
An 8-bit address and 8-bit data are sequentially transferred from the falling edge of SCTL, and each control
data is taken in at the rising edge of SCLK up to the rising edge of SCTL.
SCLK
SCTL
SDAT
ADDRESS
DATA
Serial transfer timing
2. Control Mode
The following timing and modes are changed by control data:
Variable
H SHIFT
V SHIFT
H PHASE
V PHASE
H SZ RD
H SZ WR
LN DAT0 to 7
MD DAT0 to 7
TOP BLK
BTM BLK
LFT BLK
RGT BLK
IODAT
IOSL
TEST
Address
00H
10H
20H
30H
40H
50H
41H
51H
60 to 67H
70 to 77H
A0H
B0H
C0H
D0H
80H
E0H
90H
Function
Horizontal write start timing
Vertical write start timing
Horizontal readout start timing
Vertical readout start timing
Number of readout line dots (0 to 7 bits)
Number of readout line dots (8 to 10 bits)
Number of write line dots (0 to 7 bits)
Number of write line dots (8 to 10 bits)
Conversion mode address
Conversion mode data
Vertical blanking rise timing
Vertical blanking fall timing
Horizontal blanking rise timing
Horizontal blanking fall timing
I/O port output data∗1
OUT port select∗2
∗3
∗1 Transfer xxxx.1xxx (binary) for PAL (4:3 display) and xxxx.0xxx (binary) for the other systems.
∗2 Transfer 00 (hexadecimal).
∗3 Transfer 00 (hexadecimal).
–9–
CXD2428Q
3. Scanning Line Conversion Function
LN DAT (address 6x) and MD DAT (address 7x) are data which indicate scanning line conversion coefficients.
There are the following 8 conversion coefficients:
1.67/1.75/2/2.22/2.33/2.67/2.8 = K
K=
number of scanning lines of output signal
number of scanning lines of input signal
The conversion coefficient equals the ratio of one scanning line to scan lines generated by interpolation. The
coefficient can be changed on the screen.
In the WIDE-ZOOM mode, compression and expansion on the screen can be changed by combining these 8
coefficients as desired.
Compression and expansion are carried out by setting the coefficient and the number of switching lines.
The upper 6 MD DAT bits (bits 3 to 8) provide coefficient data.
The lower 2 MD DAT bits (bits 1 and 2) and 8 LN DAT bits provide line number data.
The coefficients and corresponding MD DAT are shown below.
Coefficient
1.67
MD DAT
MSB
LSB
000100xx
1.75
001000xx
2.0
000001xx
000000xx ∗
2.1
010000xx
2.22
011100xx
2.33
101000xx
2.67
110000xx
2.8
110110xx
∗ The interpolation coefficient 2.0 has two modes which are determined by the value of bit 3.
When bit 3 is 1, an interpolation line is generated by outputting the same signal as that of the
preceding line. This mode realizes images with a higher vertical resolution.
When bit 3 is 0, an interpolation line is output by averaging signals of the preceding and following
lines. This mode realizes images with smoother diagonal lines.
4. DA Converter Clock
RYCK and BYCK, which are YCK halved and phase inverted, are output as D/A converter clocks.
5. Output Control
A black signal is output when BLNK is high.
– 10 –
CXD2428Q
Mode Setting and Operation
1. Horizontal Write
CKI is input after phase comparison with HSYNC input.
PLL frequency division value is set by H SZ WR (standard 38C (hexadecimal)), and HRET is output.
Write start timing is set by H SHIFT.
An ADCK pulse, which is CKI halved, is output.
The enable pulses RYOE and BYOE for R-Y and B-Y A/D converter are output.
HIN
HRET
H SZ WR + 2ck
HWEN
(Internal pulse)
(H SHIFT + 1) × 2ck
HCR0
RYOE
BYOE
CKI
ADCK
RYOE
BYOE
– 11 –
CXD2428Q
2. Horizontal Readout
In this IC, the readout and write clocks are asynchronous.
The readout 1H sample coefficient is set by H SZ RD.
An HOUT pulse with a pulse width of 68ck is output from horizontal readout reference pulse HRSP (internal
pulse).
Readout start timing is set by H PHASE.
The HBLK pulse set by LFT BLK and RGT BLK is output. However, this pulse does not stop readout, so it has
no relation to the actual blanking interval.
HRSP
H SZ RD + 2ck
HOUT
68ck
HREN
(Internal pulse)
H PHASE + 2ck
HBLK
RGT BLKck
LFT BLK + 2ck
HCR1
– 12 –
CXD2428Q
3. Vertical Write
Write start timing is set by V SHIFT.
The CXK1206AM/ATM write control pulses VCR0, HCR0 and WEN0 are output.
HIN
VIN
VSP
(Internal pulse)
V SHIFT + 1H
VWEN
(Internal pulse)
VCR0
HCR0
WEN0
– 13 –
CXD2428Q
4. Vertical Readout
The VBLK pulse set by TOP BLK and BTM BLK is output. However, this pulse does not stop readout, so it
has no relation to the actual blanking interval.
Readout start timing is set by V PHASE.
The CXK1206AM/ATM readout control pulses VCR1, HCR1, REN1, INC1 and INC2 are output.
The VSP pulse (internal pulse) corresponding to V SHIFT is the vertical readout reference pulse.
A VOUT pulse with a pulse width of 6H∗ (∗ indicates double scan H) is output.
HOUT
VSP
(Internal pulse)
VOUT
VREN
(Internal pulse)
6H∗
Note 1)
Note 1) PAL (4:3): 65H∗, Others: 0H∗
V PHASE + 1H∗
TOP BLK + 1H∗
VBLK
320 + BTM BLKH∗
VCR1
HCR1
REN1
Note 2) INC1 and INC2 timing varies with modes.
INC1
INC2
– 14 –
CXD2428Q
Application Circuit
CAD
YAD
+5V
+5V
0.1µ
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Y07
Y06
Y05
Y04
HCR1
INC2
VCR1
REN1
Y97
Y96
Y95
Y94
0.1µ
VSS
VDD
NC
NC
APM
CKW0
PW
HCLR0
DIN3
INC0
DIN2
VCLR0
DIN1
WE
DIN0
HCLR1
HCLR2
INC1
INC2
VCLR1
VCLR2
OE1
OE2
DO13
DON23
DO12
DO22
DO11
DO21
DO10
DO20
CKR1
CKR2
TSM
TR2
TR1
VSS
TR0
CXK1206
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C07
C06
C05
C04
HCR0
VCR0
WEN0
HCR1
INC1
VCR1
REN1
HCR1
INC2
VCR1
REN1
Y87
Y86
Y85
Y84
10k × 4
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
C97
C96
C95
C94
10k × 4
VSS
VDD
NC
NC
APM
CKW0
PW
HCLR0
DIN3
INC0
DIN2
VCLR0
DIN1
WE
DIN0
HCLR1
HCLR2
INC1
INC2
VCLR1
VCLR2
OE1
OE2
DO13
DON23
DO12
DO22
DO11
DO21
DO10
DO20
CKR1
CKR2
TSM
TR2
TR1
VSS
TR0
CXK1206
10k × 4
0.1µ
VSS
VDD
NC
NC
APM
CKW0
PW
HCLR0
DIN3
INC0
DIN2
VCLR0
DIN1
WE
DIN0
HCLR1
HCLR2
INC1
INC2
VCLR1
VCLR2
OE1
OE2
DO13
DON23
DO12
DO22
DO11
DO21
DO10
DO20
CKR1
CKR2
TSM
TR2
TR1
VSS
TR0
CXK1206
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C03
C02
C01
C00
HCR0
VCR0
WEN0
HCR1
INC1
VCR1
REN1
HCR1
INC2
VCR1
REN1
Y83
Y82
Y81
Y80
C93
C92
C91
C90
10k × 4
VSS
VDD
NC
NC
APM
CKW0
PW
HCLR0
DIN3
INC0
DIN2
VCLR0
DIN1
WE
DIN0
HCLR1
HCLR2
INC1
INC2
VCLR1
VCLR2
OE1
OE2
DO13
DON23
DO12
DO22
DO11
DO21
DO10
DO20
CKR1
CKR2
TSM
TR2
TR1
VSS
TR0
CXK1206
10k × 4
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HCR0
VCR0
WEN0
HCR1
INC1
VCR1
REN1
C83
C82
C81
C80
10k × 4
C90
C97
C96
C95
C94
C93
C92
C91
C87
C86
C85
C84
C83
Y97
10k × 4
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
C82
C81
C80
Y93
Y92
Y91
Y90
C87
C86
C85
C84
Y96
Y95
Y94
Y93
Y92
Y91
Y90
HCR1
INC2
VCR1
REN1
HCR1
INC1
VCR1
REN1
+5V
0.1µ
Y03
Y02
Y01
Y00
HCR0
VCR0
WEN0
10k × 4
+5V
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+5V
10µ
16V
0.1µ
VCR0
WEN0
HD
VD
CKI
YFD0
YFD1
YFD2
YFD3
YFD4
YFD5
YFD6
YFD7
HCR0
VSS7
VCR0
WEN0
ADCK
ODEV
HRET
HIN
VIN
CKI
RYOE
BYOE
CXD2428Q
SCLK
SCTR
VDD0
VSS0
SDAT
TST0
P0
P1
P2
VBLK
TST1
FSL1
FSL2
TST2
VSS1
BLNK
TST3
TST4
TST5
VOUT
HOUT
HBLK
CD7
CD6
CD5
CD4
CD3
VDD1
VSS2
CD2
HCR0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
YSD7
VSS6
VDD3
YSD6
YSD5
YSD4
YSD3
YSD2
YSD1
YSD0
CFD7
CFD6
CFD5
CFD4
CFD3
VSS5
CFD2
CFD1
CFD0
CSD7
CSD6
CSD5
CSD4
CSD3
CSD2
CSD1
VSS4
VDD2
CSD0
TST6
80 7978 7776 7574 7372 7170 6968 6766 6564 6362 6160 5958 5756 5554 5352 51
Y80
Y81
Y82
Y83
Y84
Y85
Y86
Y87
INC2
INC1
HCR1
VCR1
REN1
RDCK
YCK
RYCK
BYCK
YD0
VSS3
YD1
YD2
YD3
YD4
YD5
YD6
YD7
CD0
CD1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
INC2
INC1
HCR1
VCR1
REN1
28.6MHz
YDA0
YCLK
R-YCLK
B-YCLK
YDA1
YDA2
YDA3
YDA4
YDA5
YDA6
YDA7
1 2 3 4 5 6 7 8 9 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 30
10µ
16V
+5V
CDA2
CDA1
CDA0
CDA7
CDA6
CDA5
CDA4
CDA3
SIO
0.1µ
SCLK
SCTR
SDAT
YDA
CDA
HRCK
HOUT
VOUT
VBLK
B-YOE
R-YOE
HRET
ADCK
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 15 –
CXD2428Q
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
– 16 –