CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations – see “Available Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps — Device-device skew less than 500 ps • 10-MHz to 133-MHz operating range • Low jitter, less than 200 ps cycle-cycle • Space-saving 8-pin 150-mil SOIC package • 3.3V operation • Industrial temperature available Functional Description The CY2304 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 µA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations, as shown in the “Available Configurations” table. The CY2304–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY2304–2 allows the user to obtain Ref and 1/2x or 2x frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. Pin Configuration Logic Block Diagram FBK 8-pin SOIC Top View CLKA1 PLL REF CLKA2 /2 REF CLKA1 CLKA2 GND 1 2 3 4 8 7 6 5 FBK VDD CLKB2 CLKB1 Extra Divider (-2) CLKB1 CLKB2 Available Configurations Device FBK from CY2304-1 Bank A or B Reference Reference CY2304-2 Bank A Reference Reference/2 CY2304-2 Bank B 2 × Reference Reference Cypress Semiconductor Corporation Document #: 38-07247 Rev. *C Bank A Frequency Bank B Frequency • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 7, 2002 CY2304 Pin Description Pin Signal Description 1 REF[1] Input reference frequency, 5V-tolerant input 2 CLKA1[2] Clock output, Bank A 3 CLKA2[2] Clock output, Bank A 4 GND Ground 5 CLKB1[2] Clock output, Bank B 6 CLKB2 [2] Clock output, Bank B 7 VDD 3.3V supply 8 FBK PLL feedback input Zero Delay and Skew Control REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application note “CY2308: Zero Delay Buffer.” For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. Document #: 38-07247 Rev. *C Page 2 of 8 CY2304 Maximum Ratings Supply Voltage to Ground Potential.................–0.5V to +7.0V Storage Temperature ..................................–65°C to +150°C DC Input Voltage (Except Ref) ...............–0.5V to VDD + 0.5V Junction Temperature ..................................................150°C DC Input Voltage REF.............................................–0.5 to 7V Static Discharge Voltage (per MIL-STD-883, Method 3015) .............................> 2000V Operating Conditions for CY2304SC-X Commercial Temperature Devices Parameter Description Min. Max. Unit 3.0 3.6 V VDD Supply Voltage TA Operating Temperature (Ambient Temperature) 70 °C CL Load Capacitance (below 100 MHz) 30 pF 0 Load Capacitance (from 100 MHz to 133 MHz) 15 pF CIN Input Capacitance[3] 7 pF tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 50 ms Max. Unit 0.05 Electrical Characteristics for CY2304SC-X Commercial Temperature Devices Parameter Description VIL Input LOW Voltage VIH Input HIGH Voltage Test Conditions Min. 0.8 V 2.0 V IIL Input LOW Current VIN = 0V 50.0 µA IIH Input HIGH Current VIN = VDD 100.0 µA VOL Output LOW Voltage[4] IOL = 8 mA (–1, –2) 0.4 V VOH Output HIGH Voltage[4] IOH = –8 mA (–1, –2) 2.4 V IDD (PD mode) Power-down Supply Current REF = 0 MHz 12.0 µA IDD Supply Current Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND 45.0 mA Unloaded outputs, 66-MHz REF (–1,–2) 32.0 mA Unloaded outputs, 33-MHz REF (–1,–2) 18.0 mA Switching Characteristics for CY2304SC-X Commercial Temperature Devices [5] Parameter Name Test Conditions Min. Typ. Max. Unit t1 Output Frequency 30-pF load, all devices 10 100 MHz t1 Output Frequency 15-pF load, –1, –2 devices 10 133.3 MHz Duty Cycle[4] = t2 ÷ t1 (–1,–2) Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40.0 50.0 60.0 % Duty Cycle[4] = t2 ÷ t1 (–1,–2) Measured at 1.4V, FOUT < 50.0 MHz 15-pF load 45.0 50.0 55.0 % t3 Rise Time[4] (–1, –2) Measured between 0.8V and 2.0V, 30-pF load 2.20 ns t3 Rise Time[4] (–1, –2) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns Notes: 3. Applies to both REF clock and FBK. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 5. All parameters are specified with loaded output. Document #: 38-07247 Rev. *C Page 3 of 8 CY2304 Switching Characteristics for CY2304SC-X Commercial Temperature Devices (continued)[5] Parameter Name Max. Unit Measured between 0.8V and 2.0V, 30-pF load 2.20 ns Measured between 0.8V and 2.0V, 15-pF load 1.50 ns Output-to-Output Skew All outputs equally loaded on same Bank (–1,–2)[4] 200 ps Output Bank A to Output All outputs equally loaded Bank B Skew (–1) 200 ps Output Bank A to Output All outputs equally loaded Bank B Skew (–2) 400 ps t4 [4] Fall Time (–1, –2) t4 Fall Time[4] (–1, –2) t5 Test Conditions Min. Typ. t6 Skew, REF Rising Edge Measured at VDD/2 to FBK Rising Edge[4] 0 ±250 ps t7 Device-to-Device Skew[4] Measured at VDD/2 on the FBK pins of devices 0 500 ps tJ Cycle-to-Cycle Jitter[4] (–1) Measured at 66.67 MHz, loaded outputs, 15-pF load 175 ps Measured at 66.67 MHz, loaded outputs, 30-pF load 200 ps Measured at 133.3 MHz, loaded outputs, 15 pF load 100 ps tJ Cycle-to-Cycle Jitter[4] (–2) Measured at 66.67 MHz, loaded outputs 30-pF load 400 ps Measured at 66.67 MHz, loaded outputs 15-pF load 375 ps tLOCK PLL Lock Time[4] Stable power supply, valid clocks presented on REF and FBK pins 1.0 ms Operating Conditions for CY2304SI-X Industrial Temperature Devices Parameter Description Min. Max. Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) -40 85 °C CL Load Capacitance (below 100 MHz) 30 pF Load Capacitance (from 100 MHz to 133 MHz) 15 pF Input Capacitance 7 pF CIN Switching Characteristics for CY2304SI-X Industrial Temperature Devices Parameter Name Test Conditions Min. [5] Typ. Max. Unit 100 MHz 133.3 MHz 60.0 % 55.0 % Measured between 0.8V and 2.0V, 30-pF load 2.50 ns Rise Time[4] (–1, –2) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns t4 Fall Time[4] (–1, –2) Measured between 0.8V and 2.0V, 30-pF load 2.50 ns t4 Fall Time[4] (–1, –2) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns t1 Output Frequency 30-pF load, All devices t1 Output Frequency 15-pF load, All devices Duty Cycle[4] = t2 ÷ t1 (–1,–2) Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40.0 50.0 Duty Cycle[4] = t2 ÷ t1 (–1,–2) Measured at 1.4V, FOUT < 50.0 MHz 15-pF load 45.0 50.0 t3 Rise Time[4] (–1, –2) t3 Document #: 38-07247 Rev. *C 10 10 Page 4 of 8 CY2304 Switching Characteristics for CY2304SI-X Industrial Temperature Devices (continued)[5] Parameter t5 Name Test Conditions Max. Unit All outputs equally loaded 200 ps Output Bank A to Output Bank All outputs equally loaded B Skew (–1) 200 ps Output Bank A to Output Bank All outputs equally loaded B Skew (–2) 400 ps Output-to-Output Skew on same Bank (–1,–2)[4] Min. Typ. t6 Skew, REF Rising Edge to FBK Rising Edge[4] Measured at VDD/2 0 ±250 ps t7 Device-to-Device Skew[4] Measured at VDD/2 on the FBK pins of devices 0 500 ps tJ Cycle-to-Cycle Jitter[4] (–1) Measured at 66.67 MHz, loaded outputs, 15-pF load 180 ps Measured at 66.67 MHz, loaded outputs, 30-pF load 200 ps Measured at 133.3 MHz, loaded outputs, 15 pF load 100 ps Measured at 66.67 MHz, loaded outputs, 30-pF load 400 ps Measured at 66.67 MHz, loaded outputs, 15-pF load 380 ps Stable power supply, valid clocks presented on REF and FBK pins 1.0 ms Cycle-to-Cycle Jitter[4] (–2) tJ tLOCK PLL Lock Time[4] Electrical Characteristics for CY2304SI-X Industrial Temperature Devices Parameter Description Max. Unit 0.8 V VIN = 0V 50.0 µA Input HIGH Current VIN = VDD 100.0 µA Output LOW Voltage[4] IOL = 8 mA (–1, –2) 0.4 V VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current IIH VOL Voltage[4] Test Conditions Min. 2.0 IOH = –8 mA (–1, –2) V VOH Output HIGH IDD (PD mode) Power-down Supply Current REF = 0 MHz 2.4 25.0 µA V IDD Supply Current Unloaded outputs, 100 MHz, Select inputs at VDD or GND 45.0 mA Unloaded outputs, 66-MHz REF (–1, –2) 35.0 mA Unloaded outputs, 33-MHz REF (–1, –2) 20.0 mA Switching Waveforms Duty Cycle Timing t1 t2 1.4V Document #: 38-07247 Rev. *C 1.4V 1.4V Page 5 of 8 CY2304 Switching Waveforms All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V 3.3V 2.0V 0.8V 0V t4 t3 Output-Output Skew OUTPUT 1.4V 1.4V OUTPUT t5 Input-Output Skew INPUT VDD/2 VDD/2 FBK t6 Device-Device Skew VDD/2 FBK, Device 1 VDD/2 FBK, Device 2 t7 Test Circuits Test Circuit # 1 VDD 0.1 µF OUTPUTS CLK OUT C LOAD V DD 0.1 µF GND GND Test circuit for all parameters except t8 Document #: 38-07247 Rev. *C Page 6 of 8 CY2304 Ordering Information Ordering Code Package Name Package Type Operating Range CY2304SC–1 S8 8-pin 150-mil SOIC Commercial CY2304SI–1 S8 8-pin 150-mil SOIC Industrial CY2304SC–2 S8 8-pin 150-mil SOIC Commercial CY2304SI–2 S8 8-pin 150-mil SOIC Industrial Package Diagram 8-lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07247 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2304 Document Title: CY2304 3.3V Zero Delay Buffer Document Number: 38-07247 REV. ECN N0. Issue Date Orig. of Change Description of Change ** 110512 12/11/01 SZV Change from Spec number: 38-01010 to 38-07247 *A 112294 03/04/02 CKN On Pin Configuration Diagram (p.1), swapped CLKA2 and CLKA1 *B 113934 05/01/02 CKN Added Operating Conditions for CY2304SI-X Industrial Temperature Devices, p. 4 *C 121851 12/14/02 RBI Document #: 38-07247 Rev. *C Power up requirements added to Operating Conditions Information Page 8 of 8