16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC AD7621 FEATURES APPLICATIONS Medical instruments High speed data acquisition Digital signal processing Communications Instrumentation Spectrum analysis ATE FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND DVDD DGND AGND OVDD AD7621 AVDD OGND REF REF AMP IN+ SERIAL PORT SWITCHED CAP DAC IN– 16 D[15:0] PARALLEL INTERFACE PDREF BUSY RD CLOCK PDBUF PD SER/PAR CS CONTROL LOGIC AND CALIBRATION CIRCUITRY OB/2C RESET BYTESWAP 04565-001 Throughput 3 MSPS (wideband warp and warp mode) 2 MSPS (normal mode) 1.25 MSPS (impulse mode) 2.048 V internal reference Differential input range: ±VREF (VREF up to 2.5 V) INL: ±2 LSB maximum, ±1 LSB typical 16-bit resolution with no missing codes SINAD: 89 dB typical @ 100 kHz THD: −101 dB typical @ 100 kHz No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible 2.5 V single-supply operation Power dissipation: 65 mW typical @ 3 MSPS 48-lead LQFP and 48-lead LFCSP_VQ packages Speed upgrade of the AD7677 WARP IMPULSE CNVST Figure 1. Table 1. PulSAR Selection Type/kSPS Pseudo Differential True Bipolar True Differential 18-Bit Multichannel/ Simultaneous 100 to 250 AD7651 AD7660/61 AD7663 500 to 570 AD7650/52 AD7664/66 AD7665 800 to 1000 AD7653 AD7667 AD7671 AD7675 AD7678 AD7676 AD7679 AD7677 AD7674 AD7654 AD7655 >1000 AD7621 AD7641 GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7621 is a 16-bit, 3 MSPS, charge redistribution SAR, fully differential analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. It features two very high sampling rate modes (wideband warp and warp), a fast mode (normal) for asynchronous rate applications, and a reduced power mode (impulse) for low power applications where the power is scaled with the throughput. Operation is specified from −40°C to +85°C. 1. Fast Throughput. The AD7621 is a 3 MSPS, charge redistribution, 16-bit SAR ADC. 2. Superior Linearity. The AD7621 has no missing 16-bit code. 3. Internal Reference. The AD7621 has a 2.048 V internal reference with a typical drift of ±7 ppm/°C. 4. Single-Supply Operation. The AD7621 operates from a 2.5 V single supply and typically dissipates 65 mW. In impulse mode, its power dissipation decreases with the throughput. 5. Serial or Parallel Interface. Versatile parallel (16- or 8-bit bus) or 2-wire serial interface arrangement compatible with 2.5 V, 3.3 V, or 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. AD7621 TABLE OF CONTENTS Specifications..................................................................................... 3 Voltage Reference Input ............................................................ 18 Timing Specifications....................................................................... 5 Power Supply............................................................................... 19 Serial Clock Timing Specifications ............................................ 6 Power Dissipation vs. Throughput .......................................... 20 Absolute Maximum Ratings............................................................ 7 Conversion Control ................................................................... 20 ESD Caution.................................................................................. 7 Interfaces.......................................................................................... 21 Pin Configuration and Function Descriptions............................. 8 Digital Interface.......................................................................... 21 Terminology .................................................................................... 11 Parallel Interface......................................................................... 21 Typical Performance Characteristics ........................................... 12 Serial Interface ............................................................................ 22 Theory of Operation ...................................................................... 15 Master Serial Interface............................................................... 22 Circuit Information.................................................................... 15 Slave Serial Interface .................................................................. 24 Converter Operation.................................................................. 15 Microprocessor Interfacing....................................................... 26 Modes of Operation ................................................................... 15 Application ...................................................................................... 27 Transfer Functions...................................................................... 16 Layout .......................................................................................... 27 Typical Connection Diagram ................................................... 17 Evaluating the AD7621 Performance ...................................... 27 Analog Inputs.............................................................................. 17 Outline Dimensions ....................................................................... 28 Driver Amplifier Choice............................................................ 17 Ordering Guide .......................................................................... 29 REVISION HISTORY 5/05 — Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7621 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance 2 THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error 3 No Missing Codes Differential Linearity Error Transition Noise Transition Noise Zero Error, TMIN to TMAX 5 Zero Error Temperature Drift Gain Error, TMIN to TMAX5 Gain Error Temperature Drift Power Supply Sensitivity AC ACCURACY Dynamic Range Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Conditions Min 16 VIN+ − VIN− VIN+, VIN− to AGND fIN = 100 kHz 3 MSPS throughput −VREF −0.1 Wideband warp, warp modes Wideband warp, warp modes Wideband warp, warp modes Normal mode Normal mode Impulse mode Impulse mode All modes VREF = 2.048 V, PDREF = high VREF = 2.048 V, PDREF = high VREF = 2.048 V, PDREF = high VREF = 2.5 V VREF = 2.048 V Typ Max Unit Bits VREF AVDD 1 V V dB μA 333 3 1 500 2 800 1.25 ns MSPS ms ns MSPS ns MSPS +2 ±2 ±3 LSB 4 Bits LSB LSB LSB LSB ppm/°C % of FSR ppm/°C LSB 90.5 90 88 89.2 103 101 –102 −100 89.8 87.5 89 50 dB 6 dB dB dB dB dB dB dB dB dB dB MHz 1 5 ns ps rms ns 55 25 0.001 0 0 −2 16 −1 ±1 +2 0.69 0.82 −30 +30 ±1 −0.38 AVDD = 2.5 V ± 5% fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V fIN = 20 kHz fIN = 100 kHz fIN = 20 kHz fIN = 100 kHz fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V Full-scale step PDREF = PDBUF = low REF @ 25°C –40°C to +85°C AVDD = 2.5 V ± 5% Rev. 0 | Page 3 of 32 88 86 87.5 +0.38 50 2.038 2.048 ±7 ±15 2.058 V ppm/°C ppm/V AD7621 Parameter Turn-On Settling Time REFBUFIN Output Voltage REFBUFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFBUFIN Input Voltage Range TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 7 Pipeline Delay 8 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current 10 AVDD 11 DVDD OVDD Power Dissipation11 With Internal Reference10 Without Internal Reference10 With Internal Reference 12 Without Internal Reference12 In Power-Down Mode 13 TEMPERATURE RANGE 14 Specified Performance Conditions CREF = 10 μF REFBUFIN @ 25°C PDREF = PDBUF = high REF 3 MSPS throughput PDREF = high, PDBUF = low Min Typ 5 1.2 6.33 Max Unit ms V kΩ 1.8 2.048 250 AVDD V μA 1.05 1.2 1.30 V @ 25°C 273 0.85 4.7 –0.3 1.7 –1 –1 ISINK = 500 μA ISOURCE = –500 μA 3 MSPS throughput With internal reference V V μA μA 0.4 V V 2.5 2.5 2.63 2.63 3.6 V V V 25.2 3.6 1 3 MSPS throughput 3 MSPS throughput 1.25 MSPS throughput 1.25 MSPS throughput PD = high 70 65 42 37 600 –40 1 +0.6 5.25 +1 +1 OVDD − 0.3 2.37 2.37 2.30 9 TMIN to TMAX mV mV/°C kΩ mA mA mA 86 80 55 50 mW mW mW mW μW +85 °C When using an external reference. With the internal reference, the input range is −0.1 V to VREF. See the Analog Inputs section. 3 Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V. 4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV. 5 See the Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 16-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 In warp mode. Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 12 In impulse mode. Tested in parallel reading mode. 13 With all digital inputs forced to OVDD. 14 Consult factory for extended temperature range. 2 Rev. 0 | Page 4 of 32 AD7621 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter CONVERSION AND RESET (Refer to Figure 31 and Figure 32) Convert Pulse Width Time Between Conversions (Warp 2 Mode/Normal Mode/Impulse Mode) 3 CNVST Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) Aperture Delay End of Conversion to BUSY Low Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) RESET Pulse Width RESET Low to BUSY High Delay 4 BUSY High Time from RESET Low4 PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35) CNVST Low to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY Low Delay Bus Access Request to DATA Valid Bus Relinquish Time MASTER SERIAL INTERFACE MODES 5 (Refer to Figure 37 and Figure 38) CS Low to SYNC Valid Delay CS Low to Internal SCLK Valid Delay5 CS Low to SDOUT Delay CNVST Low to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay Internal SCLK Period 6 Internal SCLK High6 Internal SCLK Low6 SDOUT Valid Setup Time6 SDOUT Valid Hold Time6 SCLK Last Edge to SYNC Delay6 CS High to SYNC HI-Z CS High to Internal SCLK HI-Z CS High to SDOUT HI-Z BUSY High in Master Serial Read after Convert6 CNVST Low to SYNC Asserted Delay (All Modes) SYNC Deasserted to BUSY Low Delay Symbol Min t1 t2 t3 t4 t5 t6 t7 t8 t9 t38 t39 15 333/500/800 Typ Rev. 0 | Page 5 of 32 70 1 ns ns ns ns ns ns ns ns ns ns ns 1 10 283/430/560 50/70/50 15 10 600 283/430/560 ns 20 15 ns ns ns 10 10 10 ns ns ns 2 2 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 Unit 23 283/430/560 t10 t11 t12 t13 Max 12/137/263 0.5 8 2 3 1 0 0 12 10 10 10 See Table 4 275/400/500 13 ns ns ns ns ns ns ns ns ns ns ns ns ns AD7621 Parameter SLAVE SERIAL INTERFACE MODES5 (Refer to Figure 40 and Figure 41) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK High External SCLK Low Symbol Min t31 t32 t33 t34 t35 t36 t37 5 1 5 5 12.5 5 5 Typ Max Unit ns ns ns ns ns ns ns 8 1 See the Conversion Control section. All timings for wideband warp mode are the same as warp mode. 3 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 4 See the Digital Interface, and RESET sections. 5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. 2 SERIAL CLOCK TIMING SPECIFICATIONS Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK High Minimum Internal SCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum (Wideband and Warp Modes) BUSY High Width Maximum (Normal Mode) BUSY High Width Maximum (Impulse Mode) 500μA Symbol t18 t19 t19 t20 t21 t22 t23 t24 t28 t28 t28 0 0 0.5 8 12 2 3 1 0 0 0.500 0.650 0.780 0 1 3 16 25 6 7 5 0.5 0.5 0.720 0.870 1.000 1 0 3 32 50 15 16 5 10 9 1.160 1.310 1.440 1 1 3 64 100 31 32 5 28 26 2.040 2.190 2.320 Unit ns ns ns ns ns ns ns ns μs μs μs 2V IOL 0.8V 1.4V tDELAY 2V CL 50pF 0.8V Figure 3. Voltage Reference Levels for Timing IOH NOTE IN SERIAL INTERFACE MODES, THE SYNC, SCLK AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD. CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. 04565-002 500μA 2V 0.8V Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 32 05665-003 tDELAY TO OUTPUT PIN AD7621 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+ 1 , IN−, REF, REFBUFIN, TEMP, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD OVDD AVDD to DVDD AVDD to OVDD OVDD to DVDD 2 Digital Inputs PDREF, PDBUF 3 Internal Power Dissipation 4 Internal Power Dissipation 5 Junction Temperature Storage Temperature Range Rating AVDD + 0.3 V to AGND − 0.3 V ±0.3 V –0.3 V to +2.7 V –0.3 V to +3.8 V ±2.8 V +2.8 V to −3.8 V ≤ +0.3 V if DVDD < 2.3 V −0.3 V to +5.5 V ±20 mA 700 mW 2.5 W 125°C –65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. 1 See the Analog Inputs section. See the Power Supply section. See the Voltage Reference Input section. 4 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. 5 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. 2 3 Rev. 0 | Page 7 of 32 AD7621 REFGND REF IN– AGND NC IN+ AGND AVDD TEMP PDREF REFBUFIN PDBUF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 36 AGND PIN 1 IDENTIFIER 35 CNVST NC 3 BYTESWAP 4 34 PD 33 RESET OB/2C 5 32 CS AD7621 WARP 6 IMPULSE 7 31 RD TOP VIEW (Not to Scale) SER/PAR 8 30 DGND 29 BUSY D0 9 D1 10 28 D15 D2/DIVSCLK[0] 11 D3/DIVSCLK[1] 12 26 D13 25 D12 04565-004 D11/RDERROR D9/SCLK D10/SYNC DVDD DGND D8/SDOUT OVDD OGND D7/RDC/SDIN D6/INVSCLK D4/EXT/INT 13 14 15 16 17 18 19 20 21 22 23 24 D5/INVSYNC NC = NO CONNECT 27 D14 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 41, 42 2, 44 3, 40 4 Mnemonic AGND AVDD NC BYTESWAP Type 1 P P 5 OB/2C DI 6 WARP DI 7 IMPULSE DI 8 SER/PAR DI 9, 10 11, 12 D[0:1] D[2:3] or DIVSCLK[0:1] DO DI/O 13 D4 or EXT/INT DI/O DI Description Analog Power Ground Pin. Input Analog Power Pins. Nominally 2.5 V. No Connect. Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. Conversion Mode Selection. When WARP = high and IMPULSE = high, this selects wideband mode with slightly improved linearity and THD. When WARP = high and IMPULSE = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When WARP = low and IMPULSE = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. Conversion Mode Selection. When IMPULSE = high and WARP = low, this input selects impulse mode, a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low, the parallel port is selected. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. When SER/PAR = high, serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus. When SER/PAR = high, serial clock source select. This input is used to select the internally generated (master ) or external (slave) serial data clock. When EXT/INT = low: master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high: slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. Rev. 0 | Page 8 of 32 AD7621 Pin No. 14 Mnemonic D5 or INVSYNC Type 1 DI/O 15 D6 or INVSCLK D7 or RDC DI/O 16 DI/O or SDIN 17 18 OGND OVDD P P 19 20 21 DVDD DGND D8 or SDOUT P P DO 22 D9 DI/O or SCLK 23 D10 or SYNC DO 24 D11 DO or RDERROR 25 to 28 29 D[12:15] BUSY DO DO 30 31 DGND RD P DI Description When SER/PAR = low this output is used as Bit 5 of the parallel port data output bus. When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. When SER/PAR = low this output is used as Bit 6 of the parallel port data output bus. Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal. Bit 7 of the Parallel Port Data Output Bus. When SER/PAR = high, read during convert. When using Serial Master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is read during current conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result is read after conversion. Serial Data In. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read sequence. Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). Digital Power. Nominally at 2.5 V. Digital Power Ground. When SER/PAR = low this output is used as Bit 8 of the parallel port data output bus. When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode (EXT/INT = low). SDOUT is valid on both edges of SCLK. In slave mode (EXT/INT = high): When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. Parallel Port Data Output Bus Bit 9. When SER/PAR = low, this output is used as Bit 9 of the parallel port data output bus. Serial Clock. When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus. When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. Parallel Port Data Output Bus Bit 11. When SER/PAR = low, this output is used as Bit 11 of the parallel port data output bus. Read Error. When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data Output Bus. Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. Digital Power Ground. Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. Rev. 0 | Page 9 of 32 AD7621 Pin No. 32 Mnemonic CS Type 1 DI 33 RESET DI 34 PD DI 35 CNVST DI 36 37 AGND REF P AI/O 38 39 43 45 46 REFGND IN− IN+ TEMP REFBUFIN AI AI AI AO AI/O 47 PDREF DI 48 PDBUF DI 1 Description Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. Reset Input. When high, reset the AD7621. Current conversion if any is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND. Power-Down Input. When high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. Analog Power Ground Pin. Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. Reference Input Analog Ground. Differential Negative Analog Input. Differential Positive Analog Input. Temperature Sensor Analog Output. Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Rev. 0 | Page 10 of 32 AD7621 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full-scale through positive fullscale. The point used as negative full-scale occurs ½ LSB before the first code transition. Positive full-scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Gain Error The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full-scale (−2.0479688 V for the ±2.048 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSBs below the nominal full-scale (2.0479531 V for the ±2.048 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Zero Error The zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7621 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as TCVREF (ppm/°C ) = VREF ( Max) – VREF ( Min) × 10 6 VREF (25°C ) × (TMAX – TMIN ) where: VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX VREF (25°C) = VREF at 25°C TMAX = +85°C TMIN = –40°C Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Rev. 0 | Page 11 of 32 AD7621 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.5 1.0 1.0 DNL (LSB) INL (LSB) 0.5 0 –0.5 0.5 0 –1.0 04565-005 –2.0 0 16384 32768 –1.0 65536 49152 04565-008 –0.5 –1.5 0 16384 32768 Figure 8. Differential Nonlinearity vs. Code Figure 5. Integral Nonlinearity vs. Code 160000 149969 σ = 0.82 σ = 0.69 140000 140000 120000 120000 100000 100000 COUNTS 80000 60000 51847 54791 80000 60842 59637 60000 40000 40000 13 2415 2080 5 0 8003 8004 0 7FFC 7FFD 7FFE 7FFF 8000 8001 CODE IN HEX 8002 20000 6644 128 0 8003 8004 0 7FFC 7FFD 7FFE 7FFF 8000 8001 CODE IN HEX 8002 Figure 9. Histogram of 261,120 Conversions of a DC Input at the Code Center (Internal Reference) Figure 6. Histogram of 261,120 Conversions of a DC Input at the Code Center (External Reference) 10 2.0525 2.0520 2.0515 2.0510 2.0505 2.0500 2.0495 04565-007 2.0490 2.0485 –35 –15 5 25 45 65 85 105 ZERO SCALE, FULL-SCALE ERROR (LSB) 2.0530 2.0480 –55 6376 176 0 04565-009 0 04565-006 20000 VREF (V) 127317 6 4 2 –FS 0 –2 –4 ZERO ERROR –6 –8 +FS –10 –55 125 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units) 8 04565-010 COUNTS 160000 65536 49152 CODE CODE Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature Rev. 0 | Page 12 of 32 AD7621 –80 –100 –120 04565-011 –140 –180 0 SNR = 89.9dB THD = –104.9dB SFDR = 106.6dB SINAD = 89.8dB –40 –60 –80 –100 –120 –140 04565-014 –60 –160 –160 –180 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. FFT 20 kHz Figure 14. FFT 100 kHz 95 16.0 92 93 15.6 91 91 15.2 SNR 16.0 SNR 90 15.5 SINAD 14.0 85 ENOB 83 13.6 81 13.2 SNR, SINAD (dB) 14.4 87 ENOB (Bits) 14.8 89 SNR, SINAD (dB) AMPLITUDE (dB of Full-Scale) –40 fS = 3MSPS fIN = 98.79kHz –20 SNR = 90.1dB THD = –103.2dB SFDR = 103.8dB SINAD = 89.9dB SINAD 89 88 15.0 87 ENOB 14.5 86 12.8 77 12.4 12.0 1000 75 1 10 100 85 04565-012 79 ENOB (Bits) –20 AMPLITUDE (dB of Full-Scale) 0 fS = 3MSPS fIN = 20.1kHz 84 –55 –35 –15 5 25 45 65 85 105 14.0 125 04565-015 0 TEMPERATURE (°C) FREQUENCY (kHz) Figure 12. SNR, SINAD and ENOB vs. Frequency Figure 15. SNR, SINAD, and ENOB vs. Temperature –70 120 –80 –75 110 –85 105 –80 100 –90 100 –85 90 –95 95 –90 80 110 SFDR THD 50 –105 THIRD HARMONIC –110 –115 40 30 SECOND HARMONIC –120 1 10 100 20 1000 90 THD –105 85 –110 80 THIRD HARMONIC –115 75 SECOND HARMONIC –120 70 –125 65 –130 –55 –35 –15 5 25 45 65 85 105 60 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 13. THD, Harmonics, and SFDR vs. Frequency Figure 16. THD, Harmonics, and SFDR vs. Temperature Rev. 0 | Page 13 of 32 SFDR (dB) –100 04565-016 60 THD, HARMONICS (dB) 70 SFDR (dB) –95 –100 04565-013 THD, HARMONICS (dB) SFDR AD7621 100k AVDD, WARP/NORMAL SNR OPERATING CURRENTS (μA) 10k 90.5 SINAD 90.0 1k AVDD, IMPULSE 100 OVDD = 3.3V, ALL MODES 10 DVDD, ALL MODES OVDD, 2.5V, ALL MODES 89.5 –60 –50 –40 –30 –20 –10 0.1 10 0 04565-020 1 04565-017 SNR, SINAD REFERRED TO FULL-SCALE (dB) 91.0 PDREF = PDBUF = HIGH 100 1k INPUT LEVEL (dB) 10k 100M 1M 10M SAMPLING RATE (SPS) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 19. Operating Current vs. Sample Rate 16 280 20 14 270 18 260 16 OVDD = 2.5V @ 85°C OVDD = 2.5V @ 25°C AVDD OVDD = 3.3V @ 25°C 12 8 240 6 230 4 220 8 210 6 2 DVDD 0 –55 –35 –15 5 25 45 65 85 105 200 125 OVDD = 3.3V @ 85°C 14 10 04565-022 t12 DELAY (ns) 250 OVDD, 2.5V AVDD (μA) OVDD, 3.3V 10 04565-019 DVDD, OVDD (μA) 12 4 0 TEMPERATURE (°C) 50 100 150 200 CL (pF) Figure 18. Power-Down Operating Currents vs. Temperature Figure 20. Typical Delay vs. Load Capacitance CL Rev. 0 | Page 14 of 32 AD7621 THEORY OF OPERATION IN+ AGND LSB MSB 32,768C 16,384C 4C 2C C SW+ SWITCHES CONTROL C BUSY REF COMP REFGND 4C 2C MSB C OUTPUT CODE C SW– LSB CNVST AGND IN– 04565-024 32,768C 16,384C CONTROL LOGIC Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7621 is a very fast, low power, single-supply, precise, 16-bit analog-to-digital converter (ADC) using successive approximation architecture. The AD7621 features different modes to optimize performances according to the applications. In warp mode, the AD7621 is capable of converting 3,000,000 samples per second (3 MSPS). The AD7621 provides the user with an on-chip track-and-hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7621 can be operated from a single 2.5 V supply and be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed in 48-lead LQFP or tiny LFCSP packages that combine space savings with flexibility, allowing the AD7621 to be configured as either a serial or parallel interface. The AD7621 is pin-to-pin-compatible with, and a speed upgrade of, the AD7677. CONVERTER OPERATION The AD7621 is a successive approximation analog-to-digital converter (ADC) based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is complete and the CNVST input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 through VREF/65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. MODES OF OPERATION The AD7621 features four modes of operation: wideband warp, warp, normal, and impulse. Each of these modes is more suitable to specific applications. Wideband warp (WARP = high, IMPULSE = high) and warp (WARP = high, IMPULSE = low) modes allow the fastest conversion rate up to 3 MSPS. However, in these modes, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (after power up), the first conversion result should be ignored. These modes make the AD7621 ideal for applications where both high accuracy and fast sample rate are required. Wideband warp mode offers slightly improved linearity and THD over warp mode. Normal mode (WARP = low, IMPULSE = low) is the fastest mode (2 MSPS) without any limitation on time between conversions. This mode makes the AD7621 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. Impulse mode (WARP = low, IMPULSE = high), the lowest power dissipation mode, allows power saving between conversions. The maximum throughput in this mode is 1.25 MSPS. In this mode, the ADC powers down circuits after conversion making the AD7621 ideal for battery-powered applications. Rev. 0 | Page 15 of 32 AD7621 TRANSFER FUNCTIONS Table 7. Output Codes and Ideal Input Voltages 1 2 000...010 000...001 000...000 –FSR –FSR+1 LSB –FSR+0.5 LSB Analog Input VREF = 2.048 V +2.047938 V +2.047875 V +62.5 μV 0V −62.5 μV −2.047938 V −2.048 V Description FSR −1 LSB FSR − 2 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 111...111 111...110 111...101 Digital Output Code Straight Twos Binary Complement 0xFFFF 1 0x7FFF1 0xFFFE 0x7FFE 0x8001 0x0001 0x8000 0x0000 0x7FFF 0xFFFF 0x0001 0x8001 0x0000 2 0x80002 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). This is also the code for underrange analog input (VIN+ − VIN− below −VREF + VREFGND). +FSR–1 LSB 04565-025 ADC CODE (Straight Binary) Using the OB/2C digital input, the AD7621 offers two output codings: straight binary and twos complement. The LSB size with VREF = 2.048 V is 2 × VREF/65536, which is 62.5 μV. Refer to Figure 22 and Table 7 for the ideal transfer characteristic. +FSR–1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function DIGITAL SUPPLY (2.5V) NOTE 5 DIGITAL INTERFACE SUPPLY (2.5V OR 3.3V) 10Ω ANALOG SUPPLY (2.5V) 100nF 10μF 10μF AVDD REF CREF 10μF AGND 100nF 10μF 100nF DGND DVDD OVDD NOTE 3 OGND SERIAL PORT SCLK REFBUFIN 100nF SDOUT REFGND NOTE 4 BUSY 50Ω 10Ω ANALOG INPUT + U1 D CNVST IN+ 50pF AD7621 CC MICROCONVERTER/ MICROPROCESSOR/ DSP NOTE 7 NOTE 2 1nF OB/2C SER/PAR NOTE 1 OVDD WARP IMPULSE NOTE 2 CS 10Ω ANALOG INPUT – U2 CC RD IN– 1nF NOTE 1 NOTE 3 PD PDREF PDBUF CLOCK 50pF RESET 10kΩ 1. SEE ANALOG INPUT SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10μF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 23. Typical Connection Diagram Rev. 0 | Page 16 of 32 04565-026 NOTE 6 AD7621 TYPICAL CONNECTION DIAGRAM Figure 23 shows a typical connection diagram for the AD7621. Different circuitry from that shown in this diagram are optional and are discussed below. ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7621. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V as this causes the diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer’s U1 or U2 supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. comprised of some serial resistors and the on resistance of the switches. CIN is typically 12 pF and is mainly the ADC sampling capacitor. During the conversion phase, when the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a one-pole, low-pass filter that has a typical −3 dB cutoff frequency of 50 MHz, thereby reducing an undesirable aliasing effect while limiting noise from the inputs. Since the input impedance of the AD7621 is very high, the AD7621 can be directly driven by a low impedance source without gain error. To further improve the noise filtering achieved by the AD7621 analog input circuit, an external, onepole RC filter between the amplifier’s outputs and the ADC analog inputs can be used, as shown in Figure 23. However, large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 26. AVDD –60 PDBUF = PDREF = LOW D1 RIN IN+ OR IN– –65 –70 D2 RS = 500Ω 04565-027 –75 THD (dB) AGND Figure 24. AD7621 Simplified Analog Input. The analog input of AD7621 is a true differential structure. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 25, representing the typical CMRR over frequency with internal and external references. –80 –85 RS = 100Ω –90 RS = 50Ω –95 04565-029 CPIN CIN –100 RS = 10Ω –105 1 75 10 100 INPUT FREQUENCY (kHz) 1k Figure 26. THD vs. Analog Input Frequency and Source Resistance 70 DRIVER AMPLIFIER CHOICE CMRR (dB) 65 Although the AD7621 is easy to drive, the driver amplifier needs to meet the following requirements: EXT REF 60 INT REF 55 • Together, the driver amplifier and the AD7621 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. The AD8021 op amp, which combines ultralow noise and high gain bandwidth, meets this settling time requirement even when used with gains up to 13. • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7621. The noise 04565-099 50 45 1 10 100 1k 10k FREQUENCY (kHz) Figure 25. Analog Input CMRR vs. Frequency During the acquisition phase for ac signals, the impedance of the analog inputs, IN+ and IN−, can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 350 Ω and is a lumped component Rev. 0 | Page 17 of 32 AD7621 coming from the driver is filtered by the AD7621 analog input circuit one-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. The SNR degradation due to the amplifier is 590Ω ⎞ ⎟ ⎟⎟ ⎠ 10Ω 590Ω IN+ 1nF AD7621 1kΩ N is the noise factor of the amplifier (+1 in buffer configuration). eN is the equivalent input voltage noise density of the op amp, in nV/√Hz. 10Ω U2 1kΩ f–3dB is the input bandwidth of the AD7621 (50 MHz) or the cutoff frequency of the input filter (16 MHz), if one is used. AD8021 100nF IN– REF 1nF 10pF 10μF Figure 27. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) VOLTAGE REFERENCE INPUT For instance, a driver with an equivalent input noise density of 2.1 nV/√Hz, like the AD8021 with a noise gain of +1 when configured as a buffer, degrades the SNR by only 0.33 dB when using the RC filter in Figure 23, and by 1 dB without. The driver needs to have a THD performance suitable to that of the AD7621. Figure 13 gives the THD vs. frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In applications with a gain of 1, an 82 pF compensation capacitor is required. The AD8610 is an option when low bias current is needed in low frequency applications. Single-to-Differential Driver For applications using unipolar analog signals, a single-endedto-differential driver, as shown in Figure 27, allows for a differential input into the part. This configuration, when provided an input signal of 0 to VREF, will produce a differential ±VREF with midscale at VREF/2. The one-pole filter using R = 10 Ω and C = 1 nF provides a corner frequency of 16 MHz. If the application can tolerate more noise, the AD8139 differential driver can be used. AD8021 10pF where: • U1 04565-030 SNRLOSS ⎛ 53 ⎜ = 20 log⎜ 2 ⎜ 2809 + πf − 3dB ( Ne N ) ⎝ ANALOG INPUT (UNIPOLAR 0V TO 2.048V) The AD7621 allows the choice of either a very low temperature drift internal voltage reference or an external reference. Unlike many ADCs with internal references, the internal reference of the AD7621 provides excellent performance and can be used in almost all applications. Internal Reference (PDBUF = Low, PDREF = Low) To use the internal reference, the PDREF and PDBUF inputs must be low. This produces a 1.2 V band gap output on REFBUFIN which, amplified by the internal buffer, results in a 2.048 V reference on the REF pin. The internal reference is temperature-compensated to 2.048 V ± 10 mV. The reference is trimmed to provide a typical drift of 7 ppm/°C. This typical drift characteristic is shown in Figure 7. The output resistance of the REFBUFIN is 6.33 kΩ (minimum) when the internal reference is enabled. It is necessary to decouple this with a ceramic capacitor greater than 100 nF. Thus, the capacitor provides an RC filter for noise reduction. Since the output impedance of REFBUFIN is typically 6.33 kΩ, relative humidity (among other industrial contaminates) can directly affect the drift characteristics of the reference. Typically, a guard ring is used to reduce the effects of drift under such circumstances. However, since the AD7621 has a fine lead pitch, guarding this node is not practical. Therefore, in these industrial and other types of applications, it is recommended to use a conformal coating such as Dow Corning 1-2577 or Humiseal 1B73. External 1.2 V Reference and Internal Buffer (PDREF = High, PBBUF = Low) To use an external reference with the internal buffer, PDREF should be high and PDBUF should be low. This powers down the internal reference and allows the 1.2 V reference to be applied to REFBUFIN. Rev. 0 | Page 18 of 32 AD7621 External Reference (PDBUF = High, PRBUF = High) Temperature Sensor To use an external reference directly on the REF pin, PDREF and PDBUF should both be high. The TEMP pin measures the temperature of the AD7621. To improve the calibration accuracy over the temperature range, the output of the TEMP pin is applied to one of the inputs of the analog switch (such as, ADG779), and the ADC itself is used to measure its own temperature. This configuration is shown in Figure 28. • SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a reference voltage very close to the supply (2.5 V) instead of a typical 2.048 V reference when the internal reference is used. This is calculated by TEMPERATURE SENSOR IN+ ANALOG INPUT (UNIPOLAR) AD8021 ⎛ 2.048 ⎞ SNR = 20 log⎜ ⎟ ⎝ 2.50 ⎠ • TEMP ADG779 04565-031 For improved drift performance, an external reference, such as the AD780 or ADR431, can be used. The advantages of directly using the external voltage reference are: AD7621 CC Figure 28. Use of the Temperature Sensor Power savings when the internal reference is powered down (PBREF = PDBUF = high). POWER SUPPLY PDREF and PDBUF power down the internal reference and the internal reference buffer, respectively. Reference Decoupling Whether using an internal or external reference, the AD7621 voltage reference input (REF) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 10 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: • The low noise, low temperature drift ADR431 and AD780 • The low power ADR291 • The low cost AD1582 The AD7621 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 23. Power Sequencing The AD7621 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V until DVDD = 2.3 V during any time; for instance, at power-up or power-down (see the Absolute Maximum Ratings section). Additionally, it is very insensitive to power supply variations over a wide frequency range as shown in Figure 29. 75 70 The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C. Rev. 0 | Page 19 of 32 EXT REF 60 INT REF 55 50 04565-098 For applications that use multiple AD7621 devices, it is more effective to use the internal reference buffer in order to buffer the reference voltage. PSRR (dB) 65 The placement of the reference decoupling is also important to the performance of the AD7621. The decoupling capacitor should be mounted on the same side as the ADC right at the REF pin with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance. 45 1 10 100 FREQUENCY (kHz) Figure 29. PSRR vs. Frequency 1k 10k AD7621 Power-Up CONVERSION CONTROL At power-up, or returning to operational mode from the powerdown mode (PD = high), the AD7621 engages an initialization process. During this time, the first 128 conversions should be ignored or the RESET input could be pulsed to engage a faster initialization process. Refer to the Digital Interface section for RESET and timing details. The AD7621 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown in Figure 31. Once initiated, it cannot be restarted or aborted, even by the power-down input, PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. t2 t1 t1 CNVST BUSY POWER DISSIPATION VS. THROUGHPUT t4 t3 In impulse mode, the AD7621 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low which allows a significant power saving when the conversion rate is reduced (see Figure 30). This feature makes the AD7621 ideal for very low power, battery-operated applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, OVDD and OGND). 100k t6 t5 MODE ACQUIRE CONVERT t7 ACQUIRE CONVERT t8 04565-034 A simple power-on reset circuit, as shown in Figure 23, can be used to minimize the digital interface. As OVDD powers up, the capacitor is shorted and brings RESET high; it is then charged returning RESET to low. However, this circuit only works when powering up the AD7621 because the power down mode (PD = high) does not power down any of the supplies. As a result, RESET is low. Figure 31. Basic Conversion Timing For optimal performance, the rising edge of CNVST should not occur after the maximum CNVST low time, t1, or until the end of conversion. Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot, undershoot, or ringing. The CNVST trace should be shielded with ground and a low value (such as 50 Ω) serial resistor termination should be added close to the output of the component that drives this line. Also, a 60 pF capacitor is recommended to further reduce the effects of overshoot and undershoot as shown in Figure 23. 10k IMPULSE MODE POWER 1k PDREF = PDBUF = HIGH 100 100 1k 10k 100k 1M 04565-032 POWER DISSIPATION (μW) WARP MODE POWER For applications where SNR is critical, the CNVST signal should have very low jitter. This can be achieved by using a dedicated oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 23. 10M SAMPLING RATE (SPS) Figure 30. Power Dissipation vs. Sample Rate Rev. 0 | Page 20 of 32 AD7621 INTERFACES DIGITAL INTERFACE PARALLEL INTERFACE The AD7621 has a versatile digital interface that can be set up as either a serial or parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7621 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic high output voltage. In most applications, the OVDD supply pin of the AD7621 is connected to the host system interface 2.5 V or 3.3 V digital supply. Finally, by using the OB/2C input pin, both twos complement or straight binary coding can be used. The AD7621 is configured to use the parallel interface when SER/PAR is held low. RESET Data can be continuously read by tying CS and RD low thus requiring minimal microprocessor connections. However, in this mode the data bus is always driven and cannot be used in shared bus applications (unless the device is held in RESET). Figure 33 details the timing for this mode. CS = RD = 0 t1 CNVST t10 BUSY t4 t3 DATA BUS t11 PREVIOUS CONVERSION DATA 04565-036 The two signals, CS and RD, control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7621 in multicircuit applications and is held low in a single AD7621 design. RD is generally used to enable the conversion result on the data bus. Master Parallel Interface NEW DATA Figure 33. Master Parallel Data Timing for Reading (Continuous Read) The RESET input is used to reset the AD7621 and generate a fast initialization. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET clears the data bus and engages the initialization process indicated by pulsing BUSY high. Conversions can take place after the falling edge of BUSY. Refer to Figure 32 for the RESET timing details. t9 RESET CNVST Slave Parallel Interface In slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 34 and Figure 35, respectively. When the data is read during the conversion, it is recommended that it is read-only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. CS DATA RD t39 t8 BUSY Figure 32. RESET Timing DATA BUS CURRENT CONVERSION t12 t13 Figure 34. Slave Parallel Data Timing for Reading (Read After Convert) Rev. 0 | Page 21 of 32 04565-037 t38 04565-035 BUSY AD7621 CS = 0 SERIAL INTERFACE t1 CNVST, RD BUSY The AD7621 is configured to use the serial interface when SER/PAR is held high. The AD7621 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. t4 t3 MASTER SERIAL INTERFACE DATA BUS Internal Clock t12 04565-038 PREVIOUS CONVERSION t13 Figure 35. Slave Parallel Data Timing for Reading (Read During Convert) 8-Bit Interface (Master or Slave) The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 36, when BYTESWAP is low, the LSB byte is output on D[7:0] and the MSB is output on D[15:8]. When BYTESWAP is high, the LSB and MSB bytes are swapped, and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes. CS RD HIGH BYTE t12 PINS D[7:0] HI-Z LOW BYTE LOW BYTE t12 HI-Z t13 HIGH BYTE HI-Z 04565-039 HI-Z Usually, because the AD7621 is used with a fast throughput, the master read during conversion mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. In this mode, the SCLK period changes since the LSBs require more time to settle and the SCLK is derived from the SAR conversion cycle. In read after conversion mode, unlike other modes, the BUSY signal returns low after the 16 data bits are pulsed out and not at the end of the conversion phase resulting in a longer BUSY width. As a result, the maximum throughput cannot be achieved in this mode. BYTESWAP PINS D[15:8] The AD7621 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7621 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted, if desired. Depending on the read during convert input, RDC/SDIN, the data can be read after each conversion or during the following conversion. Figure 37 and Figure 38 show detailed timing diagrams of these two modes. Figure 36. 8-Bit and 16-Bit Parallel Interface Rev. 0 | Page 22 of 32 AD7621 RDC/SDIN = 0 EXT/INT = 0 INVSCLK = INVSYNC = 0 CS, RD t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 t24 t21 t26 1 SCLK 2 3 14 15 16 t15 t27 D15 X t16 D14 D2 D1 D0 04565-040 SDOUT t23 t22 Figure 37. Master Serial Data Timing for Reading (Read After Convert) RDC/SDIN = 1 EXT/INT = 0 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t19 t20 t21 t14 SCLK t15 1 t24 2 3 14 15 t18 t16 X t22 t27 D15 D14 D2 D1 D0 04565-041 SDOUT t26 16 t23 Figure 38. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 23 of 32 AD7621 External Clock The AD7621 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 40 and Figure 41 show the detailed timing diagrams of these methods. While the AD7621 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7621 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 40 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the conversion result can be read while both CS and RD are low. Data is shifted out MSB first with 16 clock pulses and is valid on the rising and falling edges of the clock. Among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 80 MHz, which accommodates both the slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7621 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 39. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite to the one used to shift out the data on SDOUT. Hence, the MSB of the upstream converter just follows the LSB of the downstream converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7621 AD7621 #2 (UPSTREAM) #1 (DOWNSTREAM) RDC/SDIN SDOUT CNVST RDC/SDIN SDOUT DATA OUT CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN 04565-042 SLAVE SERIAL INTERFACE Figure 39. Two AD7621 Devices in a Daisy-Chain Configuration External Clock Data Read During Previous Conversion Figure 41 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. The 16 bits have to be read before the current conversion is complete, otherwise; RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisy-chain feature in this mode and RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock (at least 30 MHz when impulse mode is used, 60 MHz when normal mode is used, or 80 MHz when warp mode is used) is recommended to ensure that all the bits are read during the first half of the SAR conversion phase. It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. However, this is not recommended when using the fastest throughput of any mode since the acquisition times are only 70 ns, 100 ns, and 50 ns for warp, normal, and impulse modes. If the maximum throughput is not used, thus allowing more acquisition time, then the use of a slower clock speed can be used to read the data. Rev. 0 | Page 24 of 32 AD7621 EXT/INT = 1 CS RD = 0 INVSCLK = 0 BUSY t35 t36 t37 SCLK 1 2 t31 3 14 15 16 17 18 t32 X SDOUT D15 t16 D14 D13 D1 D0 X15 X14 X14 X13 X1 X0 Y15 Y14 SDIN X15 t33 04565-043 t34 Figure 40. Slave Serial Data Timing for Reading (Read After Convert) EXT/INT = 1 CS RD = 0 INVSCLK = 0 CNVST BUSY t3 t36 SCLK t35 t37 1 2 t31 14 15 16 D15 D14 D13 D1 D0 t16 Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 25 of 32 04565-044 t32 X SDOUT 3 AD7621 The AD7621 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7621 is designed to interface with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7621 to prevent digital noise from coupling into the ADC. The following section illustrates the use of the AD7621 with an ADSP-219x SPI-equipped DSP. going low) using an interrupt line of the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00 by writing to the SPI control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mb/s allowing it to read an ADC result in less than 1 μs. When a higher sampling rate is desired, use one of the parallel interface modes. DVDD AD7621* SPI Interface (ADSP-219x) Figure 42 shows an interface diagram between the AD7621 and an SPI-equipped DSP, ADSP-219x. To accommodate the slower speed of the DSP, the AD7621 acts as a slave device and data must be read after conversion. This mode also allows the daisychain feature. The convert command could be initiated in response to an internal timer interrupt. The reading process can be initiated in response to the end-of-conversion signal (BUSY Rev. 0 | Page 26 of 32 ADSP-219x* SER/PAR BUSY EXT/INT CS SDOUT RD SCLK INVSCLK CNVST PFx SPIxSEL (PFx) MISOx SCKx PFx OR TFSx *ADDITIONAL PINS OMITTED FOR CLARITY Figure 42. Interfacing the AD7621 to SPI Interface 04565-045 MICROPROCESSOR INTERFACING AD7621 APPLICATION LAYOUT While the AD7621 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7621 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7621, or as close as possible to the AD7621. If the AD7621 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7621. To prevent coupling noise onto the die, avoid radiating noise, and to reduce feedthrough: • Do not run digital lines under the device. • Do run the analog ground plane under the AD7621. • Do shield fast switching signals, like CNVST or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. • Avoid crossover of digital and analog signals. • Run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. The power supply lines to the AD7621 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7621, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7621 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and to connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. Refer to Figure 23 for an example of this configuration. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7621 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with short, thick traces. EVALUATING THE AD7621 PERFORMANCE A recommended layout for the AD7621 is outlined in the documentation of the EVAL-AD7621CB evaluation board for the AD7621. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVALCONTROLBRD3. Rev. 0 | Page 27 of 32 AD7621 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 PIN 1 7.00 BSC SQ TOP VIEW 1.45 1.40 1.35 0.15 0.05 SEATING PLANE (PINS DOWN) 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 25 12 13 24 0.27 0.22 0.17 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 43. 48-Lead Low Profile Quad Flatpack (LQFP) [ST-48] Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12° MAX PIN 1 INDICATOR 48 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 1 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 44. 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 7 mm × 7 mm Body, Very Thin Quad [CP-48-1] Dimensions shown in millimeters Rev. 0 | Page 28 of 32 PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES AD7621 ORDERING GUIDE Model AD7621ACP AD7621ACPRL AD7621ACPZ 1 AD7621ACPZRL1 AD7621AST AD7621ASTRL AD7621ASTZ1 AD7621ASTZRL1 EVAL-AD7621CB 2 EVAL-CONTROLBRD3 3 1 2 3 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale (LFCSP_VQ) 48-Lead Lead Frame Chip Scale (LFCSP_VQ) 48-Lead Lead Frame Chip Scale (LFCSP_VQ) 48-Lead Lead Frame Chip Scale (LFCSP_VQ) 48-Lead Low Profile Quad Flatpack (LQFP) 48-Lead Low Profile Quad Flatpack (LQFP) 48-Lead Low Profile Quad Flatpack (LQFP) 48-Lead Low Profile Quad Flatpack (LQFP) Evaluation Board Controller Board Package Option CP-48-1 CP-48-1 CP-48-1 CP-48-1 ST-48 ST-48 ST-48 ST-48 Z = Pb-free part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. Rev. 0 | Page 29 of 32 AD7621 NOTES Rev. 0 | Page 30 of 32 AD7621 NOTES Rev. 0 | Page 31 of 32 AD7621 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04565–0–5/05(0) Rev. 0 | Page 32 of 32