Sony CXG1212UR High power 3p3t switch with logic control Datasheet

High Power 3P3T Switch with Logic Control
CXG1212UR
Description
This IC can be used in wireless communication systems, for example, CDMA EV-DO handsets.
The IC has on-chip logic for operation with 3 CMOS control inputs.
The Sony JPHEMT process is used for low insertion loss and on-chip logic circuit.
(Applications: Antenna switch for cellular handsets, CDMA, EV-DO)
Features
‹ Low insertion loss: 0.3dB@900MHz
‹ 3 CMOS compatible control line
Package
Small package size: 20-pin UQFN
Structure
GaAs JPHEMT MMIC
Absolute Maximum Ratings
(Ta = 25°C)
Š Bias voltage
VDD
7
V
Š Control voltage
Vctl
5
V
Š Operating temperature
Topr
–35 to +85
°C
Š Storage temperature
Tstg
–60 to +150
°C
Š RF input power
Pin = 37dBm
This IC is ESD sensitive device. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E05729
CXG1212UR
9
8
5
CRF
F1
3
F2
14
4
F5
F13
F11
GND
RF1 (CDMA1)
F10
F6
CRF
GND4
6
F7
12
13
7
F12
11
RF6 (Sub-Ant)
GND6
CRF
GND
GND
GND
CRF
10
GND
RF3 (GPS)
RF5 (Ext)
Block Diagram and Recommended Circuit
GND
F8
RF2 (CDMA2)
F4
2
F3
F9
CRF
RF4 (Main-Ant)
15
1
GND
CRF
20
CTLC
19
CTLB
18
CTLA
VDD
17
Cbypass
(100pF)
GND
16
When using this IC, the following external components should be used:
CRF: This capacitor is used for RF decoupling and must be used for all applications.
Cbypass: This capacitor is used for DC line filtering.
Truth Table
State CTLA CTLB CTLC
Mode
ON state
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10 F11 F12 F13
RF1 – RF5 OFF ON OFF OFF OFF OFF OFF OFF ON
ON ON OFF ON
1
L
L
L
CDMA1 Ext
2
L
L
H
CDMA1 Ext RF1 – RF5
OFF ON ON OFF OFF OFF OFF OFF OFF ON ON OFF OFF
CDMA2 Sub RF2 – RF6
3
H
L
L
CDMA1 Main RF1 – RF4 ON OFF OFF OFF OFF OFF OFF OFF ON
4
H
L
H
CDMA1 Main RF1 – RF4
ON OFF ON OFF OFF OFF OFF OFF OFF ON OFF ON OFF
CDMA2 Sub RF2 – RF6
5
L
H
L
GPS Ext
RF3 – RF5 OFF OFF OFF OFF OFF OFF ON ON ON OFF ON OFF ON
6
L
H
H
CDMA2 Ext
RF2 – RF5 OFF OFF OFF ON OFF OFF OFF ON OFF ON ON OFF ON
7
H
H
L
GPS Main
RF3 – RF4 OFF OFF OFF OFF ON OFF OFF ON ON OFF OFF ON
8
H
H
H
GPS Sub
RF3 – RF6 OFF OFF OFF OFF OFF ON OFF ON ON OFF ON ON OFF
-2-
ON OFF ON
ON
ON
CXG1212UR
DC Bias Conditions
(Ta = 25°C)
Item
Min.
Typ.
Max.
Unit
Vctl (H)
2.0
2.85
3.2
V
Vctl (L)
0
—
0.5
V
2.6
2.85
3.2
V
VDD
Pin Description
Pin No.
Symbol
Pin No.
Symbol
1
GND
11
GND
2
RF2 (CDMA2)
12
RF6 (Sub-Ant)
3
GND
13
GND6
4
RF1 (CDMA1)
14
GND4
5
GND
15
RF4 (Main-Ant)
6
GND
16
GND
7
RF3 (GPS)
17
VDD
8
GND
18
CTLA
9
GND
19
CTLB
10
RF5 (Ext)
20
CTLC
-3-
CXG1212UR
Electrical Characteristics
(Ta = 25°C, VDD = 2.85V)
Item
Insertion loss
Isolation
VSWR
Symbol
IL
ISO.
VSWR
2fo
Harmonics
3fo
Input IP3
IIP3
1dB compression input power
P1dB
Switching speed
TSW
Bias current
IDD
Control current
Ictl
*1
*2
*3
*4
Condition
Min.
Typ.
Max.
Unit
900MHz
0.30
0.55
dB
1.5GHz
0.40
0.65
dB
1.9GHz
0.50
0.75
dB
900MHz
23
30
dB
1.5GHz
20
30
dB
1.9GHz
18
25
dB
50Ω
1.2
—
*1
–75
–60
dBc
*3
–75
–60
dBc
*1
–75
–60
dBc
*3
–75
–60
dBc
*2
55
65
dBm
*4
55
65
dBm
32
dBm
VDD = 2.85V
4
10
µs
VDD = 2.85V
270
450
µA
Vctl (H) = 2.85V
15
45
µA
Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 900MHz
Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/2.85V control, VDD = 2.85V
Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 1.9GHz
Pin = 25dBm (1.9GHz) + 25dBm (1.901GHz), 0/2.85V control, VDD = 2.85V
-4-
CXG1212UR
Package Outline
(Unit: mm)
20PIN UQFN (PLASTIC)
x4
0.1
S
C
A-B
0.4 ± 0.1
1.3
0.55 ± 0.05
2.7
4-R0.3
15
C
11
10
20
6
A
B
2.7
16
26
0.14
1
0.
5
0.4
PIN 1 INDEX
0.18
0.07
0.25
0.05 M
S
C
A-B
0.05
S
MAX0.02
S
Solder Plating
+ 0.09
0.25 – 0.03
+ 0.09
0.14 – 0.03
S
TERMINAL SECTION
PACKAGE STRUCTURE
Note:Cutting burr of lead are 0.05mm MAX.
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.02g
SONY CODE
UQFN-20P-01
LEAD PLATING SPECIFICATIONS
ITEM
-5-
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
Sony Corporation
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