AD EVAL-AD1974EBZ 4 adc with pll, 192 khz, 24-bit codec Datasheet

4 ADC with PLL,
192 kHz, 24-Bit Codec
AD1974
FEATURES
GENERAL DESCRIPTION
Phase-locked loop generated or direct master clock
Low EMI design
107 dB dynamic range and SNR
−94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24 bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Log volume control with autoramp function
SPI®-controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S, and TDM modes
Master and slave modes up to 16-channel input/output
Available in a 48-lead LQFP
The AD1974 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential
inputs using the Analog Devices, Inc. patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a
microcontroller to adjust volume and many other parameters.
The AD1974 operates from 3.3 V digital and analog supplies.
The AD1974 is available in a single-ended output 48-lead LQFP.
The AD1974 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board phase-locked loop (PLL) to derive the
master clock from the LR clock or from an external crystal,
the AD1974 eliminates the need for a separate high frequency
master clock and can also be used with a suppressed bit clock.
The ADCs are designed using the latest continuous time architectures from Analog Devices to further minimize EMI. By
using 3.3 V supplies, power consumption is minimized, further
reducing emissions.
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT/OUTPUT
AD1974
SERIAL DATA PORT
ANALOG
AUDIO
INPUTS
ADC
ADC
QUAD
DEC
FILTER
48kHz/
96kHz/192kHz
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
ADC
PRECISION
VOLTAGE
REFERENCE
SDATA
OUT
CONTROL PORT
SPI
12.48MHz
CONTROL DATA
INPUT/OUTPUT
06614-001
ADC
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD1974
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 11
Applications....................................................................................... 1
Analog-to-Digital Converters (ADCs).................................... 11
General Description ......................................................................... 1
Clock Signals............................................................................... 11
Functional Block Diagram .............................................................. 1
Reset and Power-Down ............................................................. 11
Revision History ............................................................................... 2
Serial Control Port ..................................................................... 12
Specifications..................................................................................... 3
Power Supply and Voltage Reference....................................... 12
Test Conditions............................................................................. 3
Serial Data Ports—Data Format............................................... 12
Analog Performance Specifications ........................................... 3
TDM Modes................................................................................ 13
Crystal Oscillator Specifications................................................. 4
Daisy-Chain Mode ..................................................................... 15
Digital Input/Output Specifications........................................... 4
Control Registers ............................................................................ 18
Power Supply Specifications........................................................ 5
PLL and Clock Control Registers............................................. 18
Digital Filters................................................................................. 5
AUXPORT Control Registers ................................................... 19
Timing Specifications .................................................................. 5
ADC Control Registers.............................................................. 20
Absolute Maximum Ratings............................................................ 7
Additional Modes....................................................................... 22
Thermal Resistance ...................................................................... 7
Application Circuits ....................................................................... 23
ESD Caution.................................................................................. 7
Outline Dimensions ....................................................................... 24
Pin Configuration and Function Descriptions............................. 8
Ordering Guide............................................................................... 24
Typical Performance Characteristics ........................................... 10
REVISION HISTORY
4/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD1974
SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply Voltages (AVDD, DVDD)
3.3 V
Temperature Range 1
As specified in Table 1 and Table 2
Master Clock
12.288 MHz (48 kHz fS, 256 × fS mode)
Input Sample Rate
48 kHz
Measurement Bandwidth
20 Hz to 20 kHz
Word Width
24 bits
Load Capacitance (Digital Output)
20 pF
Load Current (Digital Output)
±1 mA or 1.5 kΩ to ½ DVDD supply
Input Voltage High
2.0 V
Input Voltage Low
0.8 V
1
Functionally guaranteed at −40°C to +125°C case temperature.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Full-Scale Input Voltage (Differential)
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise (THD + N)
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR
Input Resistance
Input Capacitance
Input Common-Mode Bias Voltage
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
Conditions
Min
All ADCs
Typ
Max
Unit
24
1.9
Bits
V rms
102
105
−96
dB
dB
dB
%
dB
mV
ppm/°C
dB
dB
dB
kΩ
pF
V
20 Hz to 20 kHz, −60 dB input
98
100
−1 dBFS
−10
−0.25
−10
100 mV rms, 1 kHz
100 mV rms, 20 kHz
FILTR pin
FILTR pin
CM pin
1.32
Rev. 0 | Page 3 of 24
0
100
−110
55
55
14
10
1.5
1.50
1.50
1.50
−87
+10
+0.25
+10
1.68
V
V
V
AD1974
Specifications measured at 130°C (case).
Table 2.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Full-Scale Input Voltage (Differential)
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise (THD + N)
Gain Error
Interchannel Gain Mismatch
Offset Error
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
Conditions
Min
All ADCs
Typ
Max
Unit
24
1.9
Bits
V rms
102
105
−96
dB
dB
dB
%
dB
mV
20 Hz to 20 kHz, −60 dB input
95
97
−1 dBFS
−10
−0.25
−10
FILTR pin
FILTR pin
CM pin
1.32
0
1.50
1.50
1.50
−87
+10
+0.25
+10
1.68
V
V
V
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter
Transconductance
Min
Typ
3.5
Max
Unit
Mmhos
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.
Table 4.
Parameter
Input Voltage High (VIH)
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Leakage
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
Conditions/Comments
MCLKI pin
IIH @ VIH = 2.4 V
IIL @ VIL = 0.8 V
IOH = 1 mA
IOL = 1 mA
Rev. 0 | Page 4 of 24
Min
2.0
2.2
Typ
Max
0.8
10
10
DVDD − 0.60
0.4
5
Unit
V
V
V
μA
μA
V
V
pF
AD1974
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
Power-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Conditions/Comments
Min
Typ
Max
Unit
DVDD
AVDD
MCLK = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
3.0
3.0
3.3
3.3
3.6
3.6
V
V
56
65
95
2.0
mA
mA
mA
mA
74
23
mA
mA
429
185
244
83
mW
mW
mW
mW
50
50
dB
dB
MCLK = 256 fS, 48 kHz
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
DIGITAL FILTERS
Table 6.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes @ 48 kHz
Factor
Min
0.4375 fS
Typ
Max
Unit
21
±0.015
24
27
0.5 fS
0.5625 fS
kHz
dB
kHz
kHz
dB
μs
79
22.9844 fS
479
TIMING SPECIFICATIONS
−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK)
AND RESET
tMH
tMH
fMCLK
fMCLK
tPDR
tPDRR
Condition
Comments
Min
Max
Unit
MCLK duty cycle
ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS
ADC clock source = direct MCLK @ 512 fS (bypass
on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
40
40
60
60
%
%
6.9
13.8
27.6
MHz
MHz
ns
tMCLK
MCLK frequency
Low
Recovery
Reset to active output
Rev. 0 | Page 5 of 24
15
4096
AD1974
Parameter
PLL
Lock Time
256 fS VCO Clock
Output Duty Cycle
MCLK_O Pin
SPI PORT
tCCH
tCCL
fCCLK
Condition
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALS
tABDD
AUXILIARY INTERFACE
tXDS
tXDH
tXBH
tXBL
tXLS
tXLH
CDATA setup
CDATA hold
Setup
Hold
High
COUT enable
COUT delay
COUT hold
COUT tristate
Comments
Min
Max
Unit
40
10
60
ms
%
10
ns
ns
MHz
MCLK and LRCLK input
See Figure 5
CCLK high
CCLK low
CCLK frequency
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
AAUXDATA setup
AAUXDATA hold
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
35
35
fCCLK = 1/tCCP; only tCCP shown in Figure 5
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK falling
Not shown in Figure 5
From CCLK falling
From CCLK falling
From CCLK falling, not shown in Figure 5
From CCLK falling
See Figure 13
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
See Figure 12
To AUXBCLK rising
From AUXBCLK rising
To AUXBCLK rising
From AUXBCLK rising
Rev. 0 | Page 6 of 24
10
10
10
10
10
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
+8
18
ns
ns
ns
ns
ns
ns
30
30
30
10
10
10
5
−8
10
5
10
10
10
5
ns
ns
ns
ns
ns
ns
AD1974
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Analog (AVDD)
Digital (DVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
THERMAL RESISTANCE
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
±20 mA
–0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
θJA represents thermal resistance, junction-to-ambient; θJC
represents the thermal resistance, junction-to-case. All
characteristics are for a 4-layer board.
Table 9.
Package Type
48-Lead LQFP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 24
θJA
50.1
θJC
17
Unit
°C/W
AD1974
LF
ADC2RN
ADC2RP
ADC2LN
ADC2LP
ADC1RN
ADC1RP
ADC1LN
ADC1LP
CM
AVDD
48
47
46
45
44
43
42
41
40
39
38
37
AGND
1
36
AGND
MCLKI/XI
2
35
FILTR
MCLKO/XO
3
34
AGND
AGND
4
33
AVDD
AVDD
5
AD1974
32
AGND
NC
6
31
NC
NC
TOP VIEW
(Not to Scale)
7
30
NC
NC
8
29
NC
NC
9
28
NC
PD/RST 10
27
CLATCH
NC 11
26
CCLK
DGND 12
25
DGND
18
19
20
21
22
23
24
ASDATA1
ABCLK
ALRCLK
CIN
COUT
NC
17
ASDATA2
16
AUXLRCLK
15
AUXBCLK
14
AUXDATA1
DVDD
13
AUXDATA2
SINGLE-ENDED
OUTPUT
NC = NO CONNECT
06614-020
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. AD1974 Single-Ended Output, 48-Lead LQFP Pin Configuration
Table 10. Pin Function Description
Pin No.
1, 4, 32, 34, 36
2
3
5, 33, 37, 48
6 to 9, 11, 16, 28 to 31
10
12, 25
13
14
15
17
18
19
20
21
22
23
24
26
27
35
38
39
40
41
42
43
Type1
I
I
O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I
I/O
I
I
O
O
I
I
I
I
I
Mnemonic
AGND
MCLKI/XI
MCLKO/XO
AVDD
NC
PD/RST
DGND
DVDD
AUXDATA2
AUXDATA1
AUXBCLK
AUXLRCLK
ASDATA2
ASDATA1
ABCLK
ALRCLK
CIN
COUT
CCLK
CLATCH
FILTR
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Power Supply. Connect to analog 3.3 V supply.
No Connect.
Power-Down/Reset (Active Low).
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
Auxiliary Data Input 2 (From External ADC 2).
Auxiliary Data Input 1 (From External ADC 1).
Auxiliary Bit Clock.
Auxiliary Left-Right Framing Clock.
ADC Serial Data Output 2 (ADC 2 Left and ADC 2 Right)/ADC TDM Data Input.
ADC Serial Data Output 1 (ADC 1 Left and ADC 1 Right)/ADC TDM Data Output.
Serial Bit Clock for ADCs.
Left-Right Framing Clock for ADCs.
Control Data Input (SPI).
Control Data Output (SPI).
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
Rev. 0 | Page 8 of 24
AD1974
Pin No.
44
45
46
47
1
Type1
I
I
I
O
Mnemonic
ADC2LN
ADC2RP
ADC2RN
LF
Description
ADC2 Left Negative Input.
ADC2 Right Positive Input.
ADC2 Right Negative Input.
PLL Loop Filter, Return to AVDD.
I = input, O = output.
Rev. 0 | Page 9 of 24
AD1974
0
0.08
–10
0.06
–20
0.04
–30
0.02
0
–0.02
–40
–50
–60
–0.04
–70
–0.06
–80
–0.08
–90
–0.10
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
FREQUENCY (kHz)
–100
0
5000 10000 15000 20000 25000 30000 35000 40000
FREQUENCY (kHz)
Figure 4. ADC Stop-Band Filter Response, 48 kHz
Figure 3. ADC Pass-Band Filter Response, 48 kHz
Rev. 0 | Page 10 of 24
06614-003
MAGNITUDE (dB)
0.10
06614-002
MAGNITUDE (dB)
TYPICAL PERFORMANCE CHARACTERISTICS
AD1974
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
There are four ADC channels in the AD1974 configured as two
stereo pairs with differential inputs. The ADCs can operate at a
nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs
include on-board digital antialiasing filters with a 79 dB stopband attenuation and a linear phase response, operating at
an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz
modes). Digital outputs are supplied through two serial data
output pins (one for each stereo pair) as well as a common
frame (ALRCLK) and bit clock (ABCLK). Alternatively, one
of the time division multiplexed (TDM) modes can be used
to access up to 16 channels on a single TDM data line.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to internal switched capacitors. To isolate the external driving op amp
from the glitches caused by the internal switched capacitors,
each input pin should be isolated by using a series connected,
external, 100 Ω resistor together with a 1 nF capacitor connected
from each input to ground. This capacitor must be of high quality,
for instance, a ceramic NPO capacitor or a polypropylene film
capacitor.
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The inputs
can also be ac-coupled and do not need an external dc bias to CM.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a 1.4 Hz,
6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency scales directly with sample frequency.
The voltage at CM can be used to bias the external op amps that
buffer the output signals (see the Power Supply and Voltage
Reference section).
CLOCK SIGNALS
The on-chip PLL can be selected to reference the input sample
rate from either the LRCLK or AUXLRCK pins or 256, 384, 512,
or 768 times the sample rate, referenced to the 48 kHz mode from
the MCLKI/XI pin. The default at power-up is 256 × fS from
MCLKI. In 96 kHz mode, the master clock frequency stays
at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual
multiplication rate is divided by 4. For example, if the AD1974
is programmed in 256 × fS mode, the frequency of the master
clock input is 256 × 48 kHz = 12.288 MHz. If the AD1974 is
then switched to 96 kHz operation (by writing to the SPI or
I2C port), the frequency of the master clock should remain at
12.288 MHz (128 × fS). In 192 kHz mode, this becomes 64 × fS.
The internal clock for the ADCs is 256 × fS for all clock modes.
By default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for the ADCs if selected in the
PLL and Clock Control 1 register.
Note that it is not possible to use a direct clock for the ADCs
set to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The PLL can be powered down in the PLL and Clock Control 0
register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock has
stabilized.
The internal MCLK can be disabled in the PLL and Clock Control
0 register to reduce power dissipation when the AD1974 is idle.
The clock should be stable before it is enabled. Unless a standalone mode is selected (see the Serial Control Port section), the
clock is disabled by reset and must be enabled by writing to the
SPI or I2C port for normal operation.
To maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal
be limited to less than 300 ps rms time interval error (TIE). Even
at these levels, extra noise or tones can appear in the outputs if
the jitter spectrum contains large spectral peaks. If the internal
PLL is not being used, it is highly recommended that an independent crystal oscillator generate the master clock. In addition,
it is especially important that the clock signal should not be
passed through an FPGA, CPLD, DSP, or other large digital
chip before being applied to the AD1974. In most cases, this
induces clock jitter due to the sharing of common power and
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
The reset pin sets all the control registers to their default settings.
To avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires a lock condition,
an initialization routine runs inside the AD1974. This initialization lasts for approximately 256 master clock cycles.
The PLL and Clock Control 0 register and the ADC Control 1
register power down their respective sections using power down
bits. All other register settings are retained. The PD/RST pin
should be pulled low by an external resistor to guarantee proper
startup.
Rev. 0 | Page 11 of 24
AD1974
Table 11. Standalone Mode Selection
ADC Clocks
Slave
Master
CIN
0
0
COUT
0
1
tCLS
CLATCH
0
0
tCLH
tCCH tCCL
tCCP
CLATCH
CCLK
0
0
tCOTS
CCLK
tCDS tCDH
COUT
D23
D22
D9
tCOE
D9
D8
D0
D8
D0
06614-010
CIN
tCOD
Figure 5. Format of the SPI Signal
SERIAL CONTROL PORT
The AD1974 has an SPI control port that permits the programming and reading back of the internal control registers for the
ADCs and the clock system. There is also a standalone mode
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal MCLK enable, which is set to 1;
ADC BCLK and LRCLK master/slave, which are set by COUT.
Standalone mode only supports stereo mode with an I2S data
format and 256 fS MCLK rate (see Table 11 for details). Using a
weak pull-up resistor in applications that have a microcontroller
is highly recommended. This pull-up resistor ensures that the
AD1974 recognizes the presence of a microcontroller.
The SPI control port of the AD1974 is a 4-wire serial control
port. The format is similar to that of the Motorola SPI® format
except that the input data-word is 24 bits wide. The serial bit
clock and latch can be completely asynchronous to the sample
rate of the ADCs. Figure 5 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1974, the address is 0x04, shifted left one bit due to the R/W
bit. The second byte is the AD1974 register address and the
third byte is the data.
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1974 is designed for 3.3 V supplies. Separate power
supply pins (Pin 5, Pin 13, Pin 33, Pin 37, and Pin 38) are provided for the analog and digital sections. These pins should be
bypassed with 100 nF ceramic chip capacitors, as close to the
pins as possible, to minimize noise pickup. A bulk aluminum
electrolytic capacitor of at least 22 μF should also be placed
on the same PC board as the codec. For critical applications,
improved performance is obtained with separate supplies for
the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by
means of a ferrite bead in series with each supply. It is
important that the analog supply be as clean as possible.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The ADC internal voltage reference (VREF) is brought out
on FILTR and should be bypassed as close as possible to the
AD1974 with a parallel combination of 10 μF and 100 nF. Any
external current drawn should be limited to less than 50 μA.
VREF can be disabled in the PLL and Clock Control 1 register
and FILTR can be driven from an external source. The ADC
input gain varies by the inverse ratio.
CM is the internal common-mode reference. It should be
bypassed as close as possible to the AD1974, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The four ADC channels use a common serial bit clock (ABCLK)
and a left-right framing clock (ALRCLK) in the serial data port.
The clock signals are all synchronous with the sample rate. The
normal stereo serial modes are shown in Figure 11.
The ADC serial data modes default to I2S. The ports can also be
programmed for left justified, right justified, and TDM modes.
The word width is 24 bits by default and can be programmed
for 16 or 20 bits. The ADC serial formats and serial clock polarity
are programmable according to the ADC Control 1 register.
The ADC serial ports are programmable to become the bus
masters according to the ADC Control 2 register. By default,
both ADC serial ports are in the slave mode.
Rev. 0 | Page 12 of 24
AD1974
The AD1974 serial ports also have several different TDM serial
data modes. The first and most commonly used configuration
is shown in Figure 6 where the ADC serial port outputs one
data stream consisting of four on-chip ADCs followed by four
unused slots. In this mode, ABCLK is set to 256 fS (8-channel
TDM mode).
put stream follow four on-chip ADC channel slots. It should be
noted that due to the high ABCLK frequency, this mode is
available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
ALRCLK
256 BCLKs
ABCLK
32 BCLKs
ADATA
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2 UNUSED UNUSED UNUSED UNUSED
The I/O pins of the serial ports are defined according to the
serial mode selected. For a detailed description of the function
of each pin in TDM and AUX Modes, see Table 12.
ALRCLK
ABCLK
MSB
The AD1974 allows system configurations with more than four
ADC channels (see Figure 7 and Figure 8) that use 8 ADCs and
16 ADCs. In this mode, four AUX channel slots in the TDM out-
MSB–1
MSB–2
06614-016
TDM MODES
ADATA
Figure 6. ADC TDM (8-Channel I2S Mode.
Table 12. Pin Function Changes in TDM and AUX Modes
Pin Name
ASDATA1
ASDATA2
AUXDATA1
AUXDATA2
ALRCLK
ABCLK
AUXLRCLK
AUXBCLK
Stereo Mode
ADC1 data output
ADC2 data output
Not used (ground)
Not used (ground)
ADC LRCLK input/output
ADC BCLK input/output
Not used (ground)
Not used (ground)
TDM Mode
ADC TDM data output
ADC TDM data input
Not used (ground)
Not used (ground)
ADC TDM frame sync input/output
ADC TDM BCLK input/output
Not used (ground)
Not used (ground)
AUX Mode
ADCTDM data output
Not used (float)
AUXDATA in 1 (from external ADC1)
AUXDATA in 2 (from external ADC2)
ADCTDM frame sync input/output
ADCTDM BCLK input/output
AUXLRCLK input/output
AUXBCLK input/output
ALRCLK
ABCLK
FOUR-AUX ADC CHANNELS
FOUR-ON-CHIP DAC CHANNELS
ASDATA1
(TDM_OUT)
ADCL1
ADCR1
ADCL2
ADCR2
AUXL1
AUXR1
AUXL2
AUXR2
32 BITS
MSB
AUXLRCLK
(AUX PORT)
LEFT
RIGHT
AUXDATA1
(AUX1_IN)
MSB
MSB
AUXDATA2
(AUX2_IN)
MSB
MSB
Figure 7. 8-Channel AUX ADC Mode
Rev. 0 | Page 13 of 24
06614-050
AUXBCLK
(AUX PORT)
AD1974
ALRCLK
ABCLK
ASDATA1
(TDM_OUT)
FOUR-ON-CHIP
ADC CHANNELS
ADCL1
ADCR1
ADCL2
AUXILIARY ADC CHANNELS
ADCR2
AUXL1
AUXR1
AUXL2
UNUSED SLOTS
AUXR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
32 BITS
MSB
AUXLRCLK
(AUX PORT)
LEFT
RIGHT
AUXDATA1
(AUX1_IN)
MSB
MSB
AUXDATA2
(AUX2_IN)
MSB
MSB
Figure 8. 16-Channel AUX ADC Mode
Rev. 0 | Page 14 of 24
06614-052
AUXBCLK
(AUX PORT)
AD1974
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 13 for a detailed description
of the function of each pin. See Figure 14 for a typical AD1974
configuration with two external stereo ADCs.
DAISY-CHAIN MODE
The AD1974 also allows a daisy-chain configuration to
expand the system to 8 ADCs and 16 ADCs (see Figure 9 and
Figure 10). There are two configurations for the ADC port to
work in daisy-chain mode. The first one is with an ABCLK at
256 fS shown in Figure 9. The second configuration is with an
ABCLK at 512 fS shown in Figure 10. Note that in the 512 fS
ABCLK mode, the ADC channels occupy the first eight slots,
the second eight slots are empty. The TDM_IN of the first
AD1974 must be grounded in all modes of operation. The
second AD1974 is the device attached to the DSP TDM port.
Figure 11 through Figure 13 show the serial mode formats.
For maximum flexibility, the polarity of LRCLK and BCLK
are programmable. All of the clocks are shown with their
normal polarity. The default mode is I2S.
ALRCLK
ABCLK
ASDATA1 (TDM_OUT
OF THE SECOND AD1974
IN THE CHAIN)
ASDATA2 (TDM_IN
OF THE SECOND AD1974
IN THE CHAIN)
FOUR ADC CHANNELS OF THE SECOND IC IN THE CHAIN
ADCL1
ADCR1
ADCL2
ADCR2
ADCL1
ADCR1
ADCL2
ADCR2
FOUR ADC CHANNELS OF THE FIRST IC IN THE CHAIN
ADCL1
ADCR1
ADCL2
ADCR2
32 BITS
SECOND
AD1974
DSP
MSB
06614-056
FIRST
AD1974
Figure 9. ADC TDM Daisy-Chain Mode (256 fS ABCLK, Two AD1974 Daisy Chains)
ALRCLK
ABCLK
ASDATA1 (TDM_OUT
OF THE SECOND AD1974
IN THE CHAIN)
ASDATA2 (TDM_IN
OF THE SECOND AD1974
IN THE CHAIN)
FOUR ADC CHANNELS OF
THE SECOND IC IN THE CHAIN
FOUR ADC CHANNELS OF
THE FIRST IC IN THE CHAIN
ADCL1
ADCR1
ADCL2
ADCR2
ADCL1
ADCR1
ADCL2
ADCR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
ADCL1
ADCR1
ADCL2
ADCR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
FIRST
AD1974
SECOND
AD1974
DSP
MSB
Figure 10. ADC TDM Daisy-Chain Mode (512 fS ABCLK, Two AD1974 Daisy Chains)
Rev. 0 | Page 15 of 24
06614-057
32 BITS
AD1974
LEFT CHANNEL
ALRCLK
RIGHT CHANNEL
ABCLK
ASDATA
MSB
MSB
LSB
LSB
LEFT JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
ALRCLK
RIGHT CHANNEL
ABCLK
ASDATA
LSB
MSB
LSB
MSB
I2S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
ALRCLK
RIGHT CHANNEL
ABCLK
ASDATA
LSB
MSB
LSB
MSB
RIGHT JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
ALRCLK
ABCLK
MSB
ASDATA
MSB
LSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
06614-013
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 11. Stereo Serial Modes
tXBH
AUXBCLK
tXBL
tXLH
tXLS
AUXRCLK
tXDS
AUXDATA
LEFT JUSTIFIED
MODE
MSB
MSB–1
tXDH
AUXDATA
I2C JUSTIFIED
MODE
tXDS
MSB
tXDH
tXDS
MSB
LSB
tXDH
Figure 12. Auxiliary Serial Timing
Rev. 0 | Page 16 of 24
tXDH
06614-014
tXDS
AUXDATA
RIGHT JUSTIFIED
MODE
AD1974
tABH
ABCLK
tABL
tALH
tALS
ALRCLK
tABDD
ASDATA
LEFT JUSTIFIED
MODE
MSB
MSB–1
tABDD
ASDATA
I2C JUSTIFIED
MODE
MSB
ASDATA
RIGHT JUSTIFIED
MODE
MSB
LSB
06614-015
tABDD
Figure 13. ADC Serial Timing
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)
Stereo Mode
ADC1 data output
ADC2 data output
Not used (ground)
Not used (ground)
ADC LRCLK input/output
ADC BCLK input/output
Not used (ground)
Not used (ground)
TDM Mode
ADC TDM data output
ADC TDM data input
Not used (ground)
Not used (ground)
ADC TDM Frame Sync input/output
ADC TDM BCLK input/output
Not used (ground)
Not used (ground)
TxCLK
TFS (NC)
RxDATA
SHARC
RxCLK
12.288MHz
AUX Mode
ADCTDM data output
Not used (float)
AUXDATA in 1 (from external ADC1)
AUXDATA in 2 (from external ADC2)
ADCTDM frame sync input/output
ADCTDM BCLK input/output
AUXLRCLK input/output
AUXBCLK input/output
SHARC IS RUNNING
IN SLAVE MODE
(INTERRUPT-DRIVEN)
30MHz
FSYNC-TDM (RFS)
LRCLK
AUX
ADC 1
BCLK
DATA
ASDATA1 ALRCLK ABCLK
MCLK
AUXBCLK
AUXLRCLK
AD1974
BCLK
AUXDATA1
DATA
AUXDATA2
TDM MASTER
AUX MASTER
MCLK
MCLK
LRCLK
AUX
ADC 2
06614-019
Pin Name
ASDATA1
ASDATA2
AUXDATA1
AUXDATA2
ALRCLK
ABCLK
AUXLRCLK
AUXBCLK
Figure 14. Example of AUX Mode Connection to SHARC® (AD1974 as TDM Master/AUX Master Shown)
Rev. 0 | Page 17 of 24
AD1974
CONTROL REGISTERS
The format is the same for I2C and SPI ports. The global address for the AD1974 is 0x04, shifted left one bit due to the R/W bit. All
registers are reset to 0.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Bit
Global Address
R/W
Register Address
Data
23:17
16
15:8
7:0
Table 15. Register Addresses Description
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
PLL and Clock Control 0
PLL and Clock Control 1
AUXPORT Control 0
AUXPORT Control 1
AUXPORT Control 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADC Control 0
ADC Control 1
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0
Bit
0
2:1
4:3
6:5
7
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
Normal operation
Power-down
INPUT 256 (×44.1 kHz or 48 kHz)
INPUT 384 (×44.1 kHz or 48 kHz)
INPUT 512 (×44.1 kHz or 48 kHz)
INPUT 768 (×44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × fS VCO output
512 × fS VCO output
Off
MCLKI/XI
AUXLRCLK
ALRCLK
Reserved
Disable: ADC idle
Enable: ADC active
Description
PLL power-down
MCLKI/XI pin functionality (PLL active), master clock rate setting
MCLKO/XO pin, master clock rate setting
PLL input
Internal MCLK enable
Rev. 0 | Page 18 of 24
AD1974
Table 17. PLL and Clock Control 1
Bit
0
1
2
3
7:4
Value
0
1
0
1
0
1
0
1
0000
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Description
AUXPORT clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read only)
AUXPORT CONTROL REGISTERS
Table 18. AUXPORT Control 0
Bit
0
2:1
5:3
7:6
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Function
Reserved
Reserved
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
Reserved
ADC AUX mode (ADC-, TDM-coupled)
Reserved
Description
Reserved
Sample rate
AUXDATA delay (AUXBCLK periods)
Serial format
Table 19. AUXPORT Control 1
Bit
0
2:1
3
4
5
6
7
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
Reserved
Reserved
64 (two channels)
Reserved
Reserved
Reserved
Left low
Left high
Slave
Master
Slave
Master
AUXBCLK pin
Internally generated
Normal
Inverted
Description
AUXBCLKs per frame
AUXLRCLK polarity
AUXLRCLK master/slave
AUXBCLK master/slave
AUXBCLK source
AUXBCLK polarity
Rev. 0 | Page 19 of 24
AD1974
Table 20. AUXPORT Control 2
Bit
0
2:1
4:3
5
7:6
Value
0
1
00
01
10
11
00
01
10
11
0
1
00
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
24
20
Reserved
16
Reserved
Reserved
Reserved
Description
Word width
ADC CONTROL REGISTERS
Table 21. ADC Control 0
Bit
0
1
2
3
4
5
7:6
Value
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
Function
Normal
Power down
Off
On
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
Description
Power-down
High-pass filter
ADC1L mute
ADC1R mute
ADC2L mute
ADC2R mute
Output sample rate
Table 22. ADC Control 1
Bit
1:0
4:2
Value
00
01
10
11
000
001
010
011
100
101
110
111
Function
24
20
Reserved
16
1
0
8
12
16
Reserved
Reserved
Reserved
Description
Word width
SDATA delay (BCLK periods)
Rev. 0 | Page 20 of 24
AD1974
Bit
6:5
7
Value
00
01
10
11
0
1
Function
Stereo
TDM (daisy chain)
ADC AUX mode (TDM-coupled)
Reserved
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
Description
Serial format
BCLK active edge (TDM_IN)
Table 23. ADC Control 2
Bit
0
1
2
3
5:4
6
7
Value
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
Function
50/50 (allows 32-/24-/20-/16-BCLK per channel)
Pulse (32-BCLK/channel)
Drive out on falling edge (DEF)
Drive out on rising edge
Left low
Left high
Slave
Master
64
128
256
512
Slave
Master
ABCLK pin
Internally generated
Rev. 0 | Page 21 of 24
Description
LRCLK format
BCLK polarity
LRCLK polarity
LRCLK master/slave
BCLKs per frame
BCLK master/slave
BCLK source
AD1974
ADDITIONAL MODES
The AD1974 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 15 for an example of an ADC TDM data transmission
mode that does not require high speed ABCLK. This configuration is applicable when the AD1974 master clock is generated
by the PLL with the ALRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1974 in
cases of high speed TDM data transmission, the AD1974 can
latch in the data using the falling edge of ABCLK. This effectively dedicates the entire BCLK period to the setup time. This
mode is useful in cases where the source has a large delay time
in the serial data driver. Figure 16 shows this pipeline mode of
data transmission.
ALRCLK
32 BITS
INTERNAL
ABCLK
ASDATA2
ALRCLK
06614-059
INTERNAL
ABCLK
ASDATA2
Figure 15. Serial ADC Data Transmission in TDM Format Without ABCLK
(Applicable Only If PLL Locks to ALRCLK)
ALRCLK
ABCLK
ASDATA1
06614-060
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
Figure 16. I2S Pipeline Mode in ADC Serial Data Transmission
(Applicable in Stereo and TDM Useful for High Frequency TDM Transmission)
Rev. 0 | Page 22 of 24
AD1974
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 17 and Figure 18. Figure 17 shows a typical ADC input filter circuit. Recommended loop
filters for LR clock and master clock as the PLL reference are shown in Figure 18.
120pF
100pF
5.76kΩ
2
3
+
–
OP275
+
4.7µF 237Ω
+
120pF
1nF
NPO
–
OP275
+
5.6nF
390pF
7
1nF
NPO
4.7µF 237Ω
+
ADCxP
562Ω
AVDD2
Figure 18. Recommended Loop Filters for LRCLK or MCLK PLL Reference
ADCxN
100pF
5.76kΩ
MCLK
2.2nF
3.32kΩ
5.76kΩ
5
LF
39nF
1
AVDD2
6
LRCLK
LF
5.76kΩ
06614-027
600Z
06614-023
AUDIO
INPUT
Figure 17. Typical ADC Input Filter Circuit
Rev. 0 | Page 23 of 24
AD1974
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
24
0.27
0.22
0.17
051706-A
0.75
0.60
0.45
Figure 19. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1974YSTZ 1, 2
AD1974YSTZ-RL1, 2
EVAL-AD1974EB
EVAl-AD1974EBZ1
1
2
Temperature Range
–40°C to +105°C
–40°C to +105°C
Package Description
48-Lead LQFP
48-Lead LQFP, 13” Reel
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Single-ended output; SPI control port.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06614-0-4/07(0)
Rev. 0 | Page 24 of 24
Package Option
ST-48
ST-48
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