Cypress CY8C24123A-24PXI Psoc mixed-signal array Datasheet

PSoC™ Mixed-Signal Array
Final Data Sheet
CY8C24123A,
CY8C24223A, and CY8C24423A
Features
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 2.4 to 5.25 V Operating Voltage
❐ Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ 4K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Advanced Peripherals (PSoC Blocks)
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 10 Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Port 2 Port 1 Port 0
System Bus
SRAM
256 Bytes
Global Analog Interconnect
SROM
Flash 4K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Clocks
Analog
Block
Array
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
Multiply
Accum.
POR and LVD
Decimator
I2C
System Resets
SYSTEM RESOURCES
September 8, 2004
Analog
Ref
Analog
Input
Muxing
Internal
Voltage
Ref.
❐ I2C™ Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C24x23A family can have up to three IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 6 analog blocks.
ANALOG SYSTEM
Digital
Block
Array
■ Additional System Resources
PSoC™ Functional Overview
Analog
Drivers
PSoC CORE
Global Digital Interconnect
■ New CY8C24x23A PSoC Device
❐ Derived from the CY8C24x23 Device
❐ Low Power and Low Voltage (2.4V)
The PSoC Core
Switch
Mode
Pump
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12028 Rev. *B
1
CY8C24x23A Final Data Sheet
PSoC™ Overview
processor. The CPU utilizes an interrupt controller with 11 vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 4 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Digital peripheral configurations include those listed below.
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 24 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity
■
SPI master and slave
■
I2C slave and multi-master (1 available as a System
Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 1)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Characteristics” on page 3.
The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific application requirements.
Some of the more common PSoC analog functions (most available as user modules) are listed below.
■
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
DIGITAL SYSTEM
■
DACs (up to 2, with 6- to 9-bit resolution)
Digital PSoC Block Array
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Port 1
Port 2
Port 0
To System Bus
8
Row 0
DBB00
DBB01
DCB02
To Analog
System
4
Row Output
Configuration
8
Row Input
Configuration
Digital Clocks
From Core
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
8
GOE[7:0]
GOO[7:0]
Digital System Block Diagram
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CY8C24x23A Final Data Sheet
PSoC™ Overview
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks, as shown in the figure below.
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
P0[7]
P2[3]
P2[1]
P2[6]
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.
■
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASC10
ASD11
ASD20
ASC21
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is shown in the next to the last row of
the table.
Analog Columns
Analog Blocks
Amount of SRAM
Amount of Flash
PSoC Device Characteristics
Analog Outputs
M8C Interface (Address Bus, Data Bus, Etc.)
AGNDIn
RefIn
Bandgap
Analog Inputs
Reference
Generators
Digital Blocks
RefHi
RefLo
AGND
Digital Rows
Interface to
Digital System
Digital IO (max)
Analog Reference
CY8C29x66
64
4
16
12
4
4
12
2 KB
32 KB
CY8C27x43
44
2
8
12
4
4
12
256 Bytes
16 KB
CY8C24x23
24
1
4
12
2
2
6
256 Bytes
4 KB
PSoC Device
Group
Analog System Block Diagram
CY8C24x23A
24
1
4
12
2
2
6
256 Bytes
4 KB
CY8C22x13
16
1
4
8
1
1
3
256 Bytes
2 KB
CY8C21x34
28
1
4
28
0
2
4a
512 Bytes
8 KB
CY8C21x23
16
1
4
8
0
2
4a
256 Bytes
4 KB
a. Limited analog functionality.
September 8, 2004
Document No. 38-12028 Rev. *B
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CY8C24x23A Final Data Sheet
PSoC™ Overview
Getting Started
Development Tools
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
The Cypress MicroSystems PSoC Designer is a Microsoft®
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Tele-Training
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
PSoCTM
Designer
Importable
Design
Database
Device
Database
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Context
Sensitive
Help
Graphical Designer
Interface
Results
Free PSoC "Tele-training" is available for beginners and taught
by a live marketing or application engineer over the phone. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
Commands
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
PSoC
Configuration
Sheet
PSoCTM
Designer
Core
Engine
Application
Database
Manufacturing
Information
File
Project
Database
User
Modules
Library
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
PSoC Designer Subsystems
September 8, 2004
Document No. 38-12028 Rev. *B
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CY8C24x23A Final Data Sheet
PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
Debugger
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
Design Browser
The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
September 8, 2004
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CY8C24x23A Final Data Sheet
PSoC™ Overview
User Module Development Process
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
Device Editor
User
Module
Selection
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
September 8, 2004
Source
Code
Generator
Generate
Application
Application Editor
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides highlevel functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service routines that you can adapt as needed.
Placement
and
Parameterization
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Document No. 38-12028 Rev. *B
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CY8C24x23A Final Data Sheet
PSoC™ Overview
Document Conventions
Table of Contents
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed Signal Array Technical Reference Manual. This document encompasses and is organized
into the following chapters and sections.
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC™
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SLIMO
slow IMO
SMP
switch mode pump
SRAM
static random access memory
1.
Pin Information ............................................................. 8
1.1 Pinouts ................................................................... 8
1.1.1 8-Pin Part Pinout ........................................ 8
1.1.2 20-Pin Part Pinout ...................................... 9
1.1.3 28-Pin Part Pinout .................................... 10
1.1.4 32-Pin Part Pinout .................................... 11
2.
Register Reference ..................................................... 12
2.1 Register Conventions ........................................... 12
2.1.1 Abbreviations Used .................................. 12
2.2 Register Mapping Tables ..................................... 12
3.
Electrical Specifications ............................................ 15
3.1 Absolute Maximum Ratings ................................ 16
3.2 Operating Temperature ....................................... 16
3.3 DC Electrical Characteristics ................................ 17
3.3.1 DC Chip-Level Specifications ................... 17
3.3.2 DC General Purpose IO Specifications .... 18
3.3.3 DC Operational Amplifier Specifications ... 19
3.3.4 DC Analog Output Buffer Specifications ... 22
3.3.5 DC Switch Mode Pump Specifications ..... 24
3.3.6 DC Analog Reference Specifications ....... 25
3.3.7 DC Analog PSoC Block Specifications ..... 26
3.3.8 DC POR, SMP, and LVD Specifications ... 27
3.3.9 DC Programming Specifications ............... 28
3.4 AC Electrical Characteristics ................................ 29
3.4.1 AC Chip-Level Specifications ................... 29
3.4.2 AC General Purpose IO Specifications .... 32
3.4.3 AC Operational Amplifier Specifications ... 33
3.4.4 AC Digital Block Specifications ................. 34
3.4.5 AC Analog Output Buffer Specifications ... 36
3.4.6 AC External Clock Specifications ............. 37
3.4.7 AC Programming Specifications ............... 38
3.4.8 AC I2C Specifications ............................... 39
4.
Packaging Information ............................................... 40
4.1 Packaging Dimensions ......................................... 40
4.2 Thermal Impedances .......................................... 45
4.3 Capacitance on Crystal Pins ............................... 45
5.
Ordering Information .................................................. 46
5.1 Ordering Code Definitions .................................... 46
6.
Sales and Company Information ............................... 47
6.1 Revision History ................................................... 47
6.2 Copyrights and Code Protection .......................... 47
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 15 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
September 8, 2004
Document No. 38-12028 Rev. *B
7
1. Pin Information
This chapter describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1
8-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (PDIP, SOIC)
Pin
No.
Type
Pin
Name
Description
Digital
Analog
1
IO
IO
P0[5]
Analog column mux input and column output.
2
IO
IO
P0[3]
Analog column mux input and column output.
3
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL)
Vss
Ground connection.
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA)
4
Power
5
IO
6
IO
I
P0[2]
Analog column mux input.
7
IO
I
P0[4]
Analog column mux input.
Vdd
Supply voltage.
8
Power
CY8C24123A 8-Pin PSoC Device
AIO, P0[5]
AIO, P0[3]
I2C SCL, XTALin, P1[1]
Vss
8
1
2 PDIP7
3SOIC6
5
4
Vdd
P0[4], AI
P0[2], AI
P1[0], XTALout, I2C SDA
LEGEND: A = Analog, I = Input, and O = Output.
September 8, 2004
Document No. 38-12028 Rev. *B
8
CY8C24x23A Final Data Sheet
1.1.2
1. Pin Information
20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
Type
Digital
Analog
Pin
Name
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column output.
3
IO
IO
P0[3]
Analog column mux input and column output.
4
IO
I
P0[1]
Analog column mux input.
SMP
Switch Mode Pump (SMP) connection to
external components required.
5
Power
6
IO
P1[7]
I2C Serial Clock (SCL)
7
IO
P1[5]
I2C Serial Data (SDA)
8
IO
P1[3]
9
IO
10
Power
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL)
Vss
Ground connection.
Crystal Output (XTALout), I2C Serial Data
(SDA)
11
IO
P1[0]
12
IO
P1[2]
13
IO
P1[4]
14
IO
P1[6]
15
Input
XRES
Active high external reset with internal pull
down.
IO
I
P0[0]
Analog column mux input.
17
IO
I
P0[2]
Analog column mux input.
18
IO
I
P0[4]
Analog column mux input.
19
IO
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
Power
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
PDIP
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional External Clock Input (EXTCLK)
16
20
CY8C24223A 20-Pin PSoC Device
Description
LEGEND: A = Analog, I = Input, and O = Output.
September 8, 2004
Document No. 38-12028 Rev. *B
9
CY8C24x23A Final Data Sheet
1.1.3
1. Pin Information
28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
Type
Digital
Analog
Pin
Name
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column output.
3
IO
IO
P0[3]
Analog column mux input and column output.
4
IO
I
P0[1]
Analog column mux input.
5
IO
6
IO
7
IO
8
IO
9
P2[7]
P2[5]
I
P2[3]
I
P2[1]
Direct switched capacitor block input.
SMP
Switch Mode Pump (SMP) connection to
external components required.
Power
Direct switched capacitor block input.
10
IO
P1[7]
I2C Serial Clock (SCL)
11
IO
P1[5]
I2C Serial Data (SDA)
12
IO
P1[3]
13
IO
14
Power
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL)
Vss
Ground connection.
Crystal Output (XTALout), I2C Serial Data
(SDA)
15
IO
P1[0]
16
IO
P1[2]
17
IO
P1[4]
18
IO
P1[6]
19
Input
XRES
Active high external reset with internal pull
down.
Direct switched capacitor block input.
IO
I
P2[0]
21
IO
I
P2[2]
Direct switched capacitor block input.
22
IO
P2[4]
External Analog Ground (AGND)
23
IO
P2[6]
External Voltage Reference (VRef)
24
IO
I
P0[0]
Analog column mux input.
25
IO
I
P0[2]
Analog column mux input.
26
IO
I
P0[4]
Analog column mux input.
27
IO
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
Power
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional External Clock Input (EXTCLK)
20
28
CY8C24423A 28-Pin PSoC Device
Description
LEGEND: A = Analog, I = Input, and O = Output.
September 8, 2004
Document No. 38-12028 Rev. *B
10
CY8C24x23A Final Data Sheet
1.1.4
1. Pin Information
32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
Pin
Name
1
IO
2
IO
3
IO
I
P2[3]
4
IO
I
P2[1]
P2[7]
Direct switched capacitor block input.
P2[5]
Power
Vss
Ground connection.
6
Power
SMP
Switch Mode Pump (SMP) connection to
external components required.
7
IO
P1[7]
I2C Serial Clock (SCL)
8
IO
P1[5]
I2C Serial Data (SDA)
NC
No connection. Do not use.
9
IO
11
IO
12
P1[3]
Power
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL)
Vss
Ground connection.
Crystal Output (XTALout), I2C Serial Data
(SDA)
13
IO
P1[0]
14
IO
P1[2]
15
IO
P1[4]
Optional External Clock Input (EXTCLK)
NC
No connection. Do not use.
16
17
IO
18
P1[6]
Input
XRES
Active high external reset with internal pull
down.
Direct switched capacitor block input.
19
IO
I
P2[0]
20
IO
I
P2[2]
Direct switched capacitor block input.
21
IO
P2[4]
External Analog Ground (AGND)
22
IO
P2[6]
External Voltage Reference (VRef)
23
IO
I
P0[0]
Analog column mux input.
24
IO
I
P0[2]
Analog column mux input.
NC
No connection. Do not use.
Analog column mux input.
25
26
IO
I
P0[4]
27
IO
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
28
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
Vss
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
Power
29
IO
I
P0[7]
Analog column mux input.
30
IO
IO
P0[5]
Analog column mux input and column output.
31
IO
IO
P0[3]
Analog column mux input and column output.
32
IO
I
P0[1]
Analog column mux input.
32
31
30
29
28
27
26
25
Direct switched capacitor block input.
5
10
CY8C24423A 32-Pin PSoC Device
Description
P0[1], AI
P0[3], AIO
P0[5], AIO
P0[7], AI
Vdd
P0[6], AI
P0[4], AI
NC
Analog
1
2
3
4
5
6
7
8
MLF
(Top View)
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
Type
Digital
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
NC
P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
NC
Pin
No.
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
September 8, 2004
Document No. 38-12028 Rev. *B
11
2. Register Reference
This chapter lists the registers of the CY8C24x23A PSoC device. For detailed register information, reference the PSoC™ Mixed Signal Array Technical Reference Manual.
2.1
2.1.1
Register Conventions
2.2
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
September 8, 2004
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Document No. 38-12028 Rev. *B
12
CY8C24x23A Final Data Sheet
2. Register Reference
Register Map Bank 0 Table: User Space
RW
RW
RW
RW
RW
RW
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Document No. 38-12028 Rev. *B
Access
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(0,Hex)
Name
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
September 8, 2004
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr
(0,Hex)
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
4C
0D
4D
0E
4E
0F
4F
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBB00DR0
20
#
AMX_IN
60
RW
DBB00DR1
21
W
61
DBB00DR2
22
RW
62
DBB00CR0
23
#
ARF_CR
63
RW
DBB01DR0
24
#
CMP_CR0
64
#
DBB01DR1
25
W
ASY_CR
65
#
DBB01DR2
26
RW
CMP_CR1
66
RW
DBB01CR0
27
#
67
DCB02DR0
28
#
68
DCB02DR1
29
W
69
DCB02DR2
2A
RW
6A
DCB02CR0
2B
#
6B
DCB03DR0
2C
#
6C
DCB03DR1
2D
W
6D
DCB03DR2
2E
RW
6E
DCB03CR0
2F
#
6F
30
ACB00CR3
70
RW
31
ACB00CR0
71
RW
32
ACB00CR1
72
RW
33
ACB00CR2
73
RW
34
ACB01CR3
74
RW
35
ACB01CR0
75
RW
36
ACB01CR1
76
RW
37
ACB01CR2
77
RW
38
78
39
79
3A
7A
3B
7B
3C
7C
3D
7D
3E
7E
3F
7F
Blank fields are Reserved and should not be accessed.
Name
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
13
CY8C24x23A Final Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
GDI_O_IN
D0
GDI_E_IN
D1
GDI_O_OU
D2
GDI_E_OU
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
OSC_GO_EN DD
OSC_CR4
DE
OSC_CR3
DF
OSC_CR0
E0
OSC_CR1
E1
OSC_CR2
E2
VLT_CR
E3
VLT_CMP
E4
E5
E6
E7
IMO_TR
E8
ILO_TR
E9
BDG_TR
EA
ECO_TR
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
CPU_F
F7
F8
F9
FA
FB
FC
FD
CPU_SCR1
FE
CPU_SCR0
FF
Document No. 38-12028 Rev. *B
Access
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
Name
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
September 8, 2004
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr
(1,Hex)
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
4C
0D
4D
0E
4E
0F
4F
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBB00FN
20
RW
CLK_CR0
60
RW
DBB00IN
21
RW
CLK_CR1
61
RW
DBB00OU
22
RW
ABF_CR0
62
RW
23
AMD_CR0
63
RW
DBB01FN
24
RW
64
DBB01IN
25
RW
65
DBB01OU
26
RW
AMD_CR1
66
RW
27
ALT_CR0
67
RW
DCB02FN
28
RW
68
DCB02IN
29
RW
69
DCB02OU
2A
RW
6A
2B
6B
DCB03FN
2C
RW
6C
DCB03IN
2D
RW
6D
DCB03OU
2E
RW
6E
2F
6F
30
ACB00CR3
70
RW
31
ACB00CR0
71
RW
32
ACB00CR1
72
RW
33
ACB00CR2
73
RW
34
ACB01CR3
74
RW
35
ACB01CR0
75
RW
36
ACB01CR1
76
RW
37
ACB01CR2
77
RW
38
78
39
79
3A
7A
3B
7B
3C
7C
3D
7D
3E
7E
3F
7F
Blank fields are Reserved and should not be accessed.
Name
Access
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
#
#
14
3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Refer to Table 3-20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
5.25
SLIMO Mode = 0
5.25
SLIMO
Mode=1
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
pe io
O Reg
4.75
3.60
3.00
3.00
2.40
2.40
93 kHz
12 MHz
3 MHz
SLIMO
Mode=0
SLIMO
SLIMO
Mode=1
Mode=0
SLIMO SLIMO
Mode=1 Mode=1
93 kHz
24 MHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
Figure 3-1a. Voltage versus CPU Frequency
Figure 3-1b. IMO Frequency Trim Options
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
oC
degree Celsius
µW
micro watts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nano ampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
pico ampere
MΩ
megaohm
pF
pico farad
µA
micro ampere
pp
peak-to-peak
µF
micro farad
ppm
µH
micro henry
ps
picosecond
µs
microsecond
sps
samples per second
µV
micro volts
σ
sigma: one standard deviation
micro volts root-mean-square
V
volts
µVrms
September 8, 2004
parts per million
Document No. 38-12028 Rev. *B
15
CY8C24x23A Final Data Sheet
3.1
3. Electrical Specifications
Absolute Maximum Ratings
Table 3-2. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
–
+100
oC
TA
Ambient Temperature with Power Applied
-40
–
+85
o
Vdd
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss - 0.5
–
Vdd + 0.5
V
VIOZ
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5
V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
ESD
Electro Static Discharge Voltage
2000
–
–
V
LU
Latch-up Current
–
–
200
mA
3.2
Notes
Higher storage temperatures will reduce data
retention time.
C
Human Body Model ESD
Operating Temperature
Table 3-3. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
o
TJ
Junction Temperature
-40
–
+100
oC
September 8, 2004
Document No. 38-12028 Rev. *B
Notes
C
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 45. The user must limit the power consumption to comply with this requirement.
16
CY8C24x23A Final Data Sheet
3.3
3.3.1
3. Electrical Specifications
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
2.4
–
5.25
V
See DC POR and LVD specifications, Table 318 on page 27.
IDD
Supply Current
–
5
8
mA
Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.
IDD3
Supply Current
–
3.3
6.0
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.
IDD27
Supply Current when IMO = 6 MHz using SLIMO mode.
–
2
4
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU =
0.75 MHz, 48 MHz = Disabled, VC1 = 0.375
MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz, analog
power = off.
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT.a
–
3
6.5
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC, analog
power = off.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.a
–
4
25
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC, analog
power = off.
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal.a
–
4
7.5
µA
Conditions are with properly loaded, 1 µW max,
32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤ 55
oC,
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal at high temperature.a
–
5
26
µA
analog power = off.
Conditions are with properly loaded, 1µW max,
32.768 kHz crystal. Vdd = 3.3 V, 55 oC < TA ≤ 85
o
C, analog power = off.
VREF
Reference Voltage (Bandgap)
1.28
1.30
1.33
V
Trimmed for appropriate Vdd. Vdd > 3.0V.
VREF27
Reference Voltage (Bandgap)
1.16
1.30
1.33
V
Trimmed for appropriate Vdd. Vdd = 2.4V to
3.0V.
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions
enabled.
September 8, 2004
Document No. 38-12028 Rev. *B
17
CY8C24x23A Final Data Sheet
3.3.2
3. Electrical Specifications
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-5. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
kΩ
RPU
Pull up Resistor
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (maximum
40 mA on even port pins (for example, P0[2],
P1[4]), maximum 40 mA on odd port pins (for
example, P0[3], P1[5])). 80 mA maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (maximum
100 mA on even port pins (for example, P0[2],
P1[4]), maximum 100 mA on odd port pins (for
example, P0[3], P1[5])). 150 mA maximum combined IOL budget.
VIL
Input Low Level
–
–
0.8
V
Vdd = 3.0 to 5.25
VIH
Input High Level
2.1
–
V
Vdd = 3.0 to 5.25
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
4
5.6
8
Table 3-6. 2.7V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
kΩ
RPU
Pull up Resistor
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 0.4
–
–
V
IOH = 2 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16
mA maximum, 50 mA Typ combined IOH budget).
VOL
Low Output Level
–
–
0.75
V
IOL = 11.25 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget).
VIL
Input Low Level
–
–
0.8
V
Vdd = 2.4 to 3.0
VIH
Input High Level
2.0
–
–
V
Vdd = 2.4 to 3.0
VH
Input Hysteresis
–
90
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
September 8, 2004
4
5.6
8
Document No. 38-12028 Rev. *B
18
CY8C24x23A Final Data Sheet
3.3.3
3. Electrical Specifications
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 3-7. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.6
10
mV
Power = Medium, Opamp Bias = High
–
1.3
8
mV
Power = High, Opamp Bias = High
–
1.2
7.5
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
Gross tested to 1 µA.
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range
0.0
–
Vdd
V
Common Mode Voltage Range (high power or high
opamp bias)
0.5
–
Vdd - 0.5
The common-mode input voltage range is measured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
–
–
dB
Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
GOLOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Open Loop Gain
Power = Low, Opamp Bias = High
60
Power = Medium, Opamp Bias = High
60
Power = High, Opamp Bias = High
80
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Vdd - 0.2
–
–
V
Power = Medium, Opamp Bias = High
Vdd - 0.2
–
–
V
Power = High, Opamp Bias = High
Vdd - 0.5
–
–
V
Power = Low, Opamp Bias = High
–
–
0.2
V
Power = Medium, Opamp Bias = High
–
–
0.2
V
Power = High, Opamp Bias = High
–
–
0.5
V
Power = Low, Opamp Bias = High
–
150
200
µA
Power = Low, Opamp Bias = High
–
300
400
µA
Power = Medium, Opamp Bias = High
–
600
800
µA
Power = Medium, Opamp Bias = High
–
1200
1600
µA
Power = High, Opamp Bias = High
–
2400
3200
µA
Power = High, Opamp Bias = High
–
4600
6400
µA
Supply Voltage Rejection Ratio
64
–
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
September 8, 2004
Document No. 38-12028 Rev. *B
0V ≤ VIN ≤ (Vdd - 2.30) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
19
CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-8. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
High Power is 5 Volts Only
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
GOLOA
Open Loop Gain
–
–
dB
Specification is applicable at high power. For
all other bias modes (except high power, high
opamp bias), minimum is 60 dB.
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Power = Low, Opamp Bias = Low
60
Power = Medium, Opamp Bias = Low
60
Power = High, Opamp Bias = Low
80
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = Medium, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = High is 5V only
Vdd - 0.2
–
–
V
Power = Low, Opamp Bias = Low
–
–
0.2
V
Power = Medium, Opamp Bias = Low
–
–
0.2
V
Power = High, Opamp Bias = Low
–
–
0.2
V
Power = Low, Opamp Bias = Low
–
150
200
µA
Power = Low, Opamp Bias = High
–
300
400
µA
Power = Medium, Opamp Bias = Low
–
600
800
µA
Power = Medium, Opamp Bias = High
–
1200
1600
µA
Power = High, Opamp Bias = Low
–
2400
3200
µA
Power = High, Opamp Bias = High
–
4600
6400
µA
Supply Voltage Rejection Ratio
64
–
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
September 8, 2004
Document No. 38-12028 Rev. *B
0V ≤ VIN ≤ (Vdd - 2.30) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
20
CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-9. 2.7V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
High Power is 5 Volts Only
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
GOLOA
Open Loop Gain
–
–
dB
Specification is applicable at high power. For
all other bias modes (except high power, high
opamp bias), minimum is 60 dB.
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Power = Low, Opamp Bias = Low
60
Power = Medium, Opamp Bias = Low
60
Power = High
80
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = Medium, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = High is 5V only
Vdd - 0.2
–
–
V
Power = Low, Opamp Bias = Low
–
–
0.2
V
Power = Medium, Opamp Bias = Low
–
–
0.2
V
Power = High, Opamp Bias = Low
–
–
0.2
V
Power = Low, Opamp Bias = Low
–
150
200
µA
Power = Low, Opamp Bias = High
–
300
400
µA
Power = Medium, Opamp Bias = Low
–
600
800
µA
Power = Medium, Opamp Bias = High
–
1200
1600
µA
Power = High, Opamp Bias = Low
–
2400
3200
µA
Power = High, Opamp Bias = High
–
4600
6400
µA
Supply Voltage Rejection Ratio
64
–
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
September 8, 2004
Document No. 38-12028 Rev. *B
0V ≤ VIN ≤ (Vdd - 2.30) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
21
CY8C24x23A Final Data Sheet
3.3.4
3. Electrical Specifications
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-10. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
1
–
Ω
Power = High
–
1
–
Ω
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.1 –
–
V
0.5 x Vdd + 1.1 –
–
V
VOHIGHOB
Power = High
VOLOWOB
ISOB
PSRROB
Notes
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd - 1.3
V
Power = High
–
–
0.5 x Vdd - 1.3
V
Power = Low
–
1.1
5.1
mA
Power = High
–
2.6
8.8
mA
Supply Voltage Rejection Ratio
52
–
–
dB
Supply Current Including Bias Cell (No Load)
VOUT > (Vdd - 1.25)
Table 3-11. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
1
–
Ω
Power = High
–
1
–
Ω
Power = Low
0.5 x Vdd + 1.0 –
–
V
Power = High
0.5 x Vdd + 1.0 –
–
V
Power = Low
–
–
0.5 x Vdd - 1.0
V
Power = High
–
–
0.5 x Vdd - 1.0
V
VOHIGHOB
VOLOWOB
ISOB
High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
Notes
0.8
2.0
mA
Power = High
–
2.0
4.3
mA
Supply Voltage Rejection Ratio
52
–
–
dB
September 8, 2004
Document No. 38-12028 Rev. *B
VOUT > (Vdd - 1.25)
22
CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-12. 2.7V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
1
–
Ω
Power = High
–
1
–
Ω
Power = Low
0.5 x Vdd + 0.2 –
–
V
Power = High
0.5 x Vdd + 0.2 –
–
V
VOHIGHOB
VOLOWOB
ISOB
High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd - 0.7
V
Power = High
–
–
0.5 x Vdd - 0.7
V
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
Notes
0.8
2.0
mA
Power = High
–
2.0
4.3
mA
Supply Voltage Rejection Ratio
52
–
–
dB
September 8, 2004
Document No. 38-12028 Rev. *B
VOUT > (Vdd - 1.25)
23
CY8C24x23A Final Data Sheet
3.3.5
3. Electrical Specifications
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-13. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPUMP 5V
5V Output Voltage from Pump
4.75
5.0
5.25
V
Configuration of footnote a. Average, neglecting
ripple. SMP trip voltage is set to 5.0V.
VPUMP 3V
3.3V Output Voltage from Pump
3.00
3.25
3.60
V
Configuration of footnote a. Average, neglecting
ripple. SMP trip voltage is set to 3.25V.
VPUMP 2V
2.6V Output Voltage from Pump
2.45
2.55
2.80
V
Configuration of footnote a. Average, neglecting
ripple. SMP trip voltage is set to 2.55V.
IPUMP
Available Output Current
VBAT = 1.8V, VPUMP = 5.0V
5
–
–
mA
SMP trip voltage is set to 5.0V.
VBAT = 1.5V, VPUMP = 3.25V
8
–
–
mA
SMP trip voltage is set to 3.25V.
VBAT = 1.3V, VPUMP = 2.55V
8
–
–
mA
SMP trip voltage is set to 2.55V.
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote a. SMP trip voltage is
set to 5.0V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote a. SMP trip voltage is
set to 3.25V.
VBAT2V
Input Voltage Range from Battery
1.0
–
3.0
V
Configuration of footnote a. SMP trip voltage is
set to 2.55V.
VBATSTART
Minimum Input Voltage from Battery to Start Pump
1.2
–
–
V
Configuration of footnote a. 0oC ≤ TA ≤ 100.
Configuration of footnote a.
1.25V at TA = -40oC.
∆VPUMP_Line
Line Regulation (over VBAT range)
–
5
–
%VO
Configuration of footnote a. VO is the “Vdd
Value for PUMP Trip” specified by the VM[2:0]
setting in the DC POR and LVD Specification,
Table 3-18 on page 27.
∆VPUMP_Load
Load Regulation
–
5
–
%VO
Configuration of footnote a. VO is the “Vdd
Value for PUMP Trip” specified by the VM[2:0]
setting in the DC POR and LVD Specification,
Table 3-18 on page 27.
∆VPUMP_Ripple
Output Voltage Ripple (depends on capacitor/load)
–
100
–
mVpp
Configuration of footnote a. Load is 5 mA.
E3
Efficiency
35
50
–
%
Configuration of footnote a. Load is 5 mA. SMP
trip voltage is set to 3.25V.
E2
Efficiency
FPUMP
Switching Frequency
–
1.3
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure 3-2.
D1
Vdd
VPUMP
L1
VBAT
+
SMP
Battery
PSoCTM
C1
Vss
Figure 3-2. Basic Switch Mode Pump Circuit
September 8, 2004
Document No. 38-12028 Rev. *B
24
CY8C24x23A Final Data Sheet
3.3.6
3. Electrical Specifications
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 3-14. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.33
V
–
AGND = Vdd/2
Vdd/2 - 0.04
Vdd/2 - 0.01
Vdd/2 + 0.007
V
–
AGND = 2 x BandGap
2 x BG - 0.048
2 x BG - 0.030
2 x BG + 0.024
V
P2[4]
P2[4] + 0.011
V
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] - 0.011
–
AGND = BandGap
BG - 0.009
BG + 0.008
BG + 0.016
V
–
AGND = 1.6 x BandGap
1.6 x BG - 0.022
1.6 x BG - 0.010
1.6 x BG + 0.018
V
–
AGND Block to Block Variation (AGND = Vdd/2)
-0.034
0.000
0.034
V
–
RefHi = Vdd/2 + BandGap
Vdd/2 + BG - 0.10
Vdd/2 + BG
Vdd/2 + BG + 0.10
V
–
RefHi = 3 x BandGap
3 x BG - 0.06
3 x BG
3 x BG + 0.06
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
2 x BG + P2[6] - 0.113
2 x BG + P2[6] - 0.018
2 x BG + P2[6] + 0.077
V
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
V
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] + P2[6] - 0.133
P2[4] + P2[6] - 0.016
P2[4] + P2[6]+ 0.100
V
–
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
V
–
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.04
Vdd/2 - BG + 0.024
Vdd/2 - BG + 0.04
V
–
RefLo = BandGap
BG - 0.06
BG
BG + 0.06
V
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] - 0.084
2 x BG - P2[6] + 0.025
2 x BG - P2[6] + 0.134
V
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
V
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] - P2[6] - 0.057
P2[4] - P2[6] + 0.026
P2[4] - P2[6] + 0.110
V
Table 3-15. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.33
V
–
AGND = Vdd/2
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.005
V
–
AGND = 2 x BandGap
Not Allowed
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] - 0.008
P2[4] + 0.001
P2[4] + 0.009
V
–
AGND = BandGap
BG - 0.009
BG + 0.005
BG + 0.015
V
–
AGND = 1.6 x BandGap
1.6 x BG - 0.027
1.6 x BG - 0.010
1.6 x BG + 0.018
V
–
AGND Column to Column Variation (AGND = Vdd/2)
-0.034
0.000
0.034
mV
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] - 0.075
P2[4] + P2[6] - 0.009
P2[4] + P2[6] + 0.057
V
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] - P2[6] - 0.048
P2[4]- P2[6] + 0.022
P2[4] - P2[6] + 0.092
V
September 8, 2004
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CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-16. 2.7V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.16
1.30
1.33
V
–
AGND = Vdd/2
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.01
V
–
AGND = 2 x BandGap
Not Allowed
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] - 0.01
P2[4]
P2[4] + 0.01
V
–
AGND = BandGap
BG - 0.01
BG
BG + 0.015
V
–
AGND = 1.6 x BandGap
Not Allowed
–
AGND Column to Column Variation (AGND = Vdd/2)
-0.034
0.000
0.034
mV
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] - 0.08
P2[4] + P2[6] - 0.01
P2[4] + P2[6] + 0.06
V
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] - P2[6] - 0.05
P2[4]- P2[6] + 0.01
P2[4] - P2[6] + 0.09
V
3.3.7
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-17. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switch Cap)
–
80
–
fF
September 8, 2004
Document No. 38-12028 Rev. *B
Notes
26
CY8C24x23A Final Data Sheet
3.3.8
3. Electrical Specifications
DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 3-18. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Vdd Value for PPOR Trip
VPPOR0
PORLEV[1:0] = 00b
VPPOR1
PORLEV[1:0] = 01b
VPPOR2
PORLEV[1:0] = 10b
–
2.36
2.40
V
2.82
2.95
V
4.55
4.70
V
Notes
Vdd must be greater than or equal to 2.5V
during startup, reset from the XRES pin, or
reset from Watchdog.
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.40
2.450
2.51a
V0
VLVD1
VM[2:0] = 001b
2.85
2.920
2.99b
V0
VLVD2
VM[2:0] = 010b
2.95
3.02
3.09
VLVD3
V0
VM[2:0] = 011b
3.06
3.13
3.20
VLVD4
V0
VM[2:0] = 100b
4.37
4.48
4.55
VLVD5
VM[2:0] = 101b
4.50
4.64
4.75
VLVD6
VM[2:0] = 110b
4.62
4.73
4.83
VLVD7
VM[2:0] = 111b
4.71
4.81
4.95
V0
V
V
V
Vdd Value for SMP Trip
VPUMP0
VM[2:0] = 000b
2.500
2.550
2.62c
V
VPUMP1
VM[2:0] = 001b
2.96
3.02
3.09
V0
VPUMP2
VM[2:0] = 010b
3.03
3.10
3.16
V0
3.32d
V0
V0
V
V
V
VPUMP3
VM[2:0] = 011b
3.18
3.250
VPUMP4
VM[2:0] = 100b
4.54
4.64
4.74
VPUMP5
VM[2:0] = 101b
4.62
4.73
4.83
VPUMP6
VM[2:0] = 110b
4.71
4.82
4.92
VPUMP7
VM[2:0] = 111b
4.89
5.00
5.12
a.
b.
c.
d.
Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Always greater than 50 mV above VLVD0.
Always greater than 50 mV above VLVD3.
September 8, 2004
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CY8C24x23A Final Data Sheet
3.3.9
3. Electrical Specifications
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-19. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VddIWRITE
Supply Voltage for Flash Write Operations
2.70
–
–
V
IDDP
Supply Current During Programming or Verify
–
5
25
mA
VILP
Input Low Voltage During Programming or Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or Verify
2.1
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss + 0.75
V
VOHV
Output High Voltage During Programming or Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
(total)a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
September 8, 2004
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CY8C24x23A Final Data Sheet
3.4
3. Electrical Specifications
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-20. 5V and 3.3V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO24
Internal Main Oscillator Frequency for 24 MHz
23.4
24
a,b,c
24.6
MHz
Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on
page 15. SLIMO Mode = 0.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35a,b,c
MHz
Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on
page 15. SLIMO Mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6a,b
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3b,c
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2a,b,d
MHz
F24M
Digital PSoC Block Frequency
0
24
24.6b, d
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
FPLL
PLL Frequency
–
23.986
–
MHz
Is a multiple (x732) of crystal frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
TPLLSLEWS-
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
TOS
External Crystal Oscillator Startup to 1%
–
1700
2620
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
2800
3800
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
µs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2a,c
MHz
Jitter24M1P
24 MHz Period Jitter (IMO) Peak-to-Peak
–
300
Jitter24M1R
24 MHz Period Jitter (IMO) Root Mean Squared
–
–
600
ps
FMAX
Maximum frequency of signal on row input or row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
µs
Refer to the AC Digital Block Specifications
below.
LOW
a.
b.
c.
d.
The crystal oscillator frequency is within 100
ppm of its final value by the end of the Tosacc
period. Correct operation assumes a properly loaded 1 uW maximum drive level
32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 oC
≤ TA ≤ 85 oC.
ns
Trimmed. Utilizing factory trim values.
ps
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
See the individual user module data sheets for information on maximum frequencies for user modules.
September 8, 2004
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CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-21. 2.7V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO12
Internal Main Oscillator Frequency for 12 MHz
11.5
12
12.7a,b,c
MHz
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
SLIMO Mode = 1.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35a,b,c
MHz
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
SLIMO Mode = 1.
FCPU1
CPU Frequency (2.7V Nominal)0
0.930
30
3.15a,b
MHz0
FBLK27
Digital PSoC Block Frequency (2.7V Nominal)
0
12
12.7
MHz0
F32K1
Internal Low Speed Oscillator Frequency
8
32
96
kHz
Jitter32k
32 kHz Period Jitter
–
150
TXRST
External Reset Pulse Width
10
–
–
µs
DC12M
12 MHz Duty Cycle
40
50
60
%
Jitter12M1P
12 MHz Period Jitter (IMO) Peak-to-Peak
–
340
Jitter12M1R
12 MHz Period Jitter (IMO) Root Mean Squared
–
–
600
ps
FMAX
Maximum frequency of signal on row input or row output.
–
–
12.7
MHz
TRAMP
Supply Ramp Time
0
–
–
µs
a,b,c
Refer to the AC Digital Block Specifications below.
ns
ps
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for User Modules.
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 3-3. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
September 8, 2004
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30
CY8C24x23A Final Data Sheet
3. Electrical Specifications
32K
Select
32 kHz
TOS
F32K2
Figure 3-5. External Crystal Oscillator Startup Timing Diagram
Jitter24M1
F24M
Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram
September 8, 2004
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31
CY8C24x23A Final Data Sheet
3.4.2
3. Electrical Specifications
AC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-22. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
Description
Min
Typ
Max
Units
Notes
GPIO Operating Frequency
0
–
12
MHz
Normal Strong Mode
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
Table 3-23. 2.7V AC GPIO Specifications
Symbol
FGPIO
Description
Min
Typ
Max
Units
Notes
GPIO Operating Frequency
0
–
3
MHz
Normal Strong Mode
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
6
–
50
ns
Vdd = 2.4 to 3.0V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
6
–
50
ns
Vdd = 2.4 to 3.0V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
18
40
120
ns
Vdd = 2.4 to 3.0V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
18
40
120
ns
Vdd = 2.4 to 3.0V, 10% - 90%
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
Figure 3-8. GPIO Timing Diagram
September 8, 2004
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CY8C24x23A Final Data Sheet
3.4.3
3. Electrical Specifications
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V and 2.7V.
Table 3-24. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.9
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = High, Opamp Bias = High
–
–
0.62
µs
Power = Low, Opamp Bias = Low
–
–
5.9
µs
Power = Medium, Opamp Bias = High
–
–
0.92
µs
Power = High, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
0.15
–
–
V/µs
Power = Medium, Opamp Bias = High
1.7
–
–
V/µs
Power = High, Opamp Bias = High
6.5
–
–
V/µs
Power = Low, Opamp Bias = Low
0.01
–
–
V/µs
Power = Medium, Opamp Bias = High
0.5
–
–
V/µs
Power = High, Opamp Bias = High
4.0
–
–
V/µs
Power = Low, Opamp Bias = Low
0.75
–
–
MHz
Power = Medium, Opamp Bias = High
3.1
–
–
MHz
Power = High, Opamp Bias = High
5.4
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
Table 3-25. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.92
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
–
–
5.41
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
0.31
–
–
V/µs
Power = Medium, Opamp Bias = High
2.7
–
–
V/µs
Power = Low, Opamp Bias = Low
0.24
–
–
V/µs
Power = Medium, Opamp Bias = High
1.8
–
–
V/µs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
September 8, 2004
Document No. 38-12028 Rev. *B
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CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-26. 2.7V AC Operational Amplifier Specifications
Symbol
TROA
Description
Min
Typ
Max
Units
Power = Low, Opamp Bias = Low
–
–
3.92
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
–
–
5.41
µs
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = Low, Opamp Bias = Low
0.31
–
–
V/µs
Power = Medium, Opamp Bias = High
2.7
–
–
V/µs
Power = Low, Opamp Bias = Low
0.24
–
–
V/µs
Power = Medium, Opamp Bias = High
1.8
–
–
V/µs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
ENOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
3.4.4
AC Digital Block Specifications
TSOA
SRROA
SRFOA
BWOA
Notes
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-27. 5V and 3.3V AC Digital Block Specifications
Function
Timer
Counter
Dead Band
Description
Min
Typ
Max
Units
Capture Pulse Width
50a
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
Enable Pulse Width
50a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50a
–
–
ns
Disable Mode
50a
–
–
ns
Notes
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
Width of SS_ Negated Between Transmissions
50a
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
clocking.
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
September 8, 2004
Document No. 38-12028 Rev. *B
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CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-28. 2.7V AC Digital Block Specifications
Function
Description
Min
All
Functions
Maximum Block Clocking Frequency
Timer
Capture Pulse Width
100a
Maximum Frequency, With or Without Capture
–
Counter
Dead Band
Typ
Max
Units
12.7
MHz
–0
–0
ns
–
12.7
MHz
Enable Pulse Width
100
–
Maximum Frequency, No Enable Input
–
–
12.7
MHz
Maximum Frequency, Enable Input
–
–
12.7
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
100a
–0
–0
ns
a
0
0
ns
a
0
–
0
Notes
2.4V < Vdd < 3.0V.
ns
Kill Pulse Width:
Disable Mode
0
Maximum Frequency
100
–
–
–
–
12.7
MHz
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
–
–
12.7
MHz
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
12.7
MHz
SPIM
Maximum Input Clock Frequency
–
–
6.35
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.23
ns
Width of SS_ Negated Between Transmissions
100a
–0
–0
ns
Transmitter
Maximum Input Clock Frequency
–
–
12.7
MHz
Maximum data rate at 1.59 MHz due to 8 x over
Receiver
Maximum Input Clock Frequency
–
–
12.7
MHz
Maximum data rate at 1.59 MHz due to 8 x over
Maximum data rate at 3.17 MHz due to 2 x over
clocking.
clocking.
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
September 8, 2004
Document No. 38-12028 Rev. *B
35
CY8C24x23A Final Data Sheet
3.4.5
3. Electrical Specifications
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-29. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
2.5
µs
Power = High
–
–
2.5
µs
Power = Low
–
–
2.2
µs
Power = High
–
–
2.2
µs
Power = Low
0.65
–
–
V/µs
Power = High
0.65
–
–
V/µs
Power = Low
0.65
–
–
V/µs
Power = High
0.65
–
–
V/µs
Power = Low
0.8
–
–
MHz
Power = High
0.8
–
–
MHz
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Table 3-30. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
3.8
µs
Power = High
–
–
3.8
µs
Power = Low
–
–
2.6
µs
Power = High
–
–
2.6
µs
Power = Low
0.5
–
–
V/µs
Power = High
0.5
–
–
V/µs
Power = Low
0.5
–
–
V/µs
Power = High
0.5
–
–
V/µs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
September 8, 2004
Document No. 38-12028 Rev. *B
36
CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-31. 2.7V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
3.4.6
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
4
µs
Power = High
–
–
4
µs
Power = Low
–
–
3
µs
Power = High
–
–
3
µs
Power = Low
0.4
–
–
V/µs
Power = High
0.4
–
–
V/µs
Power = Low
0.4
–
–
V/µs
Power = High
0.4
–
–
V/µs
Power = Low
0.6
–
–
MHz
Power = High
0.6
–
–
MHz
Power = Low
180
–
–
kHz
Power = High
180
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-32. 5V AC External Clock Specifications
Symbol
FOSCEXT
Description
Min
Frequency
Typ
Max
Units
0.093
–
24.6
MHz
ns
–
High Period
20.6
–
5300
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
Notes
Table 3-33. 3.3V AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency with CPU Clock divide by
Min
1a
Typ
Max
0.093
–
12.3
Units
Notes
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or greaterb
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
September 8, 2004
Document No. 38-12028 Rev. *B
37
CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-34. 2.7V AC External Clock Specifications
Symbol
FOSCEXT
Description
Min
Frequency with CPU Clock divide by 1a
Typ
Max
0.093
–
12.3
Units
Notes
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or greaterb
0.186
–
12.3
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-35. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
20
–
ms
TWRITE
Flash Block Write Time
–
20
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
TDSCLK2
Data Out Delay from Falling Edge of SCLK
–
–
70
ns
2.4 ≤ Vdd ≤ 3.0
September 8, 2004
Document No. 38-12028 Rev. *B
38
CY8C24x23A Final Data Sheet
3.4.8
3. Electrical Specifications
AC I2C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-36. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
µs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
µs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
µs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
µs
THDDATI2C
Data Hold Time
0
–
0
–
µs
TSUDATI2C
Data Set-up Time
250
–
100
–
ns
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
0.6
–
µs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
µs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
a
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Table 3-37. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
–
–
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0
–
–
–
µs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
–
–
µs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
–
–
µs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
–
–
µs
THDDATI2C
Data Hold Time
0
–
–
–
µs
TSUDATI2C
Data Set-up Time
250
–
–
–
ns
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
–
–
µs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
–
–
µs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
–
–
ns
SDA
TLOWI2C
Notes
TSPI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus
September 8, 2004
Document No. 38-12028 Rev. *B
39
4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/support/link.cfm?mr=poddim.
4.1
Packaging Dimensions
51-85075 - *A
Figure 4-1. 8-Lead (300-Mil) PDIP
September 8, 2004
Document No. 38-12028 Rev. *B
40
CY8C24x23A Final Data Sheet
4. Packaging Information
51-85066
*B
51-85066
- *C
Figure 4-2. 8-Lead (150-Mil) SOIC
20-Lead
(300-Mil)
Molded
DIPP5
51-85011-A
51-85011
- *A
Figure 4-3. 20-Lead (300-Mil) Molded DIP
September 8, 2004
Document No. 38-12028 Rev. *B
41
CY8C24x23A Final Data Sheet
4. Packaging Information
51-85077 - *C
Figure 4-4. 20-Lead (210-Mil) SSOP
51-85024 - *B
Figure 4-5. 20-Lead (300-Mil) Molded SOIC
September 8, 2004
Document No. 38-12028 Rev. *B
42
CY8C24x23A Final Data Sheet
4. Packaging Information
51-85014 - *D
Figure 4-6. 28-Lead (300-Mil) Molded DIP
51-85079 - *C
Figure 4-7. 28-Lead (210-Mil) SSOP
September 8, 2004
Document No. 38-12028 Rev. *B
43
CY8C24x23A Final Data Sheet
4. Packaging Information
51-85026 - *C
Figure 4-8. 28-Lead (300-Mil) Molded SOIC
X = 138 MIL
Y = 138 MIL
32
51-85188 - **
Figure 4-9. 32-Lead (5x5 mm) MLF
September 8, 2004
Document No. 38-12028 Rev. *B
44
CY8C24x23A Final Data Sheet
4.2
4. Packaging Information
Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
Typical θJA *
8 PDIP
123 oC/W
8 SOIC
185 oC/W
20 PDIP
109 oC/W
20 SSOP
117 oC/W
20 SOIC
81 oC/W
28 PDIP
69 oC/W
28 SSOP
101 oC/W
28 SOIC
74 oC/W
32 MLF
22 oC/W
* TJ = TA + POWER x θJA
4.3
Capacitance on Crystal Pins
Table 4-2: Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
8 PDIP
2.8 pF
8 SOIC
2.0 pF
20 PDIP
3.0 pF
20 SSOP
2.6 pF
20 SOIC
2.5 pF
28 PDIP
3.5 pF
28 SSOP
2.8 pF
28 SOIC
2.7 pF
32 MLF
2.0 pF
September 8, 2004
Document No. 38-12028 Rev. *B
45
5. Ordering Information
The following table lists the CY8C24x23A PSoC device family’s key package features and ordering codes.
5.1
Flash
(Kbytes)
RAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Columns of 3)
Digital IO Pins
Analog Inputs
Analog Outputs
XRES Pin
8 Pin (300 Mil) DIP
8 Pin (150 Mil) SOIC
8 Pin (150 Mil) SOIC
(Tape and Reel)
20 Pin (300 Mil) DIP
20 Pin (210 Mil) SSOP
20 Pin (210 Mil) SSOP
(Tape and Reel)
20 Pin (300 Mil) SOIC
20 Pin (300 Mil) SOIC
(Tape and Reel)
28 Pin (300 Mil) DIP
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
28 Pin (300 Mil) SOIC
28 Pin (300 Mil) SOIC
(Tape and Reel)
32 Pin (5x5 mm) MLF
CY8C24123A-24PXI
CY8C24123A-24SXI
4
4
256
256
No
Yes
-40C to +85C
-40C to +85C
4
4
6
6
6
6
4
4
2
2
No
No
CY8C24123A-24SXIT
4
256
Yes
-40C to +85C
4
6
6
4
2
No
CY8C24223A-24PXI
CY8C24223A-24PVXI
4
4
256
256
Yes
Yes
-40C to +85C
-40C to +85C
4
4
6
6
16
16
8
8
2
2
Yes
Yes
CY8C24223A-24PVXIT
4
256
Yes
-40C to +85C
4
6
16
8
2
Yes
CY8C24223A-24SXI
4
256
Yes
-40C to +85C
4
6
16
8
2
Yes
CY8C24223A-24SXIT
4
256
Yes
-40C to +85C
4
6
16
8
2
Yes
CY8C24423A-24PXI
CY8C24423A-24PVXI
4
4
256
256
Yes
Yes
-40C to +85C
-40C to +85C
4
4
6
6
24
24
10
10
2
2
Yes
Yes
CY8C24423A-24PVXIT
4
256
Yes
-40C to +85C
4
6
24
10
2
Yes
CY8C24423A-24SXI
4
256
Yes
-40C to +85C
4
6
24
10
2
Yes
CY8C24423A-24SXIT
4
256
Yes
-40C to +85C
4
6
24
10
2
Yes
CY8C24423A-24LFXI
4
256
Yes
-40C to +85C
4
6
24
10
2
Yes
Ordering
Code
Package
Table 5-1. CY8C24x23A PSoC Device Key Features and Ordering Information
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Package Type:
PX = PDIP Pb Free
SX = SOIC Pb Free
PVX = SSOP Pb Free
LFX = MLF Pb Free
AX = TQFP Pb Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
September 8, 2004
Document No. 38-12028 Rev. *B
46
6. Sales and Company Information
To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to
the section titled “Getting Started” on page 4 in this document.
Cypress MicroSystems
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone:
Facsimile:
800.669.0557
425.787.4641
Web Sites:
Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
6.1
Revision History
Table 6-1. CY8C24x23A Data Sheet Revision History
Document Title:
CY8C24123A, CY8C24223A, and CY8C24423A PSoC Mixed Signal Array Final Data Sheet
Document Number: 38-12028
Issue Date
Origin of Change
**
Revision
236409
ECN #
See ECN
SFV
New silicon and new document – Preliminary Data Sheet.
*A
247589
See ECN
SFV
Changed the title to read “Final” data sheet. Updated Electrical Specifications chapter.
*B
261711
See ECN
HMT
Input all SFV memo changes. Updated Electrical Specifications chapter.
Distribution: External/Public
6.2
Description of Change
Posting: None
Copyrights and Code Protection
Copyrights
© Cypress MicroSystems, Inc. 2004. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks of Cypress MicroSystems,
Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applications, unless pursuant to an express written agreement with Cypress MicroSystems.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress MicroSystems devices.
Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of
products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems,
that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress MicroSystems nor any
other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products.
September 8, 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12028 Rev. *B
47