CY2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description ■ Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to four LVPECL output pairs ■ 30 ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) ■ Up to 1.5-GHz operation The CY2DP1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1504 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz. ■ Synchronous clock enable function ■ 20-pin thin shrunk small outline package (TSSOP) ■ 2.5-V or 3.3-V operating voltage[1] ■ Commercial and industrial operating temperature range Logic Block Diagram Q0 Q0# VDD VSS Q1 Q1# IN0 IN0# Q2 Q2# IN1 IN1# Q3 Q3# IN_SEL 100k VDD Q 100k CLK_EN D Note 1. Input AC-coupling capacitors are required for voltage-translation applications. Cypress Semiconductor Corporation Document Number: 001-56215 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 10, 2011 [+] Feedback CY2DP1504 Contents Pinouts .............................................................................. 3 Absolute Maximum Ratings ............................................ 4 Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information...................................................... 10 Ordering Code Definition ........................................... 10 Package Dimension........................................................ 11 Document Number: 001-56215 Rev. *F Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Page 2 of 14 [+] Feedback CY2DP1504 Pinouts Figure 1. Pin Diagram – 20-Pin TSSOP Package 1 20 Q0 CLK_EN 2 19 Q0# IN_SEL 3 18 V DD IN0 4 17 Q1 IN0# 5 16 Q1# IN1 IN1# 6 15 Q2 14 13 Q2# CY2DP1504 V SS NC 7 8 NC 9 12 Q3 V DD 10 11 Q3# V DD Table 1. Pin Definitions Pin No. Pin Name Pin Type Description 1 VSS Power Ground 2 CLK_EN Input Synchronous clock enable. Low-voltage complementary metal oxide semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL). When CLK_EN = Low, Q(0:3) outputs are held Low and Q(0:3)# outputs are held High 3 IN_SEL Input Input clock select pin. LVCMOS/LVTTL; When IN_SEL = Low, the IN0/IN0# differential input pair is active When IN_SEL = High, the IN1/IN1# differential input pair is active 4 IN0 Input LVPECL input clock. Active when IN_SEL = Low 5 IN0# Input LVPECL complementary input clock. Active when IN_SEL = Low 6 IN1 Input LVPECL input clock. Active when IN_SEL = High 7 IN1# Input LVPECL complementary input clock. Active when IN_SEL = High 8,9 NC No connection 10,13,18 VDD Power Power supply 11,14,16,19 Q(0:3)# Output LVPECL complementary output clocks 12,15,17,20 Q(0:3) Output LVPECL output clocks Document Number: 001-56215 Rev. *F Page 3 of 14 [+] Feedback CY2DP1504 Absolute Maximum Ratings Parameter Description Condition Min Max Unit VDD Supply voltage Nonfunctional –0.5 4.6 V VIN[2] Input voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0 or VDD + 0.4 V VOUT[2] DC output or I/O voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0 or VDD + 0.4 V TS Storage temperature Non functional –55 150 °C ESDHBM Electrostatic discharge (ESD) protection (Human body model) JEDEC STD 22-A114-B 2000 – V LU Latch up UL–94 Flammability rating MSL Moisture sensitivity level Meets or exceeds JEDEC Spec JESD78B IC Latchup Test At 1/8 in V-0 3 Operating Conditions Parameter VDD TA tPU Description Supply voltage Ambient operating temperature Power ramp time Condition Min Max Unit 2.5-V supply 2.375 2.625 V 3.3-V supply 3.135 3.465 V 0 70 °C Industrial Commercial –40 85 °C Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic). 0.05 500 ms Note 2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required. Document Number: 001-56215 Rev. *F Page 4 of 14 [+] Feedback CY2DP1504 DC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Condition Min Max Unit All LVPECL outputs floating (internal IDD) – 61 mA Input high voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# – VDD + 0.3 V VIL1 Input low voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# –0.3 – V IDD Operating supply current VIH1 VIH2 Input high voltage, CLK_EN, IN_SEL VDD = 3.3 V 2.0 VDD + 0.3 V VIL2 Input low voltage, CLK_EN, IN_SEL VDD = 3.3 V –0.3 0.8 V VIH3 Input high voltage, CLK_EN, IN_SEL VDD = 2.5 V 1.7 VDD + 0.3 V VIL3 Input low voltage, CLK_EN, IN_SEL VDD = 2.5 V –0.3 0.7 V VID[3] Input differential amplitude See Figure 2 on page 7 0.4 1.0 V VICM Input common mode voltage See Figure 2 on page 7 0.5 VDD – 0.2 V IIH Input high current, all inputs Input = VDD[4] – 150 μA IIL Input low current, all inputs Input = VSS[4] –150 – μA VOH LVPECL output high voltage Terminated with 50 Ω to VDD – VOL LVPECL output low voltage Terminated with 50 Ω to VDD – 2.0[5] RP Internal pull-up/pull-down resistance, LVCMOS logic inputs CLK_EN has pull-up only IN_SEL has pull-down only 60 140 kΩ CIN Input capacitance Measured at 10 MHz; per pin – 3 pF 2.0[5] VDD – 1.20 VDD – 0.70 V VDD – 2.0 VDD – 1.63 V Notes 3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV. 4. Positive current flows into the input pin, negative current flows out of the input pin. 5. Refer to Figure 3 on page 7. Document Number: 001-56215 Rev. *F Page 5 of 14 [+] Feedback CY2DP1504 AC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Condition FIN Input frequency FOUT Output frequency VPP LVPECL differential output voltage peak Fout = DC to 150 MHz to peak, single-ended. Terminated with 50 Ω to VDD – 2.0[6] Fout = >150 MHz to 1.5 GHz tPD [7] FOUT = FIN Min Typ Max Unit DC – 1.5 GHz DC – 1.5 GHz 600 – – mV 400 – – mV Propagation delay input pair to output pair Input rise/fall time < 1.5 ns (20% to 80%) – – 480 ps tODC[8] Output duty cycle 50% duty cycle at input Frequency range up to 1 GHz 48 – 52 % tSK1[9] Output-to-output skew Any output to any output, with same load conditions at DUT – – 30 ps tSK1 D[9] Device-to-device output skew Any output to any output between two or more devices. Devices must have the same input and have the same output load. – – 150 ps PNADD Additive RMS phase noise 156.25 MHz Input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV Offset = 1 kHz – – –120 dBc/Hz Offset = 10 kHz – – –130 dBc/Hz Offset = 100 kHz – – –135 dBc/Hz Offset = 1 MHz – – –145 dBc/Hz Offset = 10 MHz – – –153 dBc/Hz Offset = 20 MHz – – –155 dBc/Hz tJIT[10] Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV – – 0.15 ps tR, tF[11] Output rise/fall time 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) – – 300 ps tSOD Time from clock edge to outputs disabled Synchronous clock enable (CLK_EN) switched Low – – 700 ps tSOE Time from clock edge to outputs enabled Synchronous clock enable (CLK_EN) switched High – – 700 ps Notes 6. Refer to Figure 3 on page 7. 7. Refer to Figure 4 on page 7. 8. Refer to Figure 5 on page 7. 9. Refer to Figure 6 on page 8. 10. Refer to Figure 7 on page 8. 11. Refer to Figure 8 on page 8. Document Number: 001-56215 Rev. *F Page 6 of 14 [+] Feedback CY2DP1504 Figure 2. Input Differential and Common Mode Voltages VA IN VICM = (VA + VB)/2 VID IN# VB Figure 3. Output Differential Voltage VOH Q VPP Q# VOL Figure 4. Input to Any Output Pair Propagation Delay IN IN # QX Q X# t PD Figure 5. Output Duty Cycle QX Q X# tPW tPERIOD tODC = Document Number: 001-56215 Rev. *F tPW tPERIOD Page 7 of 14 [+] Feedback CY2DP1504 Figure 6. Output-to-Output and Device-to-Device Skew QX Q X# Device 1 QY Q Y# tSK1 QZ Device 2 Q Z# tSK1 D Figure 7. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f2 f1 RMS Jitter ∝ Area Under the Masked Phase Noise Plot Figure 8. Output Rise/Fall Time QX 80% 80% VPP 20% QX# 20% tR Document Number: 001-56215 Rev. *F tF Page 8 of 14 [+] Feedback CY2DP1504 Figure 9. Synchronous Clock Enable Timing CLK_EN IN IN# tSOD tPD tSOE QX QX# Document Number: 001-56215 Rev. *F Page 9 of 14 [+] Feedback CY2DP1504 Ordering Information Part Number Type Production Flow Pb-free CY2DP1504ZXC 20-Pin TSSOP Commercial, 0 °C to 70 °C CY2DP1504ZXCT 20-Pin TSSOP tape and reel Commercial, 0 °C to 70 °C CY2DP1504ZXI 20-Pin TSSOP Industrial, –40 °C to 85 °C CY2DP1504ZXIT 20-Pin TSSOP tape and reel Industrial, –40 °C to 85 °C Ordering Code Definition CY 2DP15 04 ZX C/I T Tape and reel Temperature range C = Commercial I = Industrial Pb-free TSSOP package Number of differential output pairs Base part number Company ID: CY = Cypress Document Number: 001-56215 Rev. *F Page 10 of 14 [+] Feedback CY2DP1504 Package Dimension Figure 10. 20-Pin Thin Shrunk Small Outline Package (4.40 mm Body) ZZ20 51-85118 *C Document Number: 001-56215 Rev. *F Page 11 of 14 [+] Feedback CY2DP1504 Acronyms Document Conventions Table 2. Acronyms Used in this Document Table 3. Units of Measure Acronym Description Symbol Unit of Measure ESD electrostatic discharge °C degree Celsius HBM human body model dBc decibels relative to the carrier JEDEC Joint electron devices engineering council GHz giga hertz LVCMOS low-voltage complementary metal oxide semiconductor Hz hertz kΩ kilo ohm µA microamperes µF micro Farad LVPECL low-voltage positive emitter-coupled logic LVTTL low-voltage transistor-transistor logic OE Output enable RMS root mean square TSSOP thin shrunk small outline package Document Number: 001-56215 Rev. *F µs microsecond mA milliamperes ms millisecond mV millivolt MHz megahertz ns nanosecond Ω ohm pF pico Farad ps pico second V volts W watts Page 12 of 14 [+] Feedback CY2DP1504 Document History Page Document Title: CY2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input Document Number: 001-56215 Revision ECN Orig. of Change Submission Date Description of Change ** 2782891 CXQ 10/09/09 *A 2838916 CXQ 01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”. Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added tPU spec to the Operating Conditions table on page 3. Changed max IDD spec in the DC Electrical Specs table on page 4 from 60 mA to 61 mA. Change VOH in the DC Electrical Specs table on page 4: minimum from VDD - 1.15V to VDD - 1.20V; maximum from VDD - 0.75V to VDD - 0.70V. Removed VOD spec from the DC Electrical Specs table on page 4. Added RP spec in the DC Electrical Specs table on page 4. Min = 60 kΩ, Max = 140 kΩ. Added a measurement definition for CIN in the DC Electrical Specs table on page 4. Added VPP spec to the AC Electrical Specs table on page 5. VPP min = 600 mV for DC - 150 MHz and min = 400 mV for 150 MHz to 1.5 GHz. Changed letter case and some names of all the timing parameters in the AC Electrical Specs table on page 5 to be consistent with EROS. Lowered all additive phase noise mask specs by 3 dB in the AC Electrical Specs table on page 5. Added condition to tR and tF specs in the AC Electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). Changed letter case and some names of all the timing parameters in Figures 3, 4, 5, 6 and 8, to be consistent with EROS. *B 3011766 CXQ 08/20/2010 Changed maximum additive jitter from 0.25 ps to 0.11 ps in “Features” on page 1 and in tJIT in the AC Electrical Specs table. Added note 3 to describe IIH and IIL specs. Removed reference to data distribution from “Functional Description”. Changed RP for differential inputs from 100 kΩ to 150 kΩ in the Logic Block Diagram and from 60 kΩ min / 140 kΩ max to 90 kΩ min / 210 kΩ max in the DC Electrical Specs table. Added max VID of 1.0V in DC Electrical Specs table. Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs table. Added “Frequency range up to 1 GHz” condition to tODC spec. Updated package diagram. Added Acronyms and Ordering Code Definition. *C 3017258 CXQ 08/27/2010 Corrected Output Rise/Fall time diagram. *D 3100234 CXQ 11/18/2010 Updated Phase jitter to 0.15ps max from 0.11ps max. Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4” Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec JESD78B IC Latchup Test” Removed RP spec for differential input clock pins INX and INX#. Changed CIN condition to “Measured at 10 MHz”. Changed PNADD specs for 1MHz, 10MHz, and 20MHz offsets. Removed tS and tH specs from AC specs table. *E 3135201 CXQ 01/12/2011 Removed “Preliminary” status heading. Removed resistors from INx/INx# in Logic Block Diagram. Added Figure 9 to describe TSOE and TSOD. *F 3090938 CXQ 02/25/2011 Post to external web. Document Number: 001-56215 Rev. *F New Datasheet. Page 13 of 14 [+] Feedback CY2DP1504 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2011. 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Document Number: 001-56215 Rev. *F Revised January 10, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback