DA DAC9881 C9 88 1 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 18-Bit, Single-Channel, Low-Noise, Voltage-Output DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION 1 • • • • • 234 • • • • • • • 18-Bit Monotonic Over Temperature Range Relative Accuracy: ±2LSB Max Low-Noise: 24nV/√Hz Fast Settling: 5µs On-Chip Output Buffer Amplifier with Rail-to-Rail Operation Single Power Supply: +2.7V to +5.5V DAC Loading Control Selectable Power-On Reset to Zero-Scale or Midscale Power-Down Mode Unipolar Straight Binary or Twos Complement Input Mode Fast SPI™ Interface with Schmitt-Triggered Inputs: up to 50MHz, 1.8V/3V/5V Logic Small Package: QFN-24, 4mm × 4mm The DAC9881 is an 18-bit, single-channel, voltage-output digital-to-analog converter (DAC). It features 18-bit monotonicity, excellent linearity, very low-noise, and fast settling time. The on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the full supply range of 2.7V to 5.5V. The device supports a standard SPI serial interface capable of operating with input data clock frequencies up to 50MHz. The DAC9881 requires an external reference voltage to set the output range of the DAC channel. A programmable power-on reset circuit is also incorporated into the device to ensure that the DAC output powers up at zero-scale or midscale, and remains there until a valid write command. Additionally, the DAC9881 has the capability to function in either unipolar straight binary or twos complement mode. The DAC9881 provides low-power operation. To further save energy, power-down mode can be achieved by accessing the PDN pin, thereby reducing the current consumption to 25µA at 5V. Power consumption is 4mW at 5V, reducing to 125µW in power-down mode. APPLICATIONS • • • • Automatic Test Equipment Precision Instrumentation Industrial Control Data Acquisition Systems The DAC9881 is available in a 4mm × 4mm QFN-24 package with a specified temperature range of –40°C to +105°C. DGND IOVDD AGND AVDD VREFH-S VREFH-F DAC9881 RST Power-On Reset RSTSEL Control Logic USB/BTC Resistor Network SDI CS SCLK SPI Interface Shift Register GAIN PDN Input Register DAC Latch VOUT DAC RFB(1) RFB SDOSEL SDO Serial Out Control NOTE: (1) RFB = 5kW for gain = 1, RFB = 10kW for gain = 2. LDAC VREFL-S VREFL-F 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE DAC9881S ±3 –1/+2 QFN-24 RGE –40°C to +105°C DAC9881 DAC9881SB ±2 ±1 QFN-24 RGE –40°C to +105°C DAC9881B (1) PACKAGE MARKING For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). PARAMETER DAC9881 UNIT AVDD to AGND –0.3 to 6 V IOVDD to DGND –0.3 to 6 V Digital input voltage to DGND –0.3 to IOVDD + 0.3 V VOUT to AGND –0.3 to AVDD + 0.3 V Operating temperature range –40 to +105 °C Storage temperature range –65 to +150 °C +150 °C Maximum junction temperature (TJ max) Thermal impedance (θJA) ESD ratings (1) 2 46 °C/W Human body model (HBM) 3000 V Charged device model (CDM) 1000 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications at TA = TMIN to TMAX, AVDD = +4.75V to +5.5V, IOVDD = +1.8V to +5.5V, VREFH = 5V, VREFL = 0V, and gain = 1X mode, unless otherwise noted. DAC9881 PARAMETER CONDITIONS MIN TYP MAX UNIT ACCURACY (1) Measured by line passing through codes 2048 and 260096 DAC9881S ±2 ±3 LSB Integral linearity error DAC9881SB ±1 ±2 LSB Measured by line passing through codes 2048 and 260096 DAC9881S ±0.75 +2 LSB Differential linearity error ±0.5 ±1 LSB ±16 LSB ±32 LSB –1 DAC9881SB Monotonicity 18 Bits TA = +25°C, code = 2048 Zero-scale error TMIN to TMAX, code = 2048 Zero-scale drift (2) Code = 2048 Gain error TA = +25°C, measured by line passing through codes 2048 and 260096 ±16 ±32 LSB Measured by line passing through codes 2048 and 260096 ±0.25 ±0.4 ppm/°C 32 LSB/V Gain temperature drift (2) PSRR (2) ±0.25 VOUT = full-scale, AVDD = +5V ±10% ±0.8 ppm/°C of FSR ANALOG OUTPUT (2) Voltage output (3) Output voltage drift vs time 0 AVDD V Device operating for 500 hours at +25°C 0.1 ppm of FSR Device operating for 1000 hours at +25°C 0.2 ppm of FSR Output current (4) 2.5 mA Maximum load capacitance 200 pF +31/–50 mA Short-circuit current REFERENCE INPUT (2) VREFH input voltage range AVDD = +5.5V 1.25 VREFH input capacitance 5.0 AVDD V 5 VREFH input impedance pF 4.5 VREFL input voltage range –0.2 VREFL input capacitance VREFL input impedance 0 kΩ +0.2 V 4.5 pF 5 kΩ 5 µs DYNAMIC PERFORMANCE (2) Settling time To ±0.003% FS, RL = 10kΩ, CL = 50pF, code 04000h to 3C000h Slew rate From 10% to 90% of 0V to +5V Code change glitch Digital feedthrough Code = 1FFFFh to 20000h to 1FFFFh 2.5 V/µs VREFH = 5V, gain = 1X mode 37 nV-s VREFH = 2.5V, gain = 1X mode 18 nV-s VREFH = 1.25V, gain = 1X mode 9 nV-s VREFH = 2.5V, gain = 2X mode 21 nV-s VREFH = 1.25V, gain = 2X mode 10 nV-s CS = high, fSCLK = 1kHz 1 24 30 nV/√Hz Gain = 2 40 48 nV/√Hz Output noise voltage density f = 1kHz to 100kHz, full-scale output Output noise voltage f = 0.1Hz to 10Hz, full-scale output (1) (2) (3) (4) nV-s Gain = 1 2 µVPP DAC output range is 0V to +5V. 1LSB = 19µV. Ensured by design. Not production tested. The output from the VOUT pin = [(VREFH – VREFL)/262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0V to AVDD. The full-scale of the output must be less than AVDD; otherwise, output saturation occurs. Refer to Figure 26, Figure 27, and Figure 28 for details. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 3 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications at TA = TMIN to TMAX, AVDD = +4.75V to +5.5V, IOVDD = +1.8V to +5.5V, VREFH = 5V, VREFL = 0V, and gain = 1X mode, unless otherwise noted. DAC9881 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (5) High-level input voltage, VIH Low-level input voltage, VIL IOVDD = 4.5V to 5.5V 3.8 IOVDD + 0.3 V IOVDD = 2.7V to 3.3V 2.1 IOVDD + 0.3 V IOVDD = 1.7V to 2.0V 1.5 IOVDD + 0.3 V IOVDD = 4.5V to 5.5V –0.3 0.8 V IOVDD = 2.7V to 3.3V –0.3 0.6 V IOVDD = 1.7V to 2.0V –0.3 0.3 V ±10 µA Digital input current (IIN) ±1 Digital input capacitance 5 pF DIGITAL OUTPUT (5) High-level output voltage, VOH Low-level output voltage, VOL IOVDD = 2.7V to 5.5V, IOH = –1mA IOVDD – 0.2 IOVDD = 1.7V to 2.0V, IOH = –500µA IOVDD – 0.2 V V IOVDD = 2.7V to 5.5V, IOL = 1mA 0.2 V IOVDD = 1.7 to 2.0V, IOL = 500µA 0.2 V +5.5 V POWER SUPPLY AVDD +4.75 IOVDD +1.7 +5.0 AVDD AIDD VIH = IOVDD, VIL = DGND IOIDD VIH = IOVDD, VIL = DGND AIDD power-down PDN pin = IOVDD Power dissipation AVDD = 5.0V 4.3 V 0.85 1.5 mA 1 10 µA 25 50 µA 7.5 mW TEMPERATURE RANGE Specified performance (5) 4 –40 +105 °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: AVDD = 2.7V All specifications at TA = TMIN to TMAX, AVDD = +2.7V to +3.3V, IOVDD = +1.8V to AVDD, VREFH = 2.5V, VREFL = 0V and gain = 1X mode, unless otherwise noted. DAC9881 PARAMETER CONDITIONS MIN TYP MAX UNIT ±2.5 ±3.5 LSB ACCURACY (1) Measured by line passing through codes 2048 and 262143 DAC9881S Integral linearity error DAC9881SB ±2 ±3 LSB Measured by line passing through codes 2048 and 262143 DAC9881S ±1 ±2 LSB Differential linearity error ±0.75 ±1.5 LSB TA = +25°C, code = 2048 ±32 LSB TMIN to TMAX, code = 2048 ±64 LSB Zero-scale error DAC9881SB Zero-scale drift (2) Code = 2048 ±0.5 ±1.6 ppm/°C of FSR Gain error TA = +25°C, measured by line passing through codes 2048 and 262143 ±32 ±64 LSB Measured by line passing through codes 2048 and 262143 ±0.5 ±0.8 ppm/°C 64 LSB/V Gain temperature drift (2) PSRR (2) VOUT = full-scale, AVDD = +3V ±10% ANALOG OUTPUT (2) Voltage output (3) Output voltage drift vs time 0 AVDD V Device operating for 500 hours at +25°C 0.2 ppm of FSR Device operating for 1000 hours at +25°C 0.4 ppm of FSR Output current (4) 2.5 mA Maximum load capacitance 200 pF +31/–50 mA Short-circuit current REFERENCE INPUT (2) VREFH input voltage range AVDD = +3V 1.25 VREFH input capacitance 2.5 AVDD V 5 VREFH input impedance pF 4.5 VREFL input voltage range –0.2 VREFL input capacitance VREFL input impedance 0 kΩ +0.2 V 4.5 pF 5 kΩ 5 µs DYNAMIC PERFORMANCE (2) Settling time To ±0.003% FS, RL = 10kΩ, CL = 50pF, code 04000h to 3C000h Slew rate From 10% to 90% of 0V to +2.5V 2.5 V/µs 18 nV-s VREFH = 1.25V, gain = 1X mode 9 nV-s VREFH = 1.25V, gain = 2X mode 10 nV-s VREFH = 2.5V, gain = 1X mode Code change glitch Code = 1FFFFh to 20000h to 1FFFFh Digital feedthrough CS = high, fSCLK = 1kHz Output noise voltage density f = 1kHz to 100kHz, full-scale output Output noise voltage f = 0.1Hz to 10Hz, full-scale output (1) (2) (3) (4) 1 nV-s Gain = 1 24 30 nV/√Hz Gain = 2 40 48 nV/√Hz 2 µVPP DAC output range is 0V to +2.5V. 1LSB = 9.5µV. Ensured by design. Not production tested. The output from the VOUT pin = [(VREFH – VREFL)/262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0V to AVDD. The full-scale of the output must be less than AVDD; otherwise, output saturation occurs. Refer to Figure 55, Figure 56, and Figure 57 for details. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 5 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: AVDD = 2.7V (continued) All specifications at TA = TMIN to TMAX, AVDD = +2.7V to +3.3V, IOVDD = +1.8V to AVDD, VREFH = 2.5V, VREFL = 0V and gain = 1X mode, unless otherwise noted. DAC9881 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (5) High-level input voltage, VIH Low-level input voltage, VIL IOVDD = 2.7V to 3.3V 2.1 IOVDD + 0.3 V IOVDD = 1.7V to 2.0V 1.5 IOVDD + 0.3 V IOVDD = 2.7V to 3.3V –0.3 0.6 V IOVDD = 1.7V to 2.0V –0.3 0.3 V ±10 µA Digital input current (IIN) ±1 Digital input capacitance 5 pF DIGITAL OUTPUT (5) High-level output voltage, VOH Low-level output voltage, VOL IOVDD = 2.7V to 3.3V, IOH = –1mA IOVDD – 0.2 IOVDD = 1.7V to 2.0V, IOH = –500µA IOVDD – 0.2 V V IOVDD = 2.7V to 3.3V, IOL = 1mA 0.2 V IOVDD = 1.7 to 2.0V, IOL = 500µA 0.2 V +3.3 V POWER SUPPLY AVDD +2.7 IOVDD +1.7 +3.0 AVDD AIDD VIH = IOVDD, VIL = DGND IOIDD VIH = IOVDD, VIL = DGND AIDD power-down PDN pin = IOVDD Power dissipation AVDD = 3.0V 2.3 V 0.75 1.2 mA 1 10 µA 25 50 µA 3.6 mW TEMPERATURE RANGE Specified performance (5) 6 –40 +105 °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 PIN CONFIGURATION (1) SDO DGND AVDD SDOSEL CS 22 21 20 19 IOVDD 24 23 RGE PACKAGE(1) QFN-24 (TOP VIEW) SCLK 1 18 PDN SDI 2 17 RST LDAC 3 16 USB/BTC AGND 4 15 GAIN AVDD 5 14 RSTSEL VREFL-S 6 13 NC DAC9881 10 11 12 NC RFB VREFL-F 9 VOUT VREFH-F 7 8 VREFH-S (Thermal Pad)(1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. TERMINAL FUNCTIONS TERMINAL NO. NAME I/O 1 SCLK I SPI bus serial clock input DESCRIPTION 2 SDI I SPI bus serial data input 3 LDAC I Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. It is recommended to connect this pin to IOVDD through a pull-up resistor. 4 AGND I Analog ground 5 AVDD I Analog power supply 6 VREFL-S I Reference low input sense 7 VREFH-S I Reference high input sense 8 VOUT O Output of output buffer 9 RFB I Feedback resistor connected to the inverting input of the output buffer. 10 VREFL-F I Reference low input force 11 VREFH-F I Reference high input force 12 NC — Do not connect. 13 NC — Do not connect. 14 RSTSEL I Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data = 20000h. If RSTSEL = DGND, then register data = 00000h. 15 GAIN I Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD. 16 USB/BTC I Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in twos complement format when the pin is connected to DGND. 17 RST I Reset input (active low). Logic low on this pin causes the device to perform a reset. 18 PDN I Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT pin connects to AGND through a 10kΩ resistor. 19 CS I SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is high, SDO is in a high-impedance state. It is recommended to connect this pin to IOVDD through a pull-up resistor. 20 SDOSEL I SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register are shifted out from the SDO pin; this is Daisy-Chain mode for daisy-chained communication. 21 AVDD I Analog power supply. Must be connected to pin 5. 22 DGND I Digital ground 23 SDO O SPI bus serial data output. Refer to the Timing Diagrams for further detail. 24 IOVDD I Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 7 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TIMING DIAGRAMS Case 1: Standalone operation without SDO, LDAC tied low. t1 t2 CS t3 t4 t7 t6 t5 Input Register and DAC Latch Updated SCLK t8 Bit 23 (N) SDI LDAC t9 Bit 22 (N) Bit 1 (N) Bit 0 (N) Low Case 2: Standalone operation without SDO, LDAC active. t2 t1 CS Input Register Updated t3 t4 t7 t6 t5 SCLK t8 Bit 23 (N) SDI LDAC t9 Bit 22 (N) Bit 1 (N) Bit 0 (N) t14 High t15 DAC Latch Updated = Don’t Care Bit 23 = MSB Bit 0 = LSB Figure 1. Timing Diagram for Standalone Operation without SDO 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TIMING CHARACTERISTICS for Figure 1 (1) (2) (3) At –40°C to +105°C, unless otherwise noted. PARAMETER fSCLK Maximum clock frequency t1 Minumum CS high time MAX UNIT 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD CONDITIONS MIN 40 MHz 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 50 MHz 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 50 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 30 ns 10 ns t2 Delay from CS falling edge to SCLK rising edge 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 8 ns t3 Delay from SCLK falling edge to CS falling edge 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 0 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 0 ns t4 SCLK low time 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 15 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 25 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 20 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 8 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 15 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns t5 SCLK high time t6 SCLK cycle time t7 Delay from SCLK rising edge to CS rising edge t8 Input data setup time t9 Input data hold time t14 Delay from CS rising edge to LDAC falling edge t15 LDAC pulse width (1) (2) (3) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. Ensured by design. Not production tested. Sample tested during the initial release and after any redesign or process changes that may affect these parameters. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 9 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com Case 1: Standalone operation with output from SDO, LDAC tied low. t1 t2 CS Input Register and DAC Latch Updated t3 t4 t7 t6 t5 SCLK t8 Bit 23 (N) SDI t9 Bit 22 (N) Bit 1 (N) t11 High-Z SDO LDAC Bit 23 (N - 1) from Input Reg. Bit 22 (N - 1) from Input Reg. Bit 0 (N) t12 t13 Bit 1 (N - 1) from Input Reg. Bit 0 (N - 1) from Input Reg. High-Z t10 Low Case 2: Standalone operation with output from SDO, LDAC active. t2 t1 CS Input Register Updated t3 t4 t7 t6 t5 SCLK t8 Bit 23 (N) SDI t9 Bit 22 (N) Bit 1 (N) t11 High-Z SDO LDAC High Bit 23 (N - 1) from Input Reg. Bit 22 (N - 1) from Input Reg. Bit 0 (N) t12 Bit 1 (N - 1) from Input Reg. t13 Bit 0 (N - 1) from Input Reg. t10 t14 High-Z t15 DAC Latch Updated = Don’t Care Bit 23 = MSB Bit 0 = LSB Figure 2. Timing Diagram for Standalone Operation with SDO 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 Case 1: Daisy Chain, LDAC tied low. t1 t2 CS Input Register and DAC Latch Updated t3 t4 t7 t6 t5 SCLK t8 Bit 23 (N) SDI t9 Bit 22 (N) Bit 0 (N) Bit 23 (N + 1) t11 LDAC t12 Bit 23 (N) High-Z SDO Bit 0 (N + 1) t13 (1) Bit 0 (N) High-Z t10 Low Case 2: Daisy Chain, LDAC active. t1 t2 CS Input Register Updated t3 t4 t7 t6 t5 SCLK t8 Bit 23 (N) SDI t9 Bit 22 (N) Bit 0 (N) Bit 23 (N + 1) t11 LDAC High t12 t13 Bit 23 (N)(1) High-Z SDO Bit 0 (N + 1) t10 Bit 0 (N) High-Z t14 t15 DAC Latch Updated = Don’t Care Bit 23 = MSB Bit 0 = LSB NOTE: (1) SDO data delayed from SDI by 24 clock cycles. Figure 3. Timing Diagram for Daisy Chain Mode, Two Cascaded Devices Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 11 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS for Figure 2 and Figure 3 (1) (2) (3) At –40°C to +105°C, unless otherwise noted. PARAMETER fSCLK Maximum clock frequency t1 Minumum CS high time MAX UNIT 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD CONDITIONS MIN 20 MHz 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 25 MHz 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 50 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 30 ns 10 ns t2 Delay from CS falling edge to SCLK rising edge 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 8 ns t3 Delay from SCLK falling edge to CS falling edge 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 0 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 0 ns t4 SCLK low time 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 25 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 20 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 25 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 20 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 50 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 40 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 t5 SCLK high time t6 SCLK cycle time t7 Delay from SCLK rising edge to CS rising edge t8 Input data setup time t9 Input data hold time t10 Delay from CS falling edge to SDO valid t11 Delay from SCLK falling edge to SDO valid t12 SDO data hold from SCLK rising edge t13 Delay from CS rising edge to SDO high-Z t14 Delay from CS rising edge to LDAC falling edge t15 (1) (2) (3) 12 LDAC pulse width ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 15 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 20 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 15 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD t5 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD t5 ns ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 8 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 15 ns 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. Ensured by design. Not production tested. Sample tested during the initial release and after any redesign or process changes that may affect these parameters. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 2.0 TA = +25°C 1.5 1.5 1.0 1.0 DNL Error (LSB) INL Error (LSB) 2.0 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.5 0 -0.5 -0.5 -1.5 -1.5 -2.0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code Figure 4. Figure 5. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2.0 2.0 TA = -40°C 1.5 1.5 1.0 1.0 DNL Error (LSB) INL Error (LSB) 0 -1.0 0 0.5 0 -0.5 TA = -40°C 0.5 0 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -2.0 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code Figure 6. Figure 7. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARY ERROR vs DIGITAL INPUT CODE 2.0 2.0 TA = +105°C 1.5 1.5 1.0 1.0 DNL Error (LSB) INL Error (LSB) 0.5 -1.0 -2.0 TA = +25°C 0.5 0 -0.5 0.5 0 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 TA = +105°C -2.0 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code 0 Figure 8. 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code Figure 9. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 13 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 2.0 2.0 1.5 1.5 INL Max 1.0 DNL Error (LSB) INL Error (LSB) 1.0 0.5 0 -0.5 INL Min DNL Min -0.5 -1.0 -1.5 -1.5 -2.0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 -40 0 -20 20 40 60 Temperature (°C) 80 100 Figure 10. Figure 11. LINEARITY ERROR vs TEMPERATURE (GAIN = 2X MODE) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE (GAIN = 2X MODE) 2.0 120 2.0 1.5 1.5 INL Max 1.0 DNL Error (LSB) 1.0 INL Error (LSB) 0 -1.0 -2.0 DNL Max 0.5 0.5 0 -0.5 INL Min -1.0 DNL Max 0.5 0 DNL Min -0.5 -1.0 VREFH = 2.5V VREFL = 0V -1.5 VREFH = 2.5V VREFL = 0V -1.5 -2.0 -2.0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 -40 -20 0 20 40 60 Temperature (°C) 80 100 Figure 12. Figure 13. LINEARITY ERROR vs SUPPLY VOLTAGE DIFFERENTIAL LINEARITY ERROR vs SUPPLY VOLTAGE 2.0 120 2.0 1.5 1.5 INL Max 1.0 DNL Error (LSB) INL Error (LSB) 1.0 0.5 0 INL Min -0.5 -1.0 -1.5 DNL Max 0.5 0 DNL Min -0.5 -1.0 VREFH = 2.5V VREFL = 0V -1.5 -2.0 VREFH = 2.5V VREFL = 0V -2.0 2.5 3.0 3.5 4.0 4.5 5.0 Supply Voltage (V) 5.5 6.0 2.5 Figure 14. 14 3.0 3.5 4.0 4.5 5.0 Supply Voltage (V) 5.5 6.0 Figure 15. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE 2.0 2.0 1.5 1.5 INL Max 1.0 DNL Error (LSB) INL Error (LSB) 1.0 0.5 0 INL Min -0.5 -1.5 -1.5 -2.0 1.0 2.0 3.0 4.0 Reference Voltage (V) 5.0 6.0 0 1.0 2.0 3.0 4.0 Reference Voltage (V) 5.0 Figure 16. Figure 17. FULL-SCALE AND ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE AND ZERO-SCALE ERROR vs TEMPERATURE (GAIN = 2X MODE) 6.0 1.0 Full-Scale and Zero-Scale Error (mV) 1.0 Full-Scale and Zero-Scale Error (mV) DNL Min -0.5 -1.0 0 0.8 0.6 0.4 Full-Scale Error 0.2 0 Zero-Scale Error -0.2 -0.4 -0.6 -0.8 -1.0 VREFH = 2.5V VREFL = 0V 0.8 0.6 0.4 Full-Scale Error 0.2 0 -0.2 Zero-Scale Error -0.4 -0.6 -0.8 -1.0 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 125 -55 AVDD = 5.0V VREFH = 5.0V VREFL = 0V 105 125 AVDD = 2.7V VREFH = 2.7V VREFL = 0V 600 AVDD = 5.0V VREFH = 2.5V VREFL = 0V 900 AVDD Supply Current (mA) 700 AVDD = 2.7V VREFH = 2.5V VREFL = 0V 400 85 AVDD SUPPLY CURRENT vs DIGITAL INPUT CODE (GAIN = 2X MODE) AVDD = 5.0V VREFH = 2.5V VREFL = 0V 500 25 45 65 Temperature (°C) AVDD SUPPLY CURRENT vs DIGITAL INPUT CODE 1000 800 5 -15 Figure 19. 1000 900 -35 Figure 18. 1100 AVDD Supply Current (mA) 0 -1.0 -2.0 DNL Max 0.5 300 800 700 AV AVDD = 2.7V 2.7V DD = VVREFH = 1.25V 1.25V REFH = VVREFL = 0V 0V REFL = 600 500 400 300 200 100 0 200 0 65536 131072 Digital Input Code 196608 262144 0 Figure 20. 65536 131072 Digital Input Code 196608 262144 Figure 21. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 15 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. AVDD SUPPLY CURRENT vs TEMPERATURE AVDD POWER-DOWN CURRENT vs TEMPERATURE 50 AVDD Power-Down Current (mA) AVDD Supply Current (mA) 1200 1000 800 VREFH = 5.0V VREFL = 0V Gain = 1X Mode 600 VREFH = 2.5V VREFL = 0V Gain = 2X Mode 400 200 40 30 AVDD = 5.0V 20 AVDD = 2.7V 10 DAC Code Set to 3F000h 0 0 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 125 -55 85 105 125 REFERENCE CURRENT vs DIGITAL INPUT CODE REFERENCE CURRENT vs DIGITAL INPUT CODE (GAIN = 2X MODE) 1.5 VREFH Current VREFH = 2.5V VREFL = 0V Reference Current (mA) 1.0 0.5 0 VREFL Current -0.5 -1.0 VREFH Current 0.5 0 -0.5 VREFL Current -1.0 -1.5 -1.5 0 65536 131072 Digital Input Code 196608 262144 0 65536 131072 Digital Input Code 196608 262144 Figure 24. Figure 25. OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AVDD Rail) 5.0 5.00 DAC Loaded with 3FFFFh 4.5 DAC Loaded with 3FFFFh 4.95 Output Voltage (V) 4.0 Output Voltage (V) 25 45 65 Temperature (°C) Figure 23. 1.0 3.5 3.0 2.5 2.0 1.5 1.0 DAC Loaded with 3F800h 4.90 DAC Loaded with 3F000h 4.85 4.80 DAC Loaded with 00000h 0.5 0 DAC Loaded with 3E000h 4.75 0 3 6 9 I(SOURCE/SINK) (mA) 12 15 0 Figure 26. 16 5 -15 Figure 22. 1.5 Reference Current (mA) -35 1 2 3 ISOURCE (mA) 4 5 Figure 27. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AGND Rail) IOVDD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 200 0.25 IOVDD Supply Current (mA) 180 Output Voltage (V) 0.20 DAC Loaded with 02000h 0.15 DAC Loaded with 01000h 0.10 DAC Loaded with 00800h 0.05 IOVDD = 5V 160 140 120 100 80 60 40 IOVDD = 2.7V 20 DAC Loaded with 00000h 0 0 1 2 0 3 4 0 5 ISINK (mA) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Logic Input Voltage (V) Figure 28. Figure 29. LARGE SIGNAL SETTLING TIME LARGE SIGNAL SETTLING TIME 4.0 4.5 5.0 Large-Signal Output 2V/div LargeSignal Output Small-Signal Error 2V/div 5V/div 1mV/div LDAC Signal Code Change: 00000h to 3FFFFh Output Loaded with 10kW and 50pF to AGND Small-Signal Error 5V/div LDAC Signal Time (2ms/div) 1mV/div Code Change: 3FFFFh to 00000h Output Loaded with 10kW and 50pF to AGND Time (2ms/div) Figure 30. Figure 31. LARGE SIGNAL SETTLING TIME LARGE SIGNAL SETTLING TIME Large-Signal Output 2V/div Large-Signal Output Small-Signal Error 2V/div 1mV/div 1mV/div Small-Signal Error 5V/div LDAC Signal Code Change: 04000h to 3C000h Output Loaded with 10kW and 50pF to AGND 5V/div LDAC Signal Time (2ms/div) Code Change: 3C000h to 04000h Output Loaded with 10kW and 50pF to AGND Time (2ms/div) Figure 32. Figure 33. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 17 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) VREFH = 2.5V LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) VREFH = 2.5V Large-Signal Output 2V/div LargeSignal Output Small-Signal Error 2V/div 5V/div 1mV/div LDAC Signal Code Change: 00000h to 3FFFFh Output Loaded with 10kW and 50pF to AGND Small-Signal Error 5V/div 1mV/div LDAC Signal Code Change: 3FFFFh to 00000h Output Loaded with 10kW and 50pF to AGND Time (2ms/div) Time (2ms/div) Figure 34. Figure 35. LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) VREFH = 2.5V VREFH = 2.5V Large-Signal Output 2V/div Large-Signal Output Small-Signal Error 2V/div 1mV/div 1mV/div Small-Signal Error 5V/div LDAC Signal Code Change: 04000h to 3C000h Output Loaded with 10kW and 50pF to AGND 5V/div LDAC Signal Code Change: 3C000h to 04000h Output Loaded with 10kW and 50pF to AGND Time (2ms/div) Time (2ms/div) Figure 36. Figure 37. MAJOR CARRY GLITCH MAJOR CARRY GLITCH Gain = 1X Mode VREFH = +5V Code Change: 1FFFFh to 20000h Output Loaded with 10kW and 50pF to AGND Gain = 1X Mode VREFH = +5V Integrated Glitch Energy (28nV-s) 100mV/div VOUT Signal 100mV/div VOUT Signal Integrated Glitch Energy (38nV-s) 5V/div LDAC Signal 5V/div Time (2ms/div) Code Change: 20000h to 1FFFFh Output Loaded with 10kW and 50pF to AGND Time (2ms/div) Figure 38. 18 LDAC Signal Figure 39. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. MAJOR CARRY GLITCH MAJOR CARRY GLITCH Code Change: 1FFFFh to 20000h Output Loaded with 10kW and 50pF to AGND Gain = 1X Mode VREFH = +2.5V Gain = 1X Mode VREFH = +2.5V Integrated Glitch Energy (15nV-s) 100mV/div VOUT Signal 100mV/div VOUT Signal Integrated Glitch Energy (17nV-s) 5V/div LDAC Signal 5V/div Code Change: 20000h to 1FFFFh Output Loaded with 10kW and 50pF to AGND Time (2ms/div) Figure 40. Figure 41. OUTPUT NOISE DENSITY vs FREQUENCY LOW-FREQUENCY OUTPUT NOISE (0.1Hz to 10Hz) 180 DAC Code Set to 20000h Output Unloaded 160 140 120 2mV/div Output Voltage Noise Density (nV/ÖHz) Time (2ms/div) LDAC Signal 100 80 60 Gain = 2X Mode 40 20 Gain = 1X Mode 0 1 10 100 1k Frequency (Hz) 10k 100k Figure 42. Time (1s/div) Figure 43. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 19 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +2.7V At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 3.0 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2.0 TA = +25°C TA = +25°C 1.5 2.0 DNL Error (LSB) INL Error (LSB) 1.0 1.0 0 -1.0 0.5 0 -0.5 -1.0 -2.0 -1.5 -3.0 -2.0 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code Figure 44. Figure 45. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 3.0 2.0 TA = -40°C TA = -40°C 1.5 2.0 DNL Error (LSB) INL Error (LSB) 1.0 1.0 0 -1.0 0.5 0 -0.5 -1.0 -2.0 -1.5 -3.0 -2.0 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code Figure 46. Figure 47. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 3.0 2.0 TA = +105°C TA = +105°C 1.5 2.0 DNL Error (LSB) INL Error (LSB) 1.0 1.0 0 -1.0 0.5 0 -0.5 -1.0 -2.0 -1.5 -3.0 -2.0 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code 0 Figure 48. 20 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code Figure 49. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE 4.0 2.0 3.0 1.5 INL Max DNL Max 1.0 DNL Error (LSB) INL Error (LSB) 2.0 1.0 0 INL Min -1.0 DNL Min -0.5 -1.0 -3.0 -1.5 -2.0 0 0.5 1.0 1.5 2.0 Reference Voltage (V) 2.5 3.0 0 0.5 1.0 1.5 2.0 Reference Voltage (V) Figure 50. Figure 51. AVDD SUPPLY CURRENT vs TEMPERATURE REFERENCE CURRENT vs DIGITAL INPUT CODE 2.5 3.0 1.00 1000 900 800 700 VREF = 1.25V, Gain = 2X Mode 600 500 400 300 200 100 VREFH = 2.5V VREFL = 0V 0.75 VREF = 2.5V, Gain = 1X Mode Reference Current (mA) AVDD Supply Current (mA) 0 -2.0 -4.0 VREFH Current 0.50 0.25 0 VREFL Current -0.25 -0.50 -0.75 DAC Code Set to 3FFFFh 0 -1.00 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 0 125 65536 131072 Digital Input Code 196608 Figure 52. Figure 53. REFERENCE CURRENT vs DIGITAL INPUT CODE (GAIN = 2X MODE) OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY 1.00 262144 3.0 DAC Loaded with 3FFFFh, VREFH = 2.7V VREFH = 1.25V VREFL = 0V 0.75 0.50 VREFH Current 0.25 0 2.5 Output Voltage (V) Reference Current (mA) 0.5 VREFL Current -0.25 DAC Loaded with 3FFFFh, VREFH = 2.5V 2.0 1.5 1.0 -0.50 0.5 -0.75 DAC Loaded with 00000h 0 -1.00 0 65536 131072 Digital Input Code 196608 262144 0 Figure 54. 3 6 9 I(SOURCE/SINK) (mA) 12 15 Figure 55. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 21 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AVDD Rail) 2.70 OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AGND Rail) 0.25 DAC Loaded with 3FFFFh 0.20 2.60 DAC Loaded with 3F800h 2.55 DAC Loaded with 3F000h 2.50 Output Voltage (V) Output Voltage (V) 2.65 DAC Loaded with 3E000h DAC Loaded with 3FFFFh, VREFH = 2.5V 2.45 DAC Loaded with 01000h 0.15 0.10 0.05 VREFH = 2.7V, unless otherwise noted. 2.40 DAC Loaded with 00000h 0 0 1 DAC Loaded with 02000h DAC Loaded with 00800h 2 3 ISOURCE (mA) 4 5 0 1 2 3 4 5 ISINK (mA) Figure 56. Figure 57. LARGE SIGNAL SETTLING TIME LARGE SIGNAL SETTLING TIME Large-Signal Output Code Change: 3FFFFh to 00000h Output Loaded with 10kW and 50pF to AGND 1V/div Large-Signal Output Small-Signal Error 1V/div 1mV/div 1mV/div Small-Signal Error 5V/div LDAC Signal Code Change: 00000h to 3FFFFh Output Loaded with 10kW and 50pF to AGND 5V/div LDAC Signal Time (2ms/div) Time (2ms/div) Figure 58. Figure 59. LARGE SIGNAL SETTLING TIME LARGE SIGNAL SETTLING TIME Large-Signal Output 1V/div Large-Signal Output Small-Signal Error 1V/div 1mV/div 1mV/div Small-Signal Error 5V/div LDAC Signal Code Change: 04000h to 3C000h Output Loaded with 10kW and 50pF to AGND 5V/div LDAC Signal Time (2ms/div) Time (2ms/div) Figure 60. 22 Code Change: 3C000h to 04000h Output Loaded with 10kW and 50pF to AGND Figure 61. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. MAJOR CARRY GLITCH MAJOR CARRY GLITCH Code Change: 1FFFFh to 20000h Output Loaded with 10kW and 50pF to AGND Gain = 1X Mode VREFH = +2.5V Gain = 1X Mode VREFH = +2.5V Integrated Glitch Energy (17.5nV-s) 100mV/div VOUT Signal 100mV/div VOUT Signal Integrated Glitch Energy (16.5nV-s) 5V/div LDAC Signal 5V/div Time (2ms/div) LDAC Signal Code Change: 20000h to 1FFFFh Output Loaded with 10kW and 50pF to AGND Time (2ms/div) Figure 62. Figure 63. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 23 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The DAC9881 is a single-channel, 18-bit, serial-input, voltage-output digital-to-analog converter (DAC). The architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier that serves as a buffer, as shown in Figure 64. The on-chip output buffer allows rail-to-rail output swings while providing a low output impedance to drive loads. The DAC9881 operates from a single analog power supply that ranges from 2.7V to 5.5V, and typically consumes 850µA when operating with a 5V supply. Data are written to the device in a 24-bit word format, via an SPI serial interface. To enable compatibility with 1.8V, 3V, or 5V logic families, an IOVDD supply pin is provided. This pin allows the DAC9881 input and output logic to be powered from the same logic supply used to interface signals to and from the device. Internal voltage translators are included in the DAC9881 to interface digital signals to the device core. See Figure 65 for the basic configuration of the DAC9881. To ensure a known power-up state, the DAC9881 is designed with a power-on reset function. Upon power-up, the DAC9881 is reset to either zero-scale or midscale depending on the state of the RSTSEL pin. A harrdware reset can be performed by using the RST and RSTSEL pins. RFB(1) RFB R VOUT 2R 2R 2R 2R 2R 2R 2R 2R 2R 5kW VREFH 5kW NOTE: (1) RFB = 5kW for gain = 1 RFB = 10kW for gain = 2. VREFH-F VREFH-S VREFL-F VREFL-S Figure 64. DAC9881 Architecture 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 SDOSEL Chip-Select CS 19 SDOSEL 20 AVDD 21 22 SDO 4 15 14 5 (Thermal Pad) VOUT VREFH-S 13 RST Reset DAC Registers USB/BTC GAIN RSTSEL NC 12 6 7 VREFL-S DAC9881 PDN NC AVDD 16 3 11 AGND 17 VREFH-F Load DAC Registers 2 10 LDAC 18 9 Serial Data In 1 VREFL-F SDI 8 SCLK Clock 23 1mF IOVDD + 24 0.1mF DGND 1mF RFB + 1.8V to 5V 0.1mF Serial Data Out +5V 0V to +5.0V External Reference +5.0000V Figure 65. Basic Configuration Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 25 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com ANALOG OUTPUT The DAC9881 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 66), thus ensuring an accurate output voltage. The output buffer VOUT and RFB pins are provided so that the output op amp buffer feedback can be connected at the load. Without a driven load, the DAC9881 output typically swings to within 15mV of the AGND and AVDD supply rails. Because of the high accuracy of these DACs, system design problems such as grounding and wiring resistance become very important. A 18-bit converter with a 5V full-scale range has an LSB value of 19µV. The DAC9881 has a typical feedback resistor current of 0.5mA; thus, a series wiring resistance of only 100mΩ (RW1) causes a voltage drop of 50µV. In terms of a system layout, the resistivity of a typical 1-ounce copper-clad printed circuit board (PCB) is 0.5mΩ per square. For a 0.5mA current, a 0.25mm wide printed circuit conductor 25mm long results in a voltage drop of 25µV. Note that the wiring resistance of RW2 is not critical as long as the feedback resistor (RFB) is connected at the driven load. SDOSEL Chip-Select 19 CS AVDD SDOSEL 20 23 21 SDO 4 15 5 14 (Thermal Pad) 8 VOUT VREFH-S RW2 13 RST Reset DAC Registers USB/BTC GAIN RSTSEL NC 12 6 7 VREFL-S 16 DAC9881 PDN NC AVDD 3 11 AGND 17 VREFH-F Load DAC Registers 2 10 LDAC 18 9 Serial Data In 1 VREFL-F SDI RFB SCLK Clock 22 1mF IOVDD + 24 0.1mF DGND 1mF RW1 + 1.8V to 5V 0.1mF Serial Data Out +5V VOUT External Reference +5.0000V Figure 66. Analog Output Closed-Loop Configuration (RW1 and RW2 represent wiring resistance) 26 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 REFERENCE INPUTS The reference high input, VREFH, can be set to any voltage in the range of 1.25V to AVDD. The reference low input, VREFL, can be set to any voltage in the range of –0.2V to +0.2V (to provide a small offset to the output of the DAC9881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from approximately 0.5mA to 1mA in the gain = 1X mode of operation. The reference high and low inputs appear as variable loads to the external reference circuit. If the external references can source or sink the required current, and if low impedance connections are made to the VREFH and VREFL pins, external reference buffers are not required. Figure 65 shows a simple configuration of the DAC9881 using external references without force and sense reference buffers. Kelvin sense connections for the reference high and low are included on the DAC9881. When properly used with external reference buffer op amps, these reference Kelvin sense pins ensure that the driven reference high and low voltages remain stable versus varying reference load currents. Figure 67 shows an example of a reference force and sense configuration of the DAC9881 operating from a single analog reference voltage. Both the VREFL and VREFH reference voltages are set to levels of 100mV from the DAC9881 supply rails, and are derived from a +5V external reference. Figure 68 illustrates the effect of not using the reference force and sense buffers to drive the DAC9881 VREFL and VREFH pins. Figure 69 shows the improvement when using the reference buffers. A slight degradation in INL and DNL performance is seen without the use of the force and sense buffer configuration. SCLK SDI LDAC +5V AGND External Reference +5.0000V AVDD OPA2350 VREFL-S 2 3 4 DAC9881 5 6 11 12 NC 10 9 RFB VREFH-F 96kW VOUT VREFH-S 1000pF VREFL-F +4.900V 8 50W 7 2200pF 2kW 1 +0.100V 50W 2kW 2200pF 1000pF NOTE: VREFL can be connected to AGND if VREFL is not biased. 0 32768 65536 98304 131072 163840 196608 229376 262144 LE (LSB) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 DLE (LSB) Figure 67. Buffered References (VREFH = +4.900V and VREFL = 100mV). 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 32768 65536 98304 131072 163840 196608 229376 262144 Digital Input Code Digital Input Code Figure 68. Linearity and Differential Linearity Error for Figure 65 without Reference Buffers Figure 69. Linearity and Differential Linearity Error for Figure 67 with Reference Buffers Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 27 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com OUTPUT RANGE The maximum output range of the DAC9881 is VREFL to (VREFH – VREFL) × G, where G is the output buffer gain set by the GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin is connected to IOVDD, the output buffer gain = 2. The output range must not be greater than AVDD; otherwise, output saturation occurs. The DAC9881 output transfer function is given in Equation 1: V - VREFL VOUT = REFH ´ CODE ´ Buffer Gain + VREFL 262144 (1) Where: CODE = 0 to 262143. This is the digital code loaded to the DAC. Buffer Gain = 1 or 2 (set by the GAIN pin). VREFH = reference high voltage applied to the device. VREFL = reference low voltage applied to the device. INPUT DATA FORMAT The USB/BTC pin defines the input data format. When this pin is connected to IOVDD, the input data format is straight binary, as shown in Table 1. When this pin is connected to DGND, the input data format is twos complement, as shown in Table 2. Table 1. Output vs Straight Binary Code USB CODE 5V RANGE DESCRIPTION 3FFFFh +4.99998 +Full-Scale – 1LSB 30000h +3.75000 3/4-Scale 20000h +2.50000 Midscale 10000h +1.25000 1/4-Scale 00000h 0.00000 Zero-Scale Table 2. Output vs Twos Complement Code BTC CODE 5V RANGE DESCRIPTION 1FFFFh +4.99998 +Full-Scale – 1LSB 10000h +3.75000 3/4-Scale 00000h +2.50000 Midscale 3FFFFh +2.49998 Midscale – 1LSB 30000h +1.25000 1/4-Scale 20000h 0.00000 Zero-Scale POWER DOWN The DAC9881 has a hardware power-down function. When the PDN pin is high, the device is in power-down mode. When the device is in power-down, the VOUT pin is connected to ground through an internal 10kΩ resistor, but the contents of the input register and the DAC latch do not change and SPI communication remains active. When the PDN pin returns low, the device returns to normal operation. HARDWARE RESET When the RST pin is low, the device is in hardware reset mode, and the input register and DAC latch are set to the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode, and the input register and DAC latch maintain the reset value until new data are written. 28 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 POWER-ON RESET The DAC9881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and the output from the VOUT pin are set to the value defined by the RSTSEL pin. PROGRAM RESET VALUE After a power-on reset or a hardware reset, the output voltage from the VOUT pin and the values of the input register and DAC latch are determined by the status of the RSTSEL pin and the input data format, as shown in Table 3. Table 3. Reset Value RSTSEL PIN USB/BTC PIN INPUT FORMAT VOUT VALUE OF INPUT REGISTER AND DAC LATCH DGND IOVDD IOVDD IOVDD Straight Binary 0 00000h Straight Binary Midscale DGND 20000h DGND Twos Complement Midscale 00000h IOVDD DGND Twos Complement 0 20000h SERIAL INTERFACE The DAC9881 is controlled by a versatile three-wire serial interface that operates at clock rates of up to 50MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. Input Shift Register Data are loaded into the device as a 24-bit word under the control of the serial clock input, SCLK. The timing diagrams for this operation are shown in the Timing Diagram section. The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while CS is low. When CS is high, the SCLK and SDI signals are blocked out, and SDO is in high-Z status. To start the serial data transfer, CS should be taken low, observing the minimum delay from CS falling edge to SCLK rising edge, t2. After CS goes low, serial input data from SDI are clocked into the device input shift register on the rising edges of SCLK for 24 or more clock pulses. If a frame contains less than 24 bits of data, the frame is invalid. Invalid input data are not written into the input register and DAC, although the input register and DAC will continue to hold data from the preceding valid data cycle. If more than 24 bits of data are transmitted in one frame, the last 24 bits are written into the shift register and DAC. CS may be taken high after the rising edge of the 24th SCLK pulse, observing the minimum SCLK rising edge to CS rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and DAC output can be updated by taking the LDAC pin low. Table 4 shows the input shift register data word format. D17 is the MSB of the 18-bit DAC data. Table 4. Input Shift Register Data Word Format BIT B23 B22 B21 B20 B19 B18 B17 (MSB) B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) DATA X (1) X X X X X D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (1) X = don't care. Stand-Alone Mode When the SDOSEL pin is tied to IOVDD, the interface is in Stand-Alone mode. This mode provides serial readback for diagnostic purposes. The new input data (24 bits) are clocked into the device shift register and the existing data in the input register (24 bits) are shifted out from the SDO pin. If more than 24 SCLKs are clocked when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last 24 bits of input data remain in the shift register. If less than 24 SCLKs are clocked while CS is low, the data from the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further details. Daisy-Chain Mode When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several DACs, the SDO pin may be used to daisy-chain several devices together. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 29 DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 24 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the SDI input on the next DAC in the chain, a multi-DAC interface is constructed. 24 clock pulses are required for each DAC in the chain. Therefore, the total number of clock cycles must be equal to (24 x N), where N is the total number of devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action prevents any further data from being clocked into the input shift register. The contents in the shift registers are transferred into the relevant input registers on the rising edge of the CS signal. A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC registers, and all analog outputs update simultaneously. DOUBLE-BUFFERED INTERFACE The DAC9881 has a double-buffered interface consisting of two register banks: the input register and the DAC latch. The input register is connected directly to the input shift register and the digital code is transferred to the input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the resistor R-2R ladder. The contents of the DAC latch defines the output from the DAC. Access to the DAC latch is controlled by the LDAC pin. When LDAC is high, the DAC latch is latched and the input register can change state without affecting the contents of the DAC latch. When LDAC is low, however, the DAC latch becomes transparent and the contents of the input register is transferred to the DAC register. Load DAC Pin (LDAC) LDAC transfers data from the input register to the DAC latch (and, therefore, updates the DAC output). The contents of the DAC latch (and the output from DAC) can be changed in two ways, depending on the status of LDAC. Synchronous Mode When LDAC is tied low, the DAC latch updates as soon as new data are transferred into the input register after the rising edge of CS. Asynchronous Mode When LDAC is high, the DAC latch is latched. The DAC latch (and DAC output) is not updated at the same time that the input register is written to. When LDAC goes low, the DAC latch updates with the contents of the input register. 1.8V TO 5V LOGIC INTERFACE All digital input and output pins are compatible with any logic supply voltage between 1.8V and 5V. Connect the interface logic supply voltage to the IOVDD pin. Although timing is specified down to 2.7V (see the Timing Characteristics), IOVDD can operate as low as 1.8V, but with degraded timing and temperature performance. For the lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND. POWER-SUPPLY SEQUENCE For the device to work properly, IOVDD must not come up before AVDD, and the reference voltage must come up after the AVDD supply. Additionally, because the DAC input shift register is not reset during a power-on reset or hardware reset, the CS pin must not be unintentionally asserted during power-up of the device. To avoid improper power-up, it is recommended that the CS and LDAC pins be connected to IOVDD through pull-up resistors. To ensure that the electrostatic discharge (ESD) protection circuitry of this device is not activated, all other digital pins must be held at ground potential until IOVDD is applied. 30 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 APPLICATION INFORMATION BIPOLAR OPERATION USING THE DAC9881 The DAC9881 is designed for single-supply operation; however, a bipolar output is also possible using the circuit shown in Figure 70. This circuit gives a bipolar output voltage of VBIP. When GAIN = 1, VBIP can be calculated using Equation 2: VBIP(CODE) = 1 + R R3 R3 CODE - 3 ´ VREF + ´ R1 R2 R 1 262144 (2) Where: VBIP(CODE) = bipolar output voltage versus CODE from the OPA211. CODE = 0 to 262143. This is the digital code loaded to the DAC. VREF = reference high voltage applied to the DAC9881. By first choosing a value for resistor R3, R1 and R2 can be determined by Equation 3 and Equation 4, respectively: V R1 = REF ´ R3 VBIP (3) VREF ´ R3 R2 = VBIP - VREF (4) Where: VBIP= peak desired output voltage for bipolar output. VREF = reference high voltage applied to the DAC9881. NOTE: VBIP ≥ VREF. R3 = OPA211 feedback resistor chosen by user. Note that R2 is not required in the circuit of Figure 70 for bipolar output voltage ranges equal to ±VREF. Using the previous equations, and with VREF = 5V and R3 set to 10kΩ, a ±8V output span can be achieved with R1 calculated to be 6.25kΩ and R2 to be 16.67kΩ. Similarly, a near ±15V rail-to-rail output can be achieved with R1 calculated to be 3.33kΩ and R2 calculated to be 5kΩ. VREFL +15V DAC9881 VOUT VREFH R2 R1 OPA211 VBIP -15V R3 VREF NOTE: Some pins omitted for clarity. Figure 70. Bipolar Operation Using the DAC9881 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC9881 31 PACKAGE OPTION ADDENDUM www.ti.com 2-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC9881SBRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC9881SBRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC9881SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC9881SRGET ACTIVE VQFN RGE 24 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Aug-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC9881SBRGER VQFN RGE 24 DAC9881SBRGET VQFN RGE DAC9881SRGER VQFN RGE DAC9881SRGET VQFN RGE SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 24 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 24 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Aug-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC9881SBRGER VQFN RGE 24 3000 340.5 333.0 20.6 DAC9881SBRGET VQFN RGE 24 250 340.5 333.0 20.6 DAC9881SRGER VQFN RGE 24 3000 340.5 333.0 20.6 DAC9881SRGET VQFN RGE 24 250 340.5 333.0 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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