INTEGRATED CIRCUITS 74ALVT16841 2.5V/3.3V ALVT 20-bit bus interface latch (3-State) Product specification Supersedes data of 1996 Aug 28 IC23 Data Handbook 1998 Feb 13 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) FEATURES 74ALVT16841 DESCRIPTION • High speed parallel latches • 5V I/O Compatible • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying The 74ALVT16841 Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V. The 74ALVT16841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched. parity • Power-up 3-State • Power-up reset • Ideal where high speed, light loading, or increased fan-in are Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state. required with MOS microprocessors • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C PARAMETER TYPICAL UNIT 2.5V 3.3V 1.8 2.1 1.5 1.7 ns tPLH tPHL Propagation delay nDx to nQx CL = 50pF CIN Input capacitance DIR, OE VI = 0V or VCC 3 3 pF COut Output pin capacitance VI/O = 0V or VCC 9 9 pF ICCZ Total supply current Outputs disabled 40 70 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16841 DL AV16841 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16841 DGG AV16841 DGG SOT364-1 1998 Feb 13 2 853-1868 18961 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) LOGIC SYMBOL 55 54 74ALVT16841 PIN CONFIGURATION 52 51 49 48 47 1D0 1D1 1D2 1D3 1D4 1D5 1D6 45 44 43 1D7 1D8 1D9 1OE 1 56 1LE 1Q0 2 55 1D0 56 1LE 1Q1 3 54 1D1 1 1OE GND 4 53 GND 1Q2 5 52 1D2 1Q3 6 51 1D3 VCC 7 50 VCC 1Q4 8 49 1D4 1Q5 9 48 1D5 1Q6 10 47 1D6 GND 11 46 GND 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2 3 5 6 8 9 10 12 13 14 42 41 40 38 37 36 34 33 31 30 2D0 2D1 2D2 2D3 2D4 2D5 2D6 29 28 2D7 2D8 2D9 2LE 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 15 16 17 19 20 21 23 24 26 1Q9 14 43 1D9 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 27 SH00023 LOGIC SYMBOL (IEEE/IEC) 1 56 EN2 C1 20 37 2D4 21 36 2D5 VCC 22 35 VCC 23 34 2D6 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2Q9 27 30 2D9 2OE 28 29 2LE 28 EN4 2Q6 29 C3 2Q7 55 1D 2∇ 2 54 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 42 SA00076 14 3D 4∇ 15 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 SA00077 1998 Feb 13 2Q4 2Q5 3 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) PIN DESCRIPTION PIN NUMBER 74ALVT16841 FUNCTION TABLE SYMBOL FUNCTION INPUTS 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 1D0 – 1D9 2D0 – 2D9 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1Q0 – 1Q9 2Q0 – 2Q9 Data outputs 1, 28 1OE, 2OE Output enable inputs (active-Low) 56, 29 1LE, 2LE Latch enable inputs (active rising edge) 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage Data inputs OUTPUTS OPERATING MODE nOE nLE nDx nQ0 – nQ9 L L H H L H L H Transparent L L ↓ ↓ l h L H Latched H X X Z High impedance L L X NC Hold H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE transition ↓ = High-to-Low LE transition NC= No change X = Don’t care Z = High impedance “off” state LOGIC DIAGRAM nD0 nD2 nD1 D L D Q L D D Q nD4 nD3 L Q L nD5 D Q L D D Q nD7 nD6 L Q L nD8 D D Q L nD9 Q L D Q L Q nLE nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 SH00024 1998 Feb 13 4 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC CONDITIONS RATING UNIT –0.5 to +4.6 V –50 mA –1.2 to +7.0 V VO < 0 –50 mA Output in Off or High state –0.5 to +7.0 V Output in Low state 128 Output in High state –64 DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VI < 0 VOUT DC output voltage3 IOUT O DC output current Tstg Storage temperature range mA °C –65 to 150 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC 2.5V RANGE LIMITS PARAMETER DC supply voltage 3.3V RANGE LIMITS UNIT MIN MAX MIN MAX 2.3 2.7 3.0 3.6 V 0 5.5 0 5.5 V VI Input voltage VIH High-level input voltage VIL Input voltage 0.7 0.8 V IOH High-level output current –8 –32 mA Low-level output current 8 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 24 64 IOL ∆t/∆v Input transition rise or fall rate; Outputs enabled Tamb Operating free-air temperature range 1998 Feb 13 1.7 2.0 10 –40 5 +85 –40 V mA 10 ns/V +85 °C Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VOH High-level out output ut voltage VOL VRST VCC = 3.0V; IIK = –18mA 0 to 3 6V; IOH = –100µA VCC = 3 3.0 3.6V; VCC = 3.0V; IOH = –32mA Low–level out output ut voltage Power-up output low voltage6 Input In ut leakage current IHOLD Off current Bus Hold current Data inputs7 –0.85 –1.2 –0 2 VCC–0.2 VCC 2.0 2.3 0.07 0.2 0.25 0.4 VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55 VCC = 3.6V; IO = 1mA; VI = VCC or GND 0.55 0.1 ±1 VCC = 0 or 3.6V; VI = 5.5V 0.1 10 VCC = 3.6V; VI = VCC 0.5 1 0.1 -5 0.1 ±100 Control pins Data pins ins4 VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V 75 130 VCC = 3V; VI = 2.0V –75 –140 VCC = 0V to 3.6V; VCC = 3.6V ±500 UNIT V V VCC = 3.0V; IOL = 16mA VCC = 3.6V; VI = 0V IOFF MAX VCC = 3.0V; IOL = 100µA VCC = 3.6V; VI = VCC or GND II TYP1 V V µA µA µA Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 3.0V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC OE/OE = Don’t care 1 ±100 µA IOZH 3-State output High current VCC = 3.6V; VO = 3.0V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 3.6V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.07 0.1 IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 3.2 7 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 0.07 0.1 VCC = 3V to 3.6V; One input at VCC–0.6V, Other inputs at VCC or GND 0.04 0.4 mA mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 13 6 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 AC CHARACTERISTICS (3.3V 0.3V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +3.3V ±0.3V WAVEFORM UNIT MIN TYP MAX tPLH tPHL Propagation delay nDx to nQx 2 0.5 0.5 1.5 1.7 2.5 2.7 ns tPLH tPHL Propagation delay nLE to nQx 1 1.0 1.5 2.1 3.4 3.2 5.5 ns tPZH tPZL Output enable time to High and Low level 4 5 1.0 0.5 2.3 1.3 3.6 2.3 ns tPHZ tPLZ Output disable time from High and Low level 4 5 1.5 1.5 3.2 2.8 4.9 4.3 ns NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC SETUP REQUIREMENTS (3.3V 0.3V RANGE) GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = -40 to +85oC VCC = +3.3V ±0.3V Min Typ UNIT ts(H) ts(L) Setup time, High or Low nDx to nLE 3 1.0 1.0 0 0 ns th(H) th(L) Hold time, High or Low nDx to nLE 3 1.2 1.2 0.1 0.3 ns tw(H) nLE pulse width High 1 1.5 1998 Feb 13 7 ns Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VOH High-level out output ut voltage VCC = 2.3V; IIK = –18mA VCC = 2.3 to 3.6V; IOH = –100µA VCC = 2.3V; IOH = –8mA VOL Low-level output voltage VRST Power-up output low voltage7 Input In ut leakage current MAX –0.85 –1.2 VCC–0.2 VCC 1.8 2.1 0.07 0.2 VCC = 2.3V; IOL = 24mA 0.3 0.5 VCC = 2.3V; IOL = 8mA 0.4 VCC = 2.7V; IO = 1mA; VI = VCC or GND 0.55 0.1 ±1 VCC = 0 or 2.7V; VI = 5.5V 0.1 10 VCC = 2.7V; VI = VCC 0.1 1 Control pins Data pins ins4 VCC = 2.7V; VI = 0 UNIT V V VCC = 2.3V; IOL = 100µA VCC = 2.7V; VI = VCC or GND II TYP1 V V µA 0.1 -5 Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1 100 Bus Hold current VCC = 2.3V; VI = 0.7V 90 Data inputs6 VCC = 2.3V; VI = 1.7V –10 Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 2.3V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don’t care 1 100 µA IOZH 3-State output High current VCC = 2.7V; VO = 2.3V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 2.7V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1 2.3 4.5 0.04 0.1 0.04 0.4 IOFF IHOLD IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = Additional supply current per input pin2 VCC = 2.3V to 2.7V; One input at VCC–0.6V, Other inputs at VCC or GND 05 µA µA mA mA NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ± 0.2V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 1998 Feb 13 8 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 AC CHARACTERISTICS (2.5V 0.2V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +2.5V ±0.2V WAVEFORM UNIT MIN TYP MAX tPLH tPHL Propagation delay nDx to nQx 2 0.5 0.5 1.8 2.1 3.0 3.6 ns tPLH tPHL Propagation delay nLE to nQx 1 1.0 2.0 2.7 4.2 4.3 6.5 ns tPZH tPZL Output enable time to High and Low level 4 5 1.5 0.5 3.0 1.8 4.0 3.2 ns tPHZ Output disable time tPLZ from High and Low level NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 4 5 1.5 1.0 3.1 2.4 4.5 3.8 ns AC SETUP REQUIREMENTS (2.5V 0.2V RANGE) GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER UNIT Min Typ 3 0.5 1.5 0 0.2 ns Hold time, High or Low nDx to nLE 3 1.8 2.0 0 0.8 ns nLE pulse width High 1 1.5 ts(H) ts(L) Setup time, High or Low nDx to nLE th(H) th(L) tw(H) 1998 Feb 13 WAVEFORM Tamb = -40 to +85oC VCC = +2.5V ±0.2V 9 ns Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 AC WAVEFORMS VM = 1.5V at VCC w 3.0V; VM = VCC/2 at VCC v 2.7V VX = VOL + 0.3V at VCC w 3.0V; VX = VOL + 0.15V at VCC v 2.7V VY = VOH – 0.3V at VCC w 3.0V; VY = VOH – 0.15V at VCC v 2.7V VM nLE VM 3.0V or VCC whichever is less VM 3.0V or VCC whichever is less nOE VM VM 0V 0V tPZH tw(H) tPHL tPHZ tPLH VOH VOH VM nQx VY VM VM nQx 0V VOL SH00007 SA00078 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 1. Propagation Delay, Latch Enable Input to Output, and Enable Pulse Width 3.0V or VCC whichever is less nOE VM nDx INPUT 3.0V or VCC whichever is less VM VM 0V tPZL 0V tPLH VM SH00008 Waveform 2. Propagation Delay for Data to Outputs ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ VM VM 3.0V or VCC whichever is less VM 0V ts(H) nLE th(H) VM ts(L) th(L) VM 3.0V or VCC whichever is less 0V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00080 Waveform 3. Data Setup and Hold Times 1998 Feb 13 0V Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level SA00079 VM VX VOL 0V nDx 3.0V or VCC VM 3.0V or VCC whichever is less VM tPLZ nQx tPHL nQx OUTPUT VM 10 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus interface latch (3-State) 74ALVT16841 TEST CIRCUIT AND WAVEFORM 6.0V or VCC x 2 VCC Open VIN VOUT PULSE GENERATOR tW 90% RL GND VM NEGATIVE PULSE 10% 0V tTHL (tF) CL VIN VM 10% D.U.T. RT 90% tTLH (tR) tTLH (tR) RL 90% POSITIVE PULSE Test Circuit for 3-State Outputs tTHL (tF) VIN 90% VM VM 10% 10% tW 0V SWITCH POSITION TEST SWITCH tPLZ/tPZL 6V or VCC x 2 tPLH/tPHL Open tPHZ/tPZH GND INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY Amplitude RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. 74ALVT16 Rep. Rate 3.0V or VCC whichever v10MHz is less tW 500ns tR tF v2.5ns v2.5ns RT = Termination resistance should be equal to ZOUT of pulse generators. SW00025 1998 Feb 13 11 Philips Semiconductors Product specification 2.5V/3.3V ALVT 20-bit bus interface latch (3-State) SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Feb 13 12 74ALVT16841 SOT371-1 Philips Semiconductors Product specification 2.5V/3.3V ALVT 20-bit bus interface latch (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Feb 13 13 74ALVT16841 SOT364-1 Philips Semiconductors Product specification 2.5V/3.3V ALVT 20-bit bus interface latch (3-State) 74ALVT16841 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 05-96 9397-750-03578