NSC DS99R106VSX 3-40mhz dc-balanced 24-bit lvds serializer and deserializer Datasheet

DS99R105/DS99R106
3-40MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
■ Internal DC Balancing encode/decode – Supports AC-
The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream
with embedded clock information. This single serial stream
simplifies transferring a 24-bit bus over PCB traces and cable
by eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size
and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on
the high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for
the operating frequency range EMI is further reduced.
■
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled
interconnects.
Features
■ 3 MHz–40 MHz clock embedded and DC-Balancing 24:1
and 1:24 data transmissions
■ Capable to drive shielded twisted-pair cable
■ User selectable clock edge for parallel data on both
Transmitter and Receiver
■
■
■
■
■
■
■
■
■
■
■
■
■
■
coupling interface with no external coding required
Individual power-down controls for both Transmitter and
Receiver
Embedded clock CDR (clock and data recovery) on
Receiver and no external source of reference clock
needed
All codes RDL (random data lock) to support livepluggable applications
LOCK output flag to ensure data integrity at Receiver side
Balanced TSETUP/THOLD between RCLK and RDATA on
Receiver side
PTO (progressive turn-on) LVCMOS outputs to reduce
EMI and minimize SSO effects
All LVCMOS inputs and control pins have internal
pulldown
On-chip filters for PLLs on Transmitter and Receiver
Integrated 100Ω input termination on Receiver
4 mA Receiver output drive
48-pin TQFP and 48-pin LLP packages
Pure CMOS .35 μm process
Power supply range 3.3V ± 10%
Temperature range 0°C to +70°C
8 kV HBM ESD tolerance
Block Diagram
20208101
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
202081
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DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
October 2007
DS99R105/DS99R106
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DS99R105
Supply Voltage (VDD)
−0.3V to +4V
LVCMOS/LVTTL Input Voltage
−0.3V to (VDD +0.3V)
LVCMOS/LVTTL Output Voltage
−0.3V to (VDD +0.3V)
LVDS Receiver Input Voltage
−0.3V to 3.9V
LVDS Driver Output Voltage
−0.3V to 3.9V
LVDS Output Short Circuit Duration
10 ms
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity Package
De-rating:
48L TQFP
1/θJA °C/W above +25°C
θJA
45.4 (4L*); 75.0 (2L*)°C/W
θJC
21.1°C/W
θJA
28 (4L*); 79.1 (2L*)°C/W
θJC
3.71°C/W
*JEDEC
≥±8 kV
Recommended Operating
Conditions
Supply Voltage (VDD)
Operating Free Air
Temperature (TA)
Clock Rate
Supply Noise
21.0°C/W
θJA
3.7°C/W
ESD Rating (HBM)
45.8 (4L*); 75.4 (2L*) °C/W
θJC
DS99R106
28 (4L*); 79.1 (2L*) °C/W
θJC
DS99R106
DS99R105
θJA
1/θJA °C/W above +25°C
48L LLP
Min
3.0
Nom
3.3
Max
3.6
Units
V
0
3
+25
+70
40
±100
°C
MHz
mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
2.0
1.5
VDD
V
GND
1.5
0.8
V
−0.8
−1.5
V
LVCMOS/LVTTL DC SPECIFICATIONS
VIH
High Level Voltage
VIL
Low Level Input Voltage
VCL
Input Clamp Voltage
IIN
Input Current
ICL = −18 mA
(Note 8)
VIN = 0V or 3.6V
VOH
High Level Output Voltage
IOH = −4 mA
VOL
Low Level Output Voltage
IOL = +4 mA
IOS
Output Short Circuit Current
VOUT = 0V
(Note 8)
IOZ
TRI-STATE® Output Current
RPWDNB, REN = 0V
VOUT = 0V or 2.4V
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Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
Rx: RPWDNB, RRFB,
REN
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
−10
±1
+10
µA
Rx: RPWDNB, RRFB,
REN
−20
±5
+20
µA
2.3
3.0
VDD
V
GND 0.33
0.5
V
Rx: ROUT[23:0], RCLK,
LOCK
Rx: ROUT[23:0], RCLK,
LOCK
2
−40
−70
−110
mA
−30
±0.4
+30
µA
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
+50
mV
LVDS DC SPECIFICATIONS
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
IIN
Input Current
RT
Differential Internal
Termination Resistance
VOD
Output Differential Voltage
(DOUT+)–(DOUT−)
VCM = +1.2V
Rx: RIN+, RIN−
−50
mV
VIN = +2.4V,
VDD = 3.6V
±300
µA
VIN = 0V, VDD = 3.6V
±300
µA
RL = 100Ω, w/o Pre-emphasis
VODSEL = L (Figure 10)
Tx: DOUT+, DOUT−
RL = 100Ω, w/o Pre-emphasis
VODSEL = H (Figure 10)
90
100
130
Ω
250
400
600
mV
450
750
1200
mV
4
50
mV
1.50
V
1
50
mV
ΔVOD
Output Differential Voltage
Unbalance
RL = 100Ω, w/o Pre-emphasis
VOS
Offset Voltage
RL = 100Ω, w/o Pre-emphasis
ΔVOS
Offset Voltage Unbalance
RL = 100Ω, w/o Pre-emphasis
IOS
Output Short Circuit Current
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
−2
−5
−8
mA
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
−7
−10
−13
mA
TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
−15
±1
+15
µA
40
80
mA
45
85
mA
40
85
mA
45
90
mA
1
100
µA
IOZ
TRI-STATE Output Current
1.00 1.25
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs
IDDT
Serializer (Tx)
Total Supply Current
(includes load current)
Serializer (Tx)
Total Supply Current
(includes load current)
IDDTZ
Serializer (Tx)
Supply Current Power-down
RL = 100Ω
Pre-emphasis = OFF
VODSEL = L
Checker-board pattern (Figure 1)
f = 40 MHz
RL = 100Ω
Pre-emphasis = ON
VODSEL = L
Checker-board pattern (Figure 1)
f = 40 MHz
RL = 100Ω
Pre-emphasis = OFF
VODSEL = H
Checker-board pattern (Figure 1)
f = 40 MHz
RL = 100Ω
Pre-emphasis = ON
VODSEL = H
Checker-board pattern (Figure 1)
f = 40 MHz
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
3
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DS99R105/DS99R106
Symbol
DS99R105/DS99R106
Symbol
IDDR
IDDRZ
Parameter
Conditions
Pin/Freq.
Deserializer (Rx)
Total Supply Current
(includes load current)
CL = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)
f = 40 MHz
Deserializer (Rx)
Total Supply Current
(includes load current)
CL = 8 pF LVCMOS Output
Random pattern
f = 40 MHz
Deserializer (Rx)
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
RIN+/ RIN- = 0V)
Min
Typ
Max
Units
95
mA
90
mA
1
50
µA
Min
Typ
Max
Units
25
T
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
tTCP
Transmit Clock Period
tTCIH
Transmit Clock High Time
(Figure 5)
tTCIL
Transmit Clock Low Time
tCLKT
TCLK Input Transition Time
(Figure 4)
tJIT
TCLK Input Jitter
(Note 9)
333
ns
0.4T 0.5T 0.6T
ns
0.4T 0.5T 0.6T
ns
3
6
ns
33
ps
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
LVDS Low-to-High Transition Time
tLHLT
LVDS High-to-Low Transition Time
tDIS
DIN (23:0) Setup to TCLK
tDIH
DIN (23:0) Hold from TCLK
tHZD
DOUT ± HIGH to TRI-STATE Delay
tLZD
DOUT ± LOW to TRI-STATE Delay
tZHD
DOUT ± TRI-STATE to HIGH Delay
tZLD
DOUT ± TRI-STATE to LOW Delay
tPLD
Serializer PLL Lock Time
RL = 100Ω, (Figure 7)
tSD
Serializer Delay
RL = 100Ω, (Figure 8)
VODSEL = L, TRFB = H
TxOUT_E_O
RL = 100Ω,
CL = 10 pF to GND
(Note 8)
TxOUT_Eye_Opening
(respect to ideal)
Min
Typ
RL = 100Ω, (Figure 3)
CL = 10 pF to GND
VODSEL = L
tLLHT
Max
Units
0.6
ns
0.6
ns
5
ns
5
ns
RL = 100Ω,
CL = 10 pF to GND
(Figure 6) (Note 5)
15
ns
15
ns
200
ns
200
ns
10
ms
3.5T + 2.85
3.5T
+ 10
ns
RL = 100Ω, (Figure 8)
VODSEL = L, TRFB = L
3.5T + 2.85
3.5T
+ 10
ns
3–40 MHz
(Figure 9) (Notes 9, 13)
0.68
UI
(Note 10)
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tRCP
Receiver out Clock Period
tRDC
RCLK Duty Cycle
tCLH
LVCMOS Low-to-High
Transition Time
tCHL
LVCMOS High-to-Low
Transition Time
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Conditions
Pin/Freq.
tRCP = tTCP
(Note 8)
RCLK
RCLK
CL = 8 pF
(lumped load)
(Figure 11)
ROUT [23:0],
LOCK, RCLK
4
Min
Typ
Max
Units
25
T
333
ns
45
50
55
%
2.5
3.5
ns
2.5
3.5
ns
Parameter
Conditions
Pin/Freq.
ROUT [7:0]
Typ
Max
Units
tROS
ROUT (7:0) Setup Data to
RCLK (Group 1)
tROH
ROUT (7:0) Hold Data to RCLK
(Group 1)
tROS
ROUT (15:8) Setup Data to
RCLK (Group 2)
tROH
ROUT (15:8) Hold Data to
RCLK (Group 2)
tROS
ROUT (23:16) Setup Data to
RCLK (Group 3)
tROH
ROUT (23:16) Hold Data to
RCLK (Group 3)
tHZR
HIGH to TRI-STATE Delay
tLZR
LOW to TRI-STATE Delay
tZHR
tZLR
tDD
Deserializer Delay
(Figure 12)
RCLK
tDRDL
Deserializer PLL Lock Time
from Powerdown
(Figure 14)
(Notes 7, 8)
3 MHz
5
50
ms
40 MHz
5
50
ms
Receiver INput TOLerance
Left
(Figure 16)
(Notes 6, 8, 10)
3 MHz–40 MHz
0.25
UI
RxIN_TOL_R Receiver INput TOLerance
Right
(Figure 16)
(Notes 6, 8, 10)
3 MHz–40 MHz
0.25
UI
RxIN_TOL_L
(Figure 15)
Min
(Figure 15)
ROUT [15:8],
LOCK
(Figure 15)
ROUT [23:16]
(Figure 13)
(0.40)*
(29/56)*tRCP
tRCP
ns
(0.40)*
(27/56)*tRCP
tRCP
ns
(0.40)*
tRCP
0.5*tRCP
ns
(0.40)*
tRCP
0.5*tRCP
ns
(0.40)*
(27/56)*tRCP
tRCP
ns
(0.40)*
(29/56)*tRCP
tRCP
ns
ROUT [23:0],
RCLK, LOCK
3
10
ns
3
10
ns
TRI-STATE to HIGH Delay
3
10
ns
TRI-STATE to LOW Delay
3
10
ns
[4+(3/56)]T [4+(3/56)]T
+5.9
+18.5
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.
Note 8: Specification is guaranteed by characterization and is not tested in production.
Note 9: tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
Note 10: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 11: Figures 1, 2, 8, 12, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 12: Figures 5, 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 13: TxOUT_E_O is affected by pre-emphasis value.
5
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DS99R105/DS99R106
Symbol
DS99R105/DS99R106
AC Timing Diagrams and Test Circuits
20208102
FIGURE 1. Serializer Input Checker-board Pattern
20208103
FIGURE 2. Deserializer Output Checker-board Pattern
20208104
FIGURE 3. Serializer LVDS Output Load and Transition Times
20208106
FIGURE 4. Serializer Input Clock Transition Times
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6
DS99R105/DS99R106
20208107
FIGURE 5. Serializer Setup/Hold Times
20208108
FIGURE 6. Serializer TRI-STATE Test Circuit and Delay
7
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DS99R105/DS99R106
20208109
FIGURE 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
20208110
FIGURE 8. Serializer Delay
20208115
FIGURE 9. Transmitter Output Eye Opening (TxOUT_E_O)
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8
DS99R105/DS99R106
20208117
VOD = (DOUT+) – (DOUT -)
Differential output signal is shown as (DOUT+) – (DOUT -), device in Data Transfer mode.
FIGURE 10. Serializer VOD Diagram
20208105
FIGURE 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times
20208111
FIGURE 12. Deserializer Delay
9
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DS99R105/DS99R106
20208113
Note: CL includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing
20208114
FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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10
DS99R105/DS99R106
20208112
FIGURE 15. Deserializer Setup and Hold Times
20208116
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
FIGURE 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
11
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DS99R105/DS99R106
DS99R105 Serializer Pin Descriptions
Pin #
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
4-1,
DIN[23:0]
48-44,
41-32,
29-25
LVCMOS_I
Transmitter Parallel Interface Data Inputs Pins. Tie LOW if unused, do not float.
10
LVCMOS_I
Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
TCLK
CONTROL AND CONFIGURATION PINS
9
TPWDNB
LVCMOS_I
Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs
are in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
18
DEN
LVCMOS_I
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-)
Outputs are in TRI-STATE, PLL still operational and locked to TCLK.
23
PRE
LVCMOS_I
PRE-emphasis select pin.
PRE = L; Pre-emphasis is enabled
PRE = H; Pre-emphasis is disabled
11
TRFB
LVCMOS_I
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
12
VODSEL
LVCMOS_I
VOD Level Select
VODSEL = L; LVDS Driver Output is ±400 mV (RL = 100Ω)
VODSEL = H; LVDS Driver Output is ±750 mV (RL = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
5
DCAOFF
LVCMOS_I
RESERVED – This pin MUST be tied LOW.
8
DCBOFF
LVCMOS_I
RESERVED – This pin MUST be tied LOW.
13
RESRVD
LVCMOS_I
RESERVED – This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
20
DOUT+
LVDS_O
Transmitter LVDS True (+) Output. This output is intended to be loaded with a 100 ohm load to
the DOUT+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
19
DOUT−
LVDS_O
Transmitter LVDS Inverted (-) Output This output is intended to be loaded with a 100 ohm load
to the DOUT- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
22
VDDDR
VDD
Analog Voltage Supply, LVDS Output Power
21
VSSDR
GND
Analog Ground, LVDS Output Ground
16
VDDPT0
VDD
Analog Voltage supply, VCO Power
17
VSSPT0
GND
Analog Ground, VCO Ground
14
VDDPT1
VDD
Analog Voltage supply, PLL Power
15
VSSPT1
GND
Analog Ground, PLL Ground
30
VDDT
VDD
Digital Voltage supply, Tx Serializer Power
31
VSST
GND
Digital Ground, Tx Serializer Ground
7
VDDL
VDD
Digital Voltage supply, Tx Logic Power
6
VSSL
GND
Digital Ground, Tx Logic Ground
42
VDDIT
VDD
Digital Voltage supply, Tx Input Power
43
VSSIT
GND
Digital Ground, Tx Input Ground
24
VSS
GND
ESD Ground
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12
DS99R105/DS99R106
DS99R105 Pin Diagram
Serializer - DS99R105
20208119
TOP VIEW
13
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DS99R105/DS99R106
DS99R106 Deserializer Pin Descriptions
Pin #
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 1
13-16, ROUT[15:8]
21-24
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 2
3-6,
9-12
ROUT[23:16] LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 3
18
RCLK
Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
LVCMOS_O
CONTROL AND CONFIGURATION PINS
43
RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48
REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
17
LOCK
LVCMOS_O
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
2
RESRVD
LVCMOS_I
RESERVED – This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
41
RIN+
LVDS_I
Receiver LVDS True (+) Input This input is intended to be terminated with a 100 ohm load to
the RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
42
RIN−
LVDS_I
Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100 ohm load
to the RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
39
VDDIR
VDD
Analog LVDS Voltage supply, Power
40
VSSIR
GND
Analog LVDS Ground
47
VDDPR0
VDD
Analog Voltage supply, PLL Power
46
VSSPR0
GND
Analog Ground, PLL Ground
45
VDDPR1
VDD
Analog Voltage supply, PLL VCO Power
44
VSSPR1
GND
Analog Ground, PLL VCO Ground
37
VDDR1
VDD
Digital Voltage supply, Logic Power
38
VSSR1
GND
Digital Ground, Logic Ground
36
VDDR0
VDD
Digital Voltage supply, Logic Power
35
VSSR0
GND
Digital Ground, Logic Ground
30
VDDOR1
VDD
Digital Voltage supply, LVCMOS Output Power
29
VSSOR1
GND
Digital Ground, LVCMOS Output Ground
20
VDDOR2
VDD
Digital Voltage supply, LVCMOS Output Power
19
VSSOR2
GND
Digital Ground, LVCMOS Output Ground
7
VDDOR3
VDD
Digital Voltage supply, LVCMOS Output Power
8
VSSOR3
GND
Digital Ground, LVCMOS Output Ground
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14
DS99R105/DS99R106
DS99R106 Pin Diagram
Deserializer - DS99R106
20208120
TOP VIEW
15
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DS99R105/DS99R106
DATA TRANSFER
After lock is established, the Serializer inputs DIN0–DIN23
are used to input data to the Serializer. Data is clocked into
the Serializer by the TCLK input. The edge of TCLK used to
strobe the data is selectable via the TRFB pin. TRFB high
selects the rising edge for clocking data and low selects the
falling edge. The Serializer outputs (DOUT±) are intended to
drive point-to-point connections or limited multi-point applications.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted
along the single LVDS serial data stream. The CLK1 bit is
always high and the CLK0 bit is always low. The CLK1 and
CLK0 bits function as the embedded clock bits in the serial
stream. DCB functions as the DC Balance control bit. It does
not require any pre-coding of data on transmit side. The DC
Balance bit is used to minimize the short and long-term DC
bias on the signal lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used
to validate data integrity in the embedded data stream. Both
DCA and DCB coding schemes are integrated and automatically performed within Serializer and Deserializer.
The chipset supports clock frequency ranges of 3 MHz to 40
MHz. Every clock cycle, 24 databits are sent along with 4 additional overhead control bits. Thus the line rate is 1.12 Gbps
maximum (84 Mbps minimum). The link is extremely efficient
at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to only 1 single LVDS pair
providing a compression ratio of better then 25 to 1.
Serialized data and clock/control bits (24+4 bits) are transmitted from the serial data output (DOUT±) at 28 times the
TCLK frequency. For example, if TCLK is , the serial rate is
40 x 28 = 1.12 Giga bits per second. Since only 24 bits are
from input data, the serial “payload” rate is 24 times the TCLK
frequency. For instance, if TCLK = 40 MHz, the payload data
rate is 40 x 24 = 960 Mbps. TCLK is provided by the data
source and must be in the range of 3 MHz to 40 MHz nominal.
The Serializer outputs (DOUT±) can drive a point-to-point
connection as shown in Figure 17. The outputs transmit data
when the enable pin (DEN) is high and TPWDNB is high. The
DEN pin may be used to TRI-STATE the outputs when driven
low.
When the Deserializer channel attains lock to the input from
a Serializer, it drives its LOCK pin high and synchronously
delivers valid data and recovered clock on the output. The
Deserializer locks onto the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK
output pin) is synchronous to the data on the ROUT[23:0]
pins. While LOCK is high, data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge
is controlled by the RRFB input. ROUT(0-23), LOCK and
RCLK outputs will each drive a maximum of 8 pF load with a
40 MHz clock. REN controls TRI-STATE for ROUTn and the
RCLK pin on the Deserializer.
Functional Description
The DS99R105 Serializer and DS99R106 Deserializer
chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial
LVDS link from 72 Mbps to 960 Mbps throughput. The
DS99R105 transforms a 24-bit wide parallel LVCMOS data
into a single high speed LVDS serial data stream with embedded clock. The DS99R106 receives the LVDS serial data
stream and converts it back into a 24-bit wide parallel data
and recovered clock. The 24-bit Serializer/Deserializer
chipset is designed to transmit data over shielded twisted pair
(STP) at clock speeds from 3 MHz to 40 MHz.
The Deserializer can attain lock to a data stream without the
use of a separate reference clock source. The Deserializer
synchronizes to the Serializer regardless of data pattern, delivering true automatic “plug and lock” performance. The Deserializer recovers the clock and data by extracting the
embedded clock information and validating data integrity from
the incoming data stream and then deserializes the data. The
Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCK output high when
lock occurs. Each has a power down control to enable efficient
operation in various applications.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS99R105 and DS99R106 must be established before each device sends or receives data. Initialization refers to synchronizing the Serializer’s and
Deserializer’s PLL’s together. After the Serializers locks to the
input clock source, the Deserializer synchronizes to the Serializers as the second and final initialization step.
Step 1: When VDD is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE and
internal circuitry is disabled by on-chip power-on circuitry.
When VDD reaches VDD OK (2.2V) the PLL in Serializer begins
locking to a clock input. For the Serializer, the local clock is
the transmit clock, TCLK. The Serializer outputs are held in
TRI-STATE while the PLL locks to the TCLK. After locking to
TCLK, the Serializer block is now ready to send data patterns.
The Deserializer output will remain in TRI-STATE while its
PLL locks to the embedded clock information in serial data
stream. Also, the Deserializer LOCK output will remain low
until its PLL locks to incoming data and sync-pattern on the
RIN± pins.
Step 2: The Deserializer PLL acquires lock to a data stream
without requiring the Serializer to send special patterns. The
Serializer that is generating the stream to the Deserializer will
automatically send random (non-repetitive) data patterns during this step of the Initialization State. The Deserializer will
lock onto embedded clock within the specified amount of time.
An embedded clock and data recovery (CDR) circuit locks to
the incoming bit stream to recover the high-speed receive bit
clock and re-time incoming data. The CDR circuit expects a
coded input bit stream. In order for the Deserializer to lock to
a random data stream from the Serializer, it performs a series
of operations to identify the rising clock edge and validates
data integrity, then locks to it. Because this locking procedure
is independent on the data pattern, total random locking duration may vary. At the point when the Deserializer’s CDR
locks to the embedded clock, the LOCK pin goes high and
valid RCLK/data appears on the outputs. Note that the LOCK
signal is synchronous to valid data appearing on the outputs.
The Deserializer’s LOCK pin is a convenient way to ensure
data integrity is achieved on receiver side.
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RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock edge is not
detected one time in succession, the PLL loses lock and the
LOCK pin is driven low. The Deserializer then enters the operating mode where it tries to lock to a random data stream.
It looks for the embedded clock edge, identifies it and then
proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data
on ROUT is valid; when it is high, the data is valid. The system
16
package parasitics. The most common used capacitor value
for the interface is 100 nF (0.1 uF) capacitor.
A termination resistor across DOUT± is also required for
proper operation to be obtained. The termination resistor
should be equal to the differential impedance of the media
being driven. This should be in the range of 90 to 132 Ohms.
100 Ohms is a typical value common used with standard 100
Ohm transmission media. This resistor is required for control
of reflections and also to complete the current loop. It should
be placed as close to the Serializer DOUT± outputs to minimize the stub length from the pins. To match with the deferential impedance on the transmission line, the LVDS I/O are
terminated with 100 ohm resistors on Serializer DOUT± outputs pins.
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power when no
data is being transferred. The TPWDNB and RPWDNB are
used to set each device into power down mode, which reduces supply current to the µA range. The Serializer enters
powerdown when the TPWDNB pin is driven low. In powerdown, the PLL stops and the outputs go into TRI-STATE,
disabling load current and reducing supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer
exits Powerdown, its PLL must lock to TCLK before it is ready
for the Initialization state. The system must then allow time for
Initialization before data transfer can begin. The Deserializer
enters powerdown mode when RPWDNB is driven low. In
powerdown mode, the PLL stops and the outputs enter TRISTATE. To bring the Deserializer block out of the powerdown
state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer will
initialize and assert LOCK high when it is locked to the encoded clock.
PROGRESSIVE TURN–ON (PTO)
Deserializer ROUT[23:0] outputs are grouped into three
groups of eight, with each group switching about 0.5UI apart
in phase to reduce EMI, simultaneous switching noise, and
system ground bounce.
Applications Information
USING THE DS99R105 AND DS99R106
The
DS99R105/DS99R106
Serializer/Deserializer
(SERDES) pair sends 24 bits of parallel LVCMOS data over
a serial LVDS link up to 960 Mbps. Serialization of the input
data is accomplished using an on-board PLL at the Serializer
which embeds clock with the data. The Deserializer extracts
the clock/control information from the incoming data stream
and deserializes the data. The Deserializer monitors the incoming clockl information to determine lock status and will
indicate lock by asserting the LOCK output high.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or
TPWDNB pin is driven low. This will TRI-STATE both driver
output pins (DOUT+ and DOUT−). When DEN is driven high,
the serializer will return to the previous state as long as all
other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output
pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE.
The LOCK output remains active, reflecting the state of the
PLL. The Deserializer input pins are high impedance during
receiver powerdown (RPWDNB low) and power-off (VDD =
0V).
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the slope
of the speed vs. IDD curve of CMOS designs.
PRE-EMPHASIS
The DS99R105 features a Pre-Emphasis mode used to compensate for long or lossy transmission media. Cable drive is
enhanced with a user selectable Pre-Emphasis feature that
provides additional output current during transitions to counteract cable loading effects. The transmission distance will be
limited by the loss characteristics and quality of the media.
Pre-Emphasis adds extra current during LVDS logic transition
to reduce the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster transitions, increased eye openings, and improved signal integrity.
The ability of the DS99R105 to use the Pre-Emphasis feature
will extend the transmission distance in most cases.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reliably recover data. Various environmental and systematic factors include:
Serializer: TCLK jitter, VDD noise (noise bandwidth and outof-band noise)
Media: ISI, VCM noise
Deserializer: VDD noise
For a graphical representation of noise margin, please see
Figure 16.
TRANSMISSION MEDIA
The Serializer and Deserializer can be used in point-to-point
configuration, through a PCB trace, or through twisted pair
cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of the transmitter and
receiver pair. Interconnect for LVDS typically has a differential
impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance
discontinuities. In most applications that involve cables, the
transmission distance will be determined on data rates involved, acceptable bit error rate and transmission medium.
AC-COUPLING AND TERMINATION
The DS99R105 and DS99R106 supports AC-coupled interconnects through integrated DC balanced encoding/decoding
scheme. To use AC coupled connection between the Serializer and Deserializer, insert external AC coupling capacitors
in series in the LVDS signal path as illustrated in Figure 17.
The Deserializer input stage is designed for AC-coupling by
providing a built-in AC bias network which sets the internal
VCM to +1.2V. With AC signal coupling, capacitors provide the
ac-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package should be used for the AC coupling capacitor.
This will help minimize degradation of signal quality due to
17
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DS99R105/DS99R106
must monitor the LOCK pin to determine whether data on the
ROUT is valid.
DS99R105/DS99R106
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS (LVTTL) signals away from the LVDS lines
to prevent coupling from the LVCMOS lines to the LVDS lines.
Closely-coupled differential lines of 100 Ohms are typically
recommended for LVDS interconnect. The closely coupled
lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly
coupled lines will also radiate less.
Termination of the LVDS interconnect is required. For pointto-point applications, termination should be located at both
ends of the devices. Nominal value is 100 Ohms to match the
line’s differential impedance. Place the resistor as close to the
transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting stub between the termination
resistor and device.
LIVE LINK INSERTION
The Serializer and Deserializer devices support live pluggable applications. The “Hot Inserted” operation on the serial
interface does not disrupt communication data on the active
data lines. The automatic receiver lock to random data “plug
& go” live insertion capability allows the DS99R106 to attain
lock to the active data stream during a live insertion event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value
and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and
tantalum electrolytic types. RF capacitors may use values in
the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be
in the 2.2 uF to 10 uF range. Voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage
being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing, multiple capacitors are often used
to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
—S = space between the pair
—2S = space between pairs
—3S = space to LVCMOS/LVTTL signal
• Minimize the number of VIA
• Use differential connectors when operating above
500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as
possible
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
20208118
FIGURE 17. AC Coupled Application
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18
DS99R105/DS99R106
20208121
FIGURE 18. DS99R105 Typical Application Connection
19
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DS99R105/DS99R106
20208122
FIGURE 19. DS99R106 Typical Application Connection
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20
DS99R105/DS99R106
Truth Tables
TABLE 1. DS99R105 Serializer Truth Table
TPWDNB
(Pin 9)
DEN
(Pin 18)
Tx PLL Status
(Internal)
LVDS Outputs
(Pins 19 and 20)
L
X
X
Hi Z
H
L
X
Hi Z
H
H
Not Locked
Hi Z
H
H
Locked
Serialized Data with Embedded Clock
TABLE 2. DS99R106 Deserializer Truth Table
RPWDNB
(Pin 1)
REN
(Pin 48)
Rx PLL Status
(Internal)
ROUTn and RCLK
(See Pin Diagram)
LOCK
(Pin 17)
L
X
X
Hi Z
Hi Z
H
L
X
Hi Z
L = PLL Unocked;
H = PLL Locked
H
H
Not Locked
Hi Z
L
H
H
Locked
Data and RCLK Active
H
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DS99R105/DS99R106
Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions show in millimeters only
Ordering Information
NSID
Package Type
Package ID
DS99R105VS
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
VBC48A
DS99R105VSX
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel
VBC48A
DS99R106VS
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
VBC48A
DS99R106VSX
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel
VBC48A
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22
DS99R105/DS99R106
Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions show in millimeters only
Ordering Information
NSID
Package Type
Package ID
DS99R105SQ
48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch
SQA48D
DS99R105SQX
48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch, 1000 std reel
SQA48D
DS99R106SQ
48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch
SQA48D
DS99R106SQX
48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch, 1000 std reel
SQA48D
23
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DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
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