Dallas DS1211 Nonvolatile controller x 8 chip Datasheet

DS1211
Nonvolatile Controller x 8 Chip
www.dalsemi.com
FEATURES
Converts full CMOS RAMs into nonvolatile
memories
Unconditionally write protects when VCC is
out of tolerance
Automatically switches to battery when
power-fail occurs
3 to 8 decoder provides control for up to eight
CMOS RAMs
Consumes less than 100 nA of battery current
Tests battery condition on power-up
Provides for redundant batteries
Power-fail signal can be used to interrupt
processor on power failure
Optional 5% or 10% power-fail detection
Optional 20-pin SOIC surface mount package
Optional industrial temperature range of
-40°C to +85°C
PIN ASSIGNMENT
VBAT1
1
20
VCCI
VCCO
2
19
VBAT2
TOL
3
18
CE
PF
4
17
CE0
CE7
5
16
CE1
CE6
6
15
CE2
C
7
14
CE3
B
8
13
NC
A
9
12
CE4
10
11
CE5
GND
VBAT1
VCCO
TOL
PF
CE7
CE6
C
B
A
GND
20-Pin DIP (300-mil)
See Mech. Drawings
Section
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCCI
VBAT2
CE
CE0
CE1
CE2
CE3
NC
CE4
CE5
20-Pin SOIC (300-mil)
See Mech. Drawings
Section
PIN DESCRIPTION
A, B, C
- Address Inputs
CE
- Chip Enable Input
CE0
-
GND
VBAT1
VBAT2
TOL
VCCI
VCC0
PF
NC
CE7
- Chip Enable Outputs
- Ground
- + Battery 1
- + Battery 2
- Power Supply Tolerance
- +5V Supply
- RAM Supply
- Power-fail
- No Connection
DESCRIPTION
The DS1211 Nonvolatile Controller x 8 Chip is a CMOS circuit which solves the application problem of
converting CMOS RAMs into nonvolatile memories. Incoming power is monitored for an out-oftolerance condition. When such a condition is detected, the chip enables are inhibited to accomplish write
protection and the battery is switched on to supply RAMs with uninterrupted power. Special circuitry
uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery
consumption.
By combining the DS1211 nonvolatile controller/decoder chip and lithium batteries, nonvolatile RAM
operation can be achieved for up to eight CMOS memories.
See the data sheet for the DS1212 Nonvolatile Controller x 16 Chip for electrical specifications and
operation.
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