AIC3843
Current-Mode PWM Controller
n FEATURES
n DESCRIPTION
l Low Start-Up Current (300µA Typical)
The AIC3843 control IC provides the features
that are necessary to implement off-line or
DC/DC Converter fixed-frequency current-mode
schemes with a minimum number of external
components. This integrated circuits features
an under-voltage lockout (UVLO) with approximately 300µA start-up current, a precision
reference trimmed for accuracy at the error
amplifier input, high gain error amplifier, current
sensing comparator, logic to insure latched
operation, and a totem-pole output stage
designed to source or sink high peak current.
The output stage, suitable for driving the Nchannel MOSFETs, is low in the off state.
l Internal Precision Reference.
l 500KHz Current-Mode Operation.
l Pulse-by-Pulse Current Limiting.
l Automatic Feed-Forward Compensation.
l Optimized for Off-line and DC/DC Converters.
l Under-voltage Lockout with Hysteresis.
l Double Pulse Suppression.
l High Current Totem Pole Output.
n APPLICATIONS
l AC/DC Off-line Converter.
l DC/DC Off-line Converter.
n TYPICAL APPLICATION CIRCUIT
2
7
VFB
VCC
VCC
+
C2
R3
300pF
51K
C3
1000P
FEEDBACK
SIGNAL
R4
7.5K
C5
0.1µF
1
6
COMP
OUTPUT
8
VREF
GND
4
RT/CT
ISENSE
C1
47µF
INDUCTOR
R1
M1
10
R2
20K
5
R5
3
AIC3843
390
C6
300P
C4
2.2nF
C7
1nF
RS
0.33
Current Mode PWM Control Circuit
Analog Integrations Corporation
4F, 9 Industry E. 9th Rd, Science-Based Industrial Park, Hsinchu, Taiwan
TEL: 886-3-5772500
FAX: 886-3-5772510
www.analog.com.tw
DS-3843-00 012102
1
AIC3843
n ORDERING INFORMATION
AIC3843CXXX
PIN CONFIGURATION
DIP-8
SO-8
TOP VIEW
PACKING TYPE
TR: TAPE & REEL
TB: TUBE
COMP 1
PACKAGE TYPE
N: PLASTIC DIP
S: SMALL OUT LINE
8 VREF
VFB 2
7 VCC
ISENSE 3
Example: AIC3843CSTR
à in SO-8 Package & Taping & Reel Packing Type
6 OUTPUT
RT/CT 4
5 GND
(CN is not available in TR packing type.)
n ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Low Impedance Source ) … ..........… … … … .............… … … … … … ........................ 30V
Supply Voltage (ICC <30mA) ...................… ..… … … … .… … … ..… … ................… … … .......... Self Limiting
Output Current ..............… … … … … … … … … ....… … … … ....................… … … .… … … .........… ......... ±1A
Output Energy (Capacitive Load)
...................… ........… … … … … .… .........… … … .… ...................... 5µJ
Analog Inputs (Pins 2, 3) … .....… … … … … … … … ...… ......… … … … .................… … … .... -0.3V to +6.3V
Error Amp Output Sink Current ......… ....… .… … ...… … … … ................… … … .… … … … ............... 10mA
Operation Temperature Range
......… ....… .… … ...… … … … .................… … … … ............... -40°C~85°C
Power Dissipation at TA ≤25°C DIP Package
......… … … … … … … … … ....… … … … ..… … ............... 1W
SOIC Package
Storage Temperature Range
.........… … .… ..… .....… … … … … … … ............. 725mW
.....… … ...… … … … ...........................… … ......… … … …
-65°C to +150°C
Lead Temperature (Soldering, 10 seconds) .....… … ...… … … … ..… … … … … .… … ....… … ........... 300°C
Note 1:
All voltages are with respect to Pin 5.
All currents are positive into the specified terminal.
n TEST CIRCUIT
VREF
RT
Q2
2N2222
R5
4.7K
COMP
Error Amp.
Adjust
R7
4.7K
VREF
R4
100K
VFB
R6
10K
ISENSE
Adjust R3
5K
VCC
A
VCC
ISENSE
OUTPUT
RT/CT
C2
0.1µF
R1
1K
1W
C1
0.1µF
S1
OUTPUT
GND
AIC3843
GROUND
CT
2
AIC3843
n ELECTRICAL CHARACTERISTICS {V
CC
= 15V (see Note 2), -40°C ≦ TA ≦85°C, unless
otherwise specified.}
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
4.9
5
5.1
V
Reference Section
Output Voltage
IO=1mA
Line Regulation
VCC=12V to 25V
5
20
mV
Load Regulation
IO=1mA to 20mA
5
25
mV
0.2
0.4
mV/°C
Temperature Coefficient of
Output Voltage
Output Noise Voltage
Output Voltage Long Term
Drift
After 1000H at TA=25°C
Short Circuit Output Current
µV
50
f =10Hz to 10KHz
5
25
mV
-30
-85
-180
mA
47
52
57
KHz
0.2
1
%
Oscillator Section
Oscillator Frequency (see
Note 3)
Frequency Change with
Supply Voltage
Frequency Change with
Temperature
VCC=12V to 25V
TA=TLOW to THIGH
Peak-to-Peak Amplitude at
RT/CT
5
%
1.7
V
Error Amplifier Section
Feedback Input Voltage
COMP at 2.5V
2.42
Input Bias Current
Open-Loop Voltage
Amplification
VO=2V to 4V
Gain-Bandwidth Product
Supply Voltage Rejection
Ratio
VCC =12V to 25V
Output Sink Current
VFB at 2.7V, COMP at 1.1V
Output Source Current
VFB at 2.3V, COMP at 5V
High-Level Output Voltage
VFB at 2.3V, RL=15KΩ to GND
Low-Level Output Voltage
VFB at 2.7V, RL=15Ω to VREF
2.50
2.58
V
-0.3
-2
µA
65
90
dB
0.7
1
MHz
60
70
dB
2
10
mA
-0.5
-1
mA
5
6.2
V
0.8
1.1
V
3
AIC3843
n ELECTRICAL CHARACTERISTICS (Continued)
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
See Note 3 and 4
2.85
3
3.15
V/V
COMP at 5V, See Note 3
0.9
1
1.1
V
Current Sense Section
Voltage Amplification
Current Sense Comparator
Threshold
Supply Voltage Rejection
Ratio
VCC =12V to 25V, See Note 3
70
Input Bias Current
Delay Time to Output
dB
-2
-10
µA
150
300
nS
Output Section
High-Level Output Voltage
ISOURCE=20mA
13
13.5
V
ISOURCE =200mA
12
13.4
V
ISINK=20mA
0.1
0.4
V
ISINK=200mA
1.5
2.2
V
Rise Time
CL=1nF
50
150
nS
Fall Time
CL=1nF
50
150
nS
Low-Level Output Voltage
Under voltage Lockout Section
Start Threshold Voltage
7.8
8.4
9.0
V
Minimum Operating Voltage
7.0
7.6
8.2
V
95
96
100
%
0
%
0.3
0.5
mA
12
17
mA
after Start-Up
Pulse-Width-Modulator Section
Maximum Duty Cycle
Minimum Duty Cycle
Supply Voltage
Start-Up Current
Operating Supply Current
VFB and ISENSE at 0V
Limiting Voltage
ICC =25mA
30
34
V
Note: 2: Adjust VCC above the start threshold before setting it to 15V.
3. These parameters are measured at the trip point of the latch with VFB at 0V.
4. Voltage amplification is measured between ISENSE and COMP with the input changing from 0V to
0.8V.
4
AIC3843
Error AMP Configuration
2.50V
0.5mA
+
VFB
2
ZI
COMP
ZF
1
Error Amp can Source or Sink up to 0.5mA
Fig. 1
Under-Voltage Lockout
ICC
7
17mA
AIC3843
V ON
8.4V
V OFF
7.6V
500µA
V CC
Fig. 2-1
Fig. 2-2
V OFF
V ON
During under-voltage lockout, the output driver is biased to sink minor amounts of
current. Pin 6 should be shunted to ground with a bleeder resistor to prevent
activating the power switch with extraneous leakage currents.
Current Sense Circuit
Error AMP
2R
R
IS
Current Sense
Comparator
COMP
R
RS
1V
C
Current Sense
GND
Peak Current (Is) is Determined By The Formula
I SMAX≈ 1.0V
RS
A small RC filter may be required to suppress switch transients.
Fig. 3
5
AIC3843
Oscillator Section
30
30
td ( µs)
RT/CT
CT=100nF
10
RT
4
RT (KΩ)
V REF
GND
100
8
3
0
CT
5
47nF
22nF
10nF
10
4.7nF
1
2.2nF
1.0nF
0.3
1.72
For RT>5k, f≈ RT * C T
3
1
10
100
10
2
10
3
CT (nF)
4
10
5
10
6
Frequency (Hz)
Deadtime vs CT (RT>5K Ω)
Fig. 4-1
10
Timing Resistance vs. Frequency
Fig. 4-2
Fig. 4-3
7
80
0
Vcc=15V
TA=+25° solid line
TA=-55° dash line
60
3
2
SOURCE SAT
(Vcc-VoH)
1
-50
40
-100
20
-150
0
-200
SINK SAT (Vol)
-20
0
0.01
0.1
Phase (degree)
5
Voltage Gain (dB)
Saturation Voltage - (V)
6
1
10
100
1k
10k
100k
1M
Output Current, Source or Sink - (A)
Frequency (Hz)
Fig. 4-4 Output saturation characteristics
Fig. 4-5 Error Am plifier Open-Loop Frequency Response
Open-Loop Laboratory Fixture
VREF
R1
2N2222
AIC3843
4.7K
1
COMP
VREF
V FB
VCC
100K
1K
ERROR
AMP
ADJUST
2
5K
4.7K
7
3
4
VCC
0.1µF
1k
0.1µF
I SENSE
ADJUST
A
8
I SENSE
OUTPUT
R T/C T
GND
6
1W
OUTPUT
5
GND
CT
High peak currents associated with capacitive loads necessitate careful grounding techniques.
Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The
transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable
ramp to pin 3.
Fig. 5
6
AIC3843
Open-Loop Laboratory Fixture
1k
1
8
V REF
COMP
SHUTDOWN
3
330O
I SENSE
500
SHUTDOWN
TO CURRENT SENSE
RESISTOR
Fig. 6-1
Fig. 6-2
Shutdown of the AIC3843 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two-diode
drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch
is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is
removed. In one example, an externally latched shutdown may be accomplished by adding an SCR, which will be reset by cycling
Vcc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
Offline Flyback Regulator
R1
5Ω
1W
117 VAC
L1
10µH
D6
VARO
VM68
C1
250µ F
250V
R12
C9
2W
R2
56K
2W
T1
USD945
4.7K
D4
Np
1N3613
R3
4.7k
COM
C2
7
+12V
D4
R9
68Ω
3W
100µ F C3
25V
22µF
2
R5 150k
C5
0.01 µF
R6
10k
C6
16V
N12
C4
25V
2200µ F
±12V COM
C13
N12
D8
47µ F
1
8
C12
Nc
2200 µF
16V
-12V
UES1002
AIC3843
C14 100pF
UFS1002
D7
1N3613
D2
20k
C11
4700 µF
10V
600V
1N3612
R4
+ 5V
C10
4700 µF
10V
N5
3300pF
R7
6
22Ω
3
4 5
Q1
R8
UFN833
1k
C7
470pF
0.0022µ F
16V
R13
10K
R10
0.55Ω
1W
D5
1N3613
USD1120
C8
680pF
R11
2.7k
2W
Power Supply Specifications
1. Input Voltage
95VAC to 130VA
2. Line Isolation
(50Hz/60Hz)
3750V
5. Output Voltage:
A. +5V, ±5%; 1A to 4A load
Ripple voltage: 50mV P-P Max
3. Switching Frequency
40kHz
4. Efficiency @ Full Load 70%
B. +12V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
C. -12V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
Fig. 7
7
AIC3843
Slope compensation
8
VREF
0.1µF
RT
4
RT/ CT
CT
R1
3
ISENSE
R2
ISENSE
A fraction of the oscillator ramp can be
resistively summed with the current sense
signal to proved slope compensation for
converters requiring duty cycles over 50%
Note that capacitor, C forms a filter with R2 to
suppress the leading edge switch spikes.
C
AIC3843
RSENSE
Fig. 8
n BLOCK DIAGRAM
VCC
7
5
ZD
34V
UVLO
S/R
GND
8
5V
REF
VREF
5V/50mA
Internal Bias
2.50V
4
RT/CT
VFB
2
1
COMP
VREF
Good
Logic
OSC
Q1
6
OUTPUT
T
Error Amp.
+
-
S
PWM
Latch
Q2
R
D1
D2
2R
R
Z1
1V
Current
Sense
comparator
3
ISENSE
8
AIC3843
n PIN DESCRIPTIONS
PIN 1: COMP
- This pin is the error amplifier
PIN 5: GND
output and is made available
for loop compensation.
PIN 2: VFB
circuitry and power ground.
PIN 6: OUTPUT- This output directly drives the
- This is the inverting input of
the
error
normally
amplifier.
connected
It
to
is
through a resistor divider.
voltage
gate of a power MOSFET.
Peak currents up to 1A are
the
switching power supply output
PIN 3: ISENSE - A
proportional
sourced and sunk by this pin.
PIN 7: VCC
- This pin is the positive supply of
the control IC.
to
inductor current is connected
PIN 8: VREF - This is the reference output. It
provides charging current for
to this input. The PWM uses
capacitor CT through resistor
this information to terminate
RT.
the output switch conduction.
PIN 4: RT/CT
- This pin is the combined control
- The oscillator frequency and
maximum output duty cycle
are programmed by connecting resistor RT to VREF and
capacitor C T to ground. It is
feasible to operate when f ≦
500KHz.
n APPLICATION INFORMATIONS
Under voltage Lockout
There are two separate under voltage lockout
comparators incorporated to make sure that the
IC is fully functional before the output stage is
enabled. One is for power supply voltage (VCC)
and the other is for reference output voltage
efficient bootstrap startup techniques are required.
A 34V zener is connected as a shunt regulator
from VCC to ground. Its purpose is to protect the
IC from excessive voltage that can occur during
system start-up.
Reference Output
(VREF). Each has a built in hysteresis to prevent
erratic output behavior when their respective
The 5.0V reference output is trimmed to ±2.0%
thresholds are crossed. For VCC comparator the
tolerance at TA=25°C. It supplies charging current
upper and lower thresholds are 8.4V and 7.6V,
to the oscillator timing capacitor and is capable of
respectively. The large hysteresis and low start up
providing current in excess of 20mA for powering
current (0.3mA) of the AIC3843 make it ideally
additional control system circuitry. In case of
suited in off-line converter applications where
overload, the reference is short-circuit protected at
9
AIC3843
about 85mA.
oscillator and terminated when the peak inductor
current reaches the threshold level established by
Error Amplifier
the error amplifier output (pin 1). The AIC3843 is
A fully compensated error amplifier is provided
with
inverting
input
and
output
externally
accessible. The non-inverting input is internally
operated at a current mode since the inductor
current is monitored cycle-by-cycle and decides
the duty cycle.
biased at 2.5V. The converter output voltage is
usually divided down and connected to the
The inductor current is converted to a voltage by
inverting input.
inserting the ground referenced sense resistor RS
in series with the source of output switch M1.
The output of the error amplifier is accessible for
This voltage is monitored by the current
external loop compensation, with an offset at two
input (pin 3) and is compared to a level derived
diode drops (≅1.4V) and divided by three, before
sense
from the error amplifier output. In the normal
connected to the inverting input of the current
operating conditions the peak inductor current is
sense comparator. This guarantees that no drive
controlled by the voltage at pin 1 where
pulse appears at the output (pin 6).
IPK =
Oscillator
V ( pin 1)− 1. 4V
3RS
PWM Latch is used to ensure that only a single
The oscillator frequency can be programmed
pulse appears at the output during any given
through the setting of timing components RT and
oscillator cycle. However, a narrow spike on the
CT. Capacitor CT is charged from the 5.0V
leading edge of the current waveform can usually
reference output through RT to about 2.8V and
be observed and may cause the power supply to
discharged to about 1.2V by the internal
exhibit an instability when the output is tightly
discharge current. When CT is discharged the
loaded.
output (pin 6) must be in the low state, thus
producing
a
controlled
amount
of
output
Output Switch
deadtime. Note that many values of RT and CT
The AIC3843 contains a single totem-pole output
can produce the same frequency but only one
stage that was specifically designed for direct
combination will yield a specific output deadtime
drive of power MOSFET. If any under voltage
at a given frequency.
lockout is detected, internal circuitry will keep the
output switch in a sinking current mode, no
Current Sense Comparator and PWM
Latch
external pull down resistor is needed.
The output switch of AIC3843 is initiated by the
10
AIC3843
n PHYSICAL DIMENSIONS
l
8 LEAD PLASTIC SO (unit: mm)
D
SYMBOL
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
H
E
e
e
A
A1
C
B
l
1.27(TYP)
H
5.80
6.20
L
0.40
1.27
L
8 LEAD PLASTIC DIP (unit: mm)
D
E1
E
A2
A1
MAX
A1
0.381
—
A2
2.92
4.96
b
0.35
0.56
C
0.20
0.36
D
9.01
10.16
E
7.62
8.26
E1
6.09
7.12
e
eB
e
MIN
C
L
b
SYMBOL
2.54 (TYP)
eB
—
10.92
L
2.92
3.81
11