AD ADM3052BRWZ Isolated can transceiver with integrated high voltage, bus-side, linear regulator Datasheet

Isolated CAN Transceiver with Integrated
High Voltage, Bus-Side, Linear Regulator
ADM3052
FEATURES
GENERAL DESCRIPTION
5 kV rms isolated CAN transceiver
Integrated V+ linear regulator
Bus side powered by V+ and V−
11 V to 25 V operation on V+
5 V or 3.3 V operation on VDD1
Complies with ISO 11898 standard
High speed data rates up to 1 Mbps
Short-circuit protection on bus pins
Integrated bus miswire protection
Unpowered nodes do not disturb the bus
110 or more nodes on the bus
Thermal shutdown protection
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition (pending)
5000 VRMS for 1 minute per UL 1577
VDE Certificates of Conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
Industrial operating temperature range: −40°C to +85°C
Wide body, 16-lead SOIC package
The ADM3052 is an isolated controller area network (CAN)
physical layer transceiver with a V+ integrated linear regulator.
The ADM3052 complies with the ISO 11898 standard.
The device employs Analog Devices, Inc., iCoupler® technology
to combine a 3-channel isolator, a CAN transceiver, and a linear
regulator into a single package. The power is isolated between a
single 3.3 V or 5 V supply on VDD1, the logic side, and a single
24 V supply provided on V+, the bus side.
The ADM3052 creates an isolated interface between the CAN
protocol controller and the physical layer bus. It is capable of
running at data rates up to 1 Mbps.
The device has integrated miswire protection on the bus pins,
V+, V−, CANH, and CANL.
The device has current-limiting and thermal shutdown features
to protect against output short circuits and situations where the
bus may be shorted to ground or power terminals. The part
is fully specified over the industrial temperature range and is
available in a 16-lead, wide-body SOIC package.
APPLICATIONS
CAN data buses
Industrial field networks
DeviceNet applications
FUNCTIONAL BLOCK DIAGRAM
VDD1
CINT
ISOLATION
BARRIER
LINEAR
REGULATOR
V+R
VDD2
V+SENSE
DECODE
ENCODE
BUS
V+SENSE
VDD2
V+
PROTECTION
ENCODE
DECODE
RxD
DECODE
ENCODE
TxD
DRIVER
CANH
RxD
CANL
RECEIVER
VREF
REFERENCE
VOLTAGE
VREF
GND2
GND2
DIGITAL ISOLATION
ADM3052
CAN TRANSCEIVER
GND1
LOGIC SIDE
BUS SIDE
V–
09292-001
TxD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADM3052
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits ..................................................................................... 12
Applications ....................................................................................... 1
Switching Characteristics .............................................................. 13
General Description ......................................................................... 1
Circuit Description......................................................................... 14
Functional Block Diagram .............................................................. 1
CAN Transceiver Operation ..................................................... 14
Revision History ............................................................................... 2
Electrical Isolation...................................................................... 14
Specifications..................................................................................... 3
Truth Tables................................................................................. 14
Timing Specifications .................................................................. 4
Thermal Shutdown .................................................................... 16
Regulatory Information ............................................................... 4
Linear Regulator ......................................................................... 16
Insulation and Safety-Related Specifications ............................ 4
Magnetic Field Immunity.......................................................... 16
VDE 0884 Insulation Characteristics (Pending) ...................... 5
Applications Information .............................................................. 17
Absolute Maximum Ratings............................................................ 6
Typical Applications ................................................................... 17
ESD Caution .................................................................................. 6
Outline Dimensions ....................................................................... 18
Pin Configuration and Function Descriptions ............................. 7
Ordering Guide .......................................................................... 18
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
6/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADM3052
SPECIFICATIONS
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 5.5 V, TA = −40°C to +85°C, V+ = 11 V to 25 V, unless otherwise noted.
Table 1.
Parameter
SUPPLY CURRENT
Power Supply Current Logic Side
TxD/RxD Data Rate 1 Mbps
Power Supply Current Bus Side
Recessive State
Dominant State
TxD/RxD Data Rate 1 Mbps
EXTERNAL RESISTOR
Resistance
Power Rating
DRIVER
Logic Inputs
Input Voltage High
Input Voltage Low
CMOS Logic Input Currents
Differential Outputs
Recessive Bus Voltage
CANH Output Voltage
CANL Output Voltage
Differential Output Voltage
Short-Circuit Current, CANH
Symbol
Min
Typ
Max
Unit
IDD1
0.7
2
mA
I+
I+
I+
64
48
10
75
55
mA
mA
mA
300
303
Ω
W
Voltage Dominant
Input Voltage Hysteresis
CANH, CANL Input Resistance
Differential Input Resistance
Logic Outputs
Output Low Voltage
Output High Voltage
Short-Circuit Current
VOLTAGE REFERENCE
Reference Output Voltage
BUS VOLTAGE SENSE
V+SENSE Output Voltage Low
V+SENSE Output Voltage High
Threshold Voltage
COMMON-MODE TRANSIENT
IMMUNITY1
1
RL = 60 Ω, see Figure 26
RL = 60 Ω, see Figure 26
RL = 60 Ω, see Figure 26
RP
297
0.75
VIH
VIL
IIH, IIL
0.7 VDD1
V
0.25 VDD1 V
500
μA
TxD
TxD
TxD
VCANL, VCANH
VCANH
VCANL
VOD
VOD
ISCCANH
2.0
2.75
0.5
1.5
−500
3.0
4.5
2.0
3.0
+50
−200
200
V
V
V
V
mV
mA
mA
mA
VTxD = high, RL = ∞, see Figure 23
VTxD = low, see Figure 23
VTxD = low, see Figure 23
VTxD = low, RL = 45 Ω, see Figure 23
VTxD = high, RL = ∞, see Figure 23
VCANH = −5 V
VCANH = −36 V
VCANL = 36 V
−7 V < VCANL, VCANH < 12 V, see Figure 24,
CL = 15 pF
−7 V < VCANL, VCANH < 12 V, see Figure 24,
CL = 15 pF
See Figure 24
−100
Short-Circuit Current, CANL
RECEIVER
Differential Inputs
Voltage Recessive
Test Conditions
ISCCANL
VIDR
−1.0
+0.5
V
VIDD
0.9
5.0
V
VHYS
RIN
RDIFF
5
20
25
100
mV
kΩ
kΩ
VOL
VOH
IOS
0.2
0.4
VDD1 − 0.3 VDD1 − 0.2
7
85
V
V
mA
IOUT = 1.5 mA
IOUT = −1.5 mA
VOUT = GND1 or VDD1
VREF
2.025
V
|IREF = 50 μA|
VOL
VOH
V+SENSETH
0.2
0.4
VDD1 − 0.3 VDD1 − 0.2
7.0
10
25
V
V
V
kV/μs
IO+SENSE = 1.5 mA
IO+SENSE = −1.5 mA
150
3.025
VCM = 1 kV, transient magnitude = 800 V
CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates
apply to both rising and falling common-mode voltage edges.
Rev. 0 | Page 3 of 20
ADM3052
TIMING SPECIFICATIONS
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 5.5 V, TA = −40°C to +85°C, V+ = 11 V to 25 V, unless otherwise noted.
Table 2.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay from TxD On to Bus Active
Symbol
Min
Typ
Max
Unit
tonTxD
90
Mbps
ns
Propagation Delay from TxD Off to Bus Inactive
toffTxD
120
ns
RECEIVER
Propagation Delay from TxD On to Receiver Active
tonRxD
200
ns
toffRxD
250
ns
tSE
tSD
300
10
μs
ms
1
Propagation Delay from TxD Off to Receiver Inactive
POWER-UP
Enable Time, V+ High to V+SENSE Low
Disable Time, V+ Low to V+SENSE High
Test Conditions
See Figure 25 and Figure 27,
RL = 60 Ω, CL = 100 pF
See Figure 25 and Figure 27,
RL = 60 Ω, CL = 100 pF
See Figure 25 and Figure 27,
RL = 60 Ω, CL = 100 pF
See Figure 25 and Figure 27,
RL = 60 Ω, CL = 100 pF
See Figure 29
See Figure 29
REGULATORY INFORMATION
The ADM3052 approval is pending by the organizations listed in Table 3.
Table 3.
Organization
UL
Approval Type
Recognized under the component recognition
program of Underwriters Laboratories, Inc.
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
Notes
In accordance with UL 1577, each ADM3052 is proof tested by
applying an insulation test voltage ≥6000 V rms for 1 second
(current leakage detection limit = 10 μA)
In accordance with DIN V VDE V 0884-10, each ADM3052 is proof
tested by applying an insulation test voltage ≥1590 V peak for
1 second (partial discharge detection limit = 5 pC)
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
7.7
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
7.6
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>175
IIIa
mm
V
Rev. 0 | Page 4 of 20
Conditions
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance along body
Insulation distance through insulation
DIN IEC 112/VDE 0303-1
Material group (DIN VDE 0110)
ADM3052
VDE 0884 INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation within the safety limit data. Maintenance of the safety data must be ensured by
means of protective circuits.
Table 5.
Description
CLASSIFICATIONS
Installation Classification per DIN VDE 0110 for Rated
Mains Voltage
≤150 V rms
≤300 V rms
≤400 V rms
Climatic Classification
Pollution Degree
VOLTAGE
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests, Subgroup 1
After Input and/or Safety Test,
Subgroup 2/Subgroup 3
Highest Allowable Overvoltage
SAFETY-LIMITING VALUES
Case Temperature
Input Current
Output Current
Insulation Resistance at TS
Test Conditions
Symbol
VIORM
VPR
846
1590
V peak
V peak
VPR
1357
V peak
1018
V peak
VTR
6000
V peak
TS
IS, INPUT
IS, OUTPUT
RS
150
265
335
>109
°C
mA
mA
Ω
VIORM × 1.6 = VPR, tm = 60 sec,
partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec,
partial discharge < 5 pC
Rev. 0 | Page 5 of 20
Unit
I to IV
I to III
I to II
40/85/21
2
DIN VDE 0110
VIORM × 1.875 = VPR, 100% production tested,
tm = 1 sec, partial discharge < 5 pC
Characteristic
ADM3052
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 6.
Parameter
VDD1
V+
V+R
Digital Input Voltage
TxD
Digital Output Voltage
RxD
V+SENSE
CANH, CANL
VREF
Operating Temperature Range
Storage Temperature Range
ESD (Human Body Model)
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
θJA, Thermal Impedance
TJ, Junction Temperature
Rating
−0.5 V to +6 V
−36 V to +36 V
−36 V to +36 V
−0.5 V to VDD1 + 0.5 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−0.5 V to VDD1 + 0.5 V
−0.5 V to VDD1 + 0.5 V
−36 V to +36 V
−0.5 V to +6 V
−40°C to +85°C
−55°C to +150°C
3 kV
300°C
215°C
220°C
53°C/W
130°C
Rev. 0 | Page 6 of 20
ADM3052
NC 1
16
V–
GND1 2
15
V+
GND1 3
14
V+R
V+SENSE 4
ADM3052
13
CINT
RxD 5
TOP VIEW
(Not to Scale)
12
CANH
TxD 6
11
CANL
VDD1 7
10
VREF
GND1 8
9
V–
NOTES
1. NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
09292-006
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
NC
GND1
GND1
V+SENSE
5
6
7
RxD
TxD
VDD1
8
9
10
11
12
13
14
GND1
V−
VREF
CANL
CANH
CINT
V+R
15
16
V+
V−
Description
No Connect. Do not connect to this pin.
Ground (Logic Side).
Ground (Logic Side).
Bus Voltage Sense. A low level on V+SENSE indicates that there is power connected on the bus on V+ and V−.
A high level on V+SENSE indicates that power is not connected on the bus on V+ and V−.
Receiver Output Data.
Driver Input Data.
Power Supply (Logic Side). Decoupling capacitor to GND1 required; capacitor value should be between
0.01 μF and 0.1 μF.
Ground (Logic Side).
Ground (Bus Side).
Reference Voltage Output.
Low Level CAN Voltage Input/Output.
High Level CAN Voltage Input/Output.
A capacitor of 1 μF, 10 V is required on this pin.
Connect a 300 Ω, 750 mW resistor between V+R and V+. It is recommended that a 10 μF capacitor be fitted
between V+R and GND2.
Bus Power Connection. Connect a 300 Ω, 750 mW resistor between V+R and V+.
Ground (Bus Side).
Rev. 0 | Page 7 of 20
ADM3052
TYPICAL PERFORMANCE CHARACTERISTICS
195
VDD1 = 3.3V, V+ = 25V
VDD1 = 5V, V+ = 25V
VDD1 = 3.3V, TA = 25°C
VDD1 = 5V, TA = 25°C
194
PROPAGATION DELAY TxD ON TO
RECEIVER ACTIVE, tonRxD (ns)
PROPAGATION DELAY TxD OFF TO
RECEIVER INACTIVE, toffRxD (ns)
162
160
158
156
154
152
193
192
191
190
189
150
–15
10
35
60
85
TEMPERATURE (°C)
188
11
09292-023
148
–40
19
21
23
25
90
V+ = 25V
156
155
154
153
11
13
15
17
19
21
23
25
SUPPLY VOLTAGE, V+ (V)
Figure 4. Propagation Delay from TxD On to Receiver Active
vs. Supply Voltage, V+
VDD1 = 3.3V
80
VDD1 = 5V
75
70
65
60
–40
09292-024
152
85
–15
10
35
60
85
TEMPERATURE (°C)
09292-015
PROPAGATION DELAY, toffTxD (ns)
VDD1 = 3.3V, TA = 25°C
VDD1 = 5V, TA = 25°C
Figure 7. Propagation Delay from TxD Off to Bus Inactive vs. Temperature
85
250
VDD1 = 3.3V, V+ = 25V
VDD1 = 5V, V+ = 25V
PROPAGATION DELAY TxD OFF TO
BUS INACTIVE, toffTxD (ns)
84
200
150
100
50
VDD1 = 3.3V, TA = 25°C
VDD1 = 5V, TA = 25°C
83
82
81
80
79
78
77
0
–40
–15
10
35
60
85
TEMPERATURE (°C)
09292-025
76
75
11
13
15
17
19
21
23
SUPPLY VOLTAGE, V+ (V)
Figure 8. Propagation Delay from TxD Off to Bus Inactive
vs. Supply Voltage, V+
Figure 5. Propagation Delay from TxD Off to Receiver Inactive
vs. Temperature
Rev. 0 | Page 8 of 20
25
09292-029
PROPAGATION DELAY TxD ON TO
RECEIVER ACTIVE, tonRxD (ns)
17
Figure 6. Propagation Delay from TxD Off to Receiver Inactive
vs. Supply Voltage, V+
157
PROPAGATION DELAY TxD OFF TO
RECEIVER INACTIVE, toffRxD (ns)
15
SUPPLY VOLTAGE, V+ (V)
Figure 3. Propagation Delay from TxD On to Receiver Active
vs. Temperature
151
13
09292-026
164
ADM3052
51
VDD1 = 3.3V, V+ = 25V
VDD1 = 5V, V+ = 25V
VDD1 = 3.3V, V+ = 25V
VDD1 = 5V, V+ = 25V
50
PROPAGATION DELAY TxD ON
TO BUS ACTIVE, tonTxD (ns)
50
49
48
47
46
48
47
46
–15
10
35
60
85
TEMPERATURE (°C)
44
–40
Figure 9. Propagation Delay from TxD On to Bus Active vs. Temperature
10
35
60
85
TEMPERATURE (°C)
Figure 12. Propagation Delay from TxD On to Bus Active vs. Temperature
50
VDD1 = 3.3V, TA = 25°C
VDD1 = 5V, TA = 25°C
48
50
V+ = 11V,
V+ = 18V,
V+ = 25V,
VDD1 = 5V, TA = 25°C
VDD1 = 5V, TA = 25°C
VDD1 = 5V, TA = 25°C
46
SUPPLY CURRENT, I+ (mA)
PROPAGATION DELAY TxD ON
TO BUS ACTIVE, tonTxD (ns)
–15
09292-021
44
–40
51
49
45
45
09292-023
PROPAGATION DELAY TxD ON TO
BUS ACTIVE, tonTxD (ns)
51
49
48
47
46
44
42
40
38
36
34
45
13
15
17
19
21
23
25
SUPPLY VOLTAGE, V+ (V)
30
100
09292-022
44
11
Figure 10. Propagation Delay from TxD On to Bus Active
vs. Supply Voltage, V+
Figure 13. Supply Current (I+) vs. Data Rate (Across V+, VDD1 = 5 V)
1.2
VDD1 = 3.3V, TA = 25°C
VDD1 = 5V, TA = 25°C
VDD1 = 3.3V, V+ = 24V, TA = 25°C
VDD1 = 5V, V+ = 24V, TA = 25°C
SUPPLY CURRENT, IDD1 (mA)
1.0
2.38
2.37
2.36
2.35
2.34
0.8
0.6
0.4
0.2
2.32
11
13
15
17
19
21
SUPPLY VOLTAGE, V+ (V)
23
25
0
100
Figure 11. Differential Output Voltage Dominant vs. Supply Voltage, V+
1000
DATA RATE (kbps)
09292-020
2.33
09292-028
DIFFERENTIAL OUTPUT VOLTAGE DOMINANT,
VOD (V)
2.40
2.39
1000
DATA RATE (kbps)
09292-019
32
Figure 14. Supply Current (IDD1) vs. Data Rate (VDD1 = 3.3 V, 5 V; V+ = 24 V)
Rev. 0 | Page 9 of 20
ADM3052
2.38
2.36
2.34
2.32
2.30
2.28
2.26
–40
–15
10
35
60
85
TEMPERATURE (°C)
40
20
10
35
2.80
VDD1 = 3.3V, TA = 25°C
VDD1 = 5V, TA = 25°C
REFERENCE VOLTAGE, VREF (V)
2.38
2.37
2.36
2.35
2.34
60
VCC
VCC
VCC
VCC
2.75
2.33
85
= 5V,
= 5V,
= 5V,
= 5V,
IREF
IREF
IREF
IREF
= +50µA
= –50µA
= +5µA
= –5µA
2.70
2.65
2.60
2.55
2.50
13
15
17
19
21
23
25
2.40
–40
–15
10
35
60
85
60
85
TEMPERATURE (°C)
Figure 16. Driver Differential Output Voltage Dominant vs. Supply Voltage, V+
09292-032
2.45
SUPPLY VOLTAGE, V+ (V)
Figure 19. VREF vs. Temperature
4.895
85
VCC = 5V
IOUT = –1.5mA
V+SENSE ENABLE TIME, tSE (µs)
4.890
4.885
4.880
4.875
4.870
4.865
80
VDD1 = 3.3V
75
VDD1 = 5V
70
65
4.855
–40
–15
10
35
60
TEMPERATURE (°C)
85
Figure 17. Receiver Output High Voltage vs. Temperature
60
–40
–15
10
35
TEMPERATURE (°C)
Figure 20. Enable Time, V+ High to V+SENSE Low vs. Temperature
Rev. 0 | Page 10 of 20
09292-016
4.860
09292-031
RECEIVER OUTPUT HIGH VOLTAGE, VOH (V)
–15
Figure 18. Receiver Output Low Voltage vs. Temperature
09292-033
DIFFERENTIAL OUTPUT VOLTAGE DOMINANT,
VOD (V)
60
TEMPERATURE (°C)
2.40
2.32
11
80
0
–40
Figure 15. Driver Differential Output Voltage Dominant vs. Temperature
2.39
100
09292-030
RECEIVER OUTPUT LOW VOLTAGE, VOL (mV)
2.40
120
VDD1 = 3.3V, V+ = 25V
VDD1 = 5V, V+ = 25V
09292-027
DIFFERENTIAL OUTPUT VOLTAGE DOMINANT,
VOD (V)
2.42
ADM3052
VDD1 = 3.3V
660
VDD1 = 5V
650
640
630
620
610
600
–40
–15
10
35
60
85
TEMPERATURE (°C)
Figure 21. Disable Time, V+ Low to V+SENSE High vs. Temperature
09292-017
V+SENSE DISABLE, tSD (µs)
670
8.56
8.54
VDD1 = 3.3V
VDD1 = 5V
8.52
8.50
8.48
8.46
8.44
8.42
8.40
–40
–15
10
35
TEMPERATURE (°C)
60
85
09292-018
V+SENSE THRESHOLD VOLTAGE HIGH TO LOW (V)
680
Figure 22. Bus Voltage Sense Threshold Voltage High to Low vs. Temperature
Rev. 0 | Page 11 of 20
ADM3052
TEST CIRCUITS
CANH
TxD
RL
RL
2
VCANH
RL
2
CL
CANL
VOC
VCANL
RxD
09292-009
VOD
09292-007
TxD
15pF
Figure 23. Driver Voltage Measurements
Figure 25. Switching Characteristics Measurements
VID
RxD
CL
CANL
09292-008
CANH
Figure 24. Receiver Voltage Measurements
1µF
VDD1
CINT
ISOLATION
BARRIER
10µF
RP
VDD2
V+SENSE
DECODE
ENCODE
V+
V+R
LINEAR
REGULATOR
100nF
V+
BUS
V+SENSE
VDD2
PROTECTION
ENCODE
DECODE
TxD
DRIVER
CANH
RxD
CANL
RxD
DECODE
VREF
REFERENCE
VOLTAGE
VREF
GND2
GND2
DIGITAL ISOLATION
ADM3052
V–
CAN TRANSCEIVER
GND1
LOGIC SIDE
RL
RECEIVER
ENCODE
BUS SIDE
Figure 26. Supply Current Measurement Test Circuit
Rev. 0 | Page 12 of 20
09292-010
TxD
ADM3052
SWITCHING CHARACTERISTICS
VDD1
0.7VDD1
VTxD
0.25V DD1
0V
VOD
VDIFF = VCANH – VCANL
VDIFF
0.9V
0.5V
VOR
toffTxD
tonTxD
VDD1
VDD1 – 0.3V
VRxD
0V
tonRxD
09292-002
0.4V
toffRxD
Figure 27. Driver and Receiver Propagation Delay
VRxD
HIGH
LOW
VID (V)
0.9
0.5
09292-004
VHYS
Figure 28. Receiver Input Hysteresis
25V
V+SENSETH
V+SENSETH
V+
0V
tSD
tSE
VDD1
0.4V
0V
Figure 29. V+SENSE Enable/Disable Time
Rev. 0 | Page 13 of 20
09292-005
VDD1 – 0.3
V+SENSE
ADM3052
CIRCUIT DESCRIPTION
CAN TRANSCEIVER OPERATION
TRUTH TABLES
A CAN bus has two states: dominant and recessive. A dominant
state is present on the bus when the differential voltage between
CANH and CANL is greater than 0.9 V. A recessive state is
present on the bus when the differential voltage between CANH
and CANL is less than 0.5 V. During a dominant bus state, the
CANH pin is high and the CANL pin is low. During a recessive
bus state, both the CANH and CANL pins are in the high
impedance state.
The truth tables in this section use the abbreviations shown
in Table 8.
ELECTRICAL ISOLATION
In the ADM3052, electrical isolation is implemented on the
logic side of the interface. Therefore, the part has two main
sections: a digital isolation section and a transceiver section
(see Figure 30). The driver input signal, which is applied to the
TxD pin and referenced to the logic ground (GND1), is coupled
across an isolation barrier to appear at the transceiver section
referenced to the isolated ground (V−). Similarly, the receiver
input and V+, which are referenced to the isolated ground in
the transceiver section, are coupled across the isolation barrier
to appear at the RxD pin and V+SENSE referenced to the logic
ground, respectively.
iCoupler Technology
The digital signals transmit across the isolation barrier using
iCoupler technology. This technique uses chip scale transformer
windings to couple the digital signals magnetically from one
side of the barrier to the other. Digital inputs are encoded into
waveforms that are capable of exciting the primary transformer
winding. At the secondary winding, the induced waveforms are
decoded into the binary value that was originally transmitted.
Table 8. Truth Table Abbreviations
Letter
H
L
I
X
Z
NC
Description
High level
Low level
Indeterminate
Don’t care
High impedance (off)
Disconnected
Table 9. Transmitting
Supply Status
VDD1
V+
On
On
On
On
On
On
Off
On
On
Off
Input
TxD
L
H
Floating
X
L
Bus State
Dominant
Recessive
Recessive
Recessive
I
Outputs
CANH
CANL
H
L
Z
Z
Z
Z
Z
Z
I
I
V+SENSE
L
L
L
I
H
Table 10. Receiving
Supply Status
VDD1
V+
On
On
On
On
On
On
On
On
Off
On
On
Off
Positive and negative logic transitions at the input cause narrow
(~1 ns) pulses to be sent to the decoder via the transformer. The
decoder is bistable and is, therefore, set or reset by the pulses,
indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh
pulses, indicative of the correct input state, is sent to ensure dc
correctness at the output. If the decoder receives no internal
pulses for more than about 5 μs, the input side is assumed to be
unpowered or nonfunctional, in which case the output is forced
to a default state (see Table 9 and Table 10).
Rev. 0 | Page 14 of 20
Inputs
VID = CANH − CANL
≥ 0.9 V
≤ 0.5 V
0.5 V < VID < 0.9 V
Inputs open
X
X
Bus State
Dominant
Recessive
I
Recessive
X
X
RxD
L
H
I
H
I
H
Outputs
V+SENSE
L
L
L
L
I
H
ADM3052
1µF
VDD1
CINT
ISOLATION
BARRIER
10µF
RP
VDD2
V+SENSE
DECODE
ENCODE
V+
V+R
LINEAR
REGULATOR
100nF
V+
BUS
V+SENSE
VDD2
PROTECTION
ENCODE
DECODE
DRIVER
CANH
RxD
CANL
RxD
DECODE
VREF
REFERENCE
VOLTAGE
VREF
GND2
GND2
DIGITAL ISOLATION
ADM3052
V–
CAN TRANSCEIVER
GND1
LOGIC SIDE
RL
RECEIVER
ENCODE
BUS SIDE
Figure 30. Digital Isolation and Transceiver Sections
Rev. 0 | Page 15 of 20
09292-010
TxD
TxD
ADM3052
100
MAGNETIC FIELD IMMUNITY
The limitation on the magnetic field immunity of the iCoupler
is set by the condition in which an induced voltage in the receiving coil of the transformer is large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this may occur. The 3 V operating condition of the
ADM3052 is examined because it represents the most susceptible
mode of operation.
The pulses at the transformer output have an amplitude greater
than 1 V. The decoder has a sensing threshold of about 0.5 V,
thus establishing a 0.5 V margin in which induced voltages can
be tolerated.
The voltage induced across the receiving coil is given by
⎛ − dβ ⎞
2
V =⎜
⎟∑ πrn ; n = 1, 2, . . . , N
⎝ dt ⎠
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
1
0.1
0.01
0.001
1k
100M
Figure 31. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse and
is the worst-case polarity, it reduces the received pulse from
>1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of
the decoder.
Figure 32 shows the magnetic flux density values in terms of
more familiar quantities, such as maximum allowable current
flow at given distances away from the ADM3052 transformers.
1000
DISTANCE = 1m
100
DISTANCE = 5mm
10
DISTANCE = 100mm
1
0.1
0.01
1k
Given the geometry of the receiving coil and an imposed
requirement that the induced voltage is, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field can be determined using Figure 31.
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
09292-012
The linear regulator takes the V+ bus power (ranging between
11 V to 25 V) and regulates this voltage to 5 V to provide power
to the internal bus-side circuitry (iCoupler isolation, V+SENSE, and
transceiver circuits). The linear regulator uses two regulation
loops to share the power dissipation between the internal die and
an external resistor. This reduces the internal heat dissipation in
the package. The 300 Ω external resistor should be capable of
dissipating 750 mW of power and have a tolerance of 1%.
10
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
09292-013
LINEAR REGULATOR
MAXIMUM ALLOWABLE CURRENT (kA)
The ADM3052 contains thermal shutdown circuitry that protects
the part from excessive power dissipation during fault conditions.
Shorting the driver outputs to a low impedance source can result
in high driver currents. The thermal sensing circuitry detects the
increase in die temperature under this condition and disables the
driver outputs. This circuitry is designed to disable the driver
outputs when a junction temperature of 150°C is reached. As
the device cools, the drivers reenable at a temperature of 140°C.
MAXIMUM ALLOWABLE MAGNETIC
FLUX DENSITY (kGAUSS)
THERMAL SHUTDOWN
Figure 32. Maximum Allowable Current for
Various Current-to-ADM3052 Spacings
With combinations of strong magnetic field and high frequency,
any loops formed by PCB traces can induce error voltages large
enough to trigger the thresholds of succeeding circuitry. Care
should be taken in the layout of such traces to avoid this possibility.
Rev. 0 | Page 16 of 20
ADM3052
APPLICATIONS INFORMATION
TYPICAL APPLICATIONS
3.3V/5V SUPPLY
1µF
100nF
CINT
VDD1
ISOLATION
BARRIER
10µF
ADM3052
VDD2
V+SENSE
DECODE
RP
100nF
V+
BUS
V+SENSE
ENCODE
V+
V+R
LINEAR
REGULATOR
VDD2
CAN
CONTROLLER
BUS
CONNECTOR
PROTECTION
TxD
ENCODE
DECODE
V+
TxD
DRIVER
CANH
CANH
RxD
RxD
RECEIVER
ENCODE
DECODE
VREF
CANL
REFERENCE
VOLTAGE
CANL
V–
GND2
GND2
RL
VREF
GND1
CAN TRANSCEIVER
LOGIC SIDE
BUS SIDE
Figure 33. Typical Isolated CAN Node Using the ADM3052
Rev. 0 | Page 17 of 20
09292-014
V–
DIGITAL ISOLATION
ADM3052
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
1
Figure 34. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADM3052BRWZ
ADM3052BRWZ-REEL7
EVAL-ADM3052EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead SOIC_W
16-Lead SOIC_W
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
Package Option
RW-16
RW-16
ADM3052
NOTES
Rev. 0 | Page 19 of 20
ADM3052
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09292-0-6/11(0)
Rev. 0 | Page 20 of 20
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