Poly Phase Multifunction Energy Metering IC with Per Phase Information ADE7758 Reference 2.4 V (drift 30 ppm/°C typ) with external overdrive capability Single 5 V supply, low power (70 mW typ) FEATURES High accuracy, supports IEC 60687, IEC 61036, IEC 61268, IEC 62053-21, IEC 62053-22, and IEC 62053-23 Compatible with 3-phase/3-wire, 3-phase/4-wire, and other 3-phase services Less than 0.1% active energy error over a dynamic range of 1000 to 1 at 25°C Supplies active/reactive/apparent energy, voltage rms, current rms, and sampled waveform data Two pulse outputs, one for active power and the other selectable between reactive and apparent power with programmable frequency Digital power, phase, and rms offset calibration On-chip user programmable thresholds for line voltage SAG and overvoltage detections On-chip digital integrator enables direct interface-to-current sensors with di/dt output A PGA in the current channel allows direct interface to shunts and current transformers A SPI® compatible serial interface with IRQ Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time GENERAL DESCRIPTION The ADE77581 is a high accuracy 3-phase electrical energy measurement IC with a serial interface and two pulse outputs. The ADE7758 incorporates second-order ∑-∆ ADCs, a digital integrator, reference circuitry, temperature sensor, and all the signal processing required to perform active, reactive, and apparent energy measurement and rms calculations. The ADE7758 is suitable to measure active, reactive, and apparent energy in various 3-phase configurations, such as WYE or DELTA services, both with three or four wires. The ADE7758 provides system calibration features for each phase, i.e., rms offset correction, phase calibration, and power calibration. The APCF logic output gives active power information, and the VARCF logic output provides instantaneous reactive or apparent power information. (Continued on Page 4) FUNCTIONAL BLOCK DIAGRAM AVDD REFIN/OUT AGND 4 12 11 ADE7758 X2 POWER SUPPLY MONITOR AVAG[11:0] AVRMSGAIN[11:0] AVRMSOS[11:0] 4kΩ X2 REACTIVE OR APPARENT POWER LPF AIGAIN[11:0] IAP 5 PGA1 + IAN 6 – 90° PHASE SHIFTING FILTER ADC DFC 2 INTEGRATOR ADC – IBP 7 IBN 8 – Φ APHCAL[6:0] ADC PGA2 + VBP 15 ADC ICP 9 PGA1 + ICN 10 PGA2 + ADC VN 13 1 ACTIVE/REACTIVE/APPARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE B (SEE PHASE A FOR DETAILED SIGNAL PATH) PHASE B AND PHASE C DATA AWG[11:0] ACTIVE POWER APCFNUM[11:0] % VADIV[7:0] % VARDIV[7:0] DFC % WDIV[7:0] – VCP 14 AWATTOS[11:0] – ADC 17 VARCF VARCFDEN[11:0] AVARG[11:0] LPF2 PGA1 + ÷ LPF2 AVAROS[11:0] PGA2 + VAP 16 π dt HPF VARCFNUM[11:0] AIRMSOS[11:0] ACTIVE/REACTIVE/APPARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE C (SEE PHASE A FOR DETAILED SIGNAL PATH) ÷ APCFDEN[11:0] ADE7758 REGISTERS AND SERIAL INTERFACE 1 APCF 3 DVDD 2 DGND 19 CLKIN – 20 CLKOUT 22 24 23 21 18 DIN DOUT SCLK CS IRQ 04443-0-001 2.4V REF Patents Pending. Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADE7758 TABLE OF CONTENTS Specifications..................................................................................... 5 Active Power Calculation .......................................................... 30 Timing Characteristics..................................................................... 7 Reactive Power Calculation ...................................................... 35 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Apparent Power Calculation..................................................... 38 Energy Registers Scaling ........................................................... 41 Terminology .................................................................................... 12 Waveform Sampling Mode ....................................................... 41 Typical Performance Characteristics ........................................... 13 Calibration................................................................................... 41 Theory of Operation ...................................................................... 19 Checksum Register..................................................................... 54 Antialiasing Filter ....................................................................... 19 Analog Inputs.............................................................................. 19 Current Channel ADC............................................................... 20 di/dt Current Sensor and Digital Integrator ........................... 21 Peak Current Detection ............................................................. 22 Overcurrent Detection Interrupt ............................................. 22 Voltage Channel ADC ............................................................... 22 Zero-Crossing Detection........................................................... 24 Phase Compensation.................................................................. 24 Period Measurement .................................................................. 26 Line Voltage SAG Detection ..................................................... 26 SAG Level Set.............................................................................. 26 Peak Voltage Detection.............................................................. 26 Phase Sequence Detection......................................................... 27 Power-Supply Monitor............................................................... 27 ADE7758 Interrupts................................................................... 54 Using the ADE7758 Interrupts with an MCU........................ 54 Interrupt Timing ........................................................................ 55 ADE7758 Serial Interface.......................................................... 55 ADE7758 Serial Write Operation ............................................ 56 ADE7758 Serial Read Operation ............................................. 57 Accessing the ADE7758 On-Chip Registers........................... 58 Communications Register......................................................... 58 Operational Mode Register (0x13) .......................................... 61 Measurement Mode Register (0x14) ....................................... 62 Waveform Mode Register (0x15) ............................................. 62 Computational Mode Register (0x16)..................................... 63 Line Cycle Accumulation Mode Register (0x17) ................... 64 Interrupt Mask Register (0x18) ................................................ 65 Reference Circuit ........................................................................ 28 Interrupt Status Register (0x19)/Reset Interrupt Status Register (0x1A)........................................................................... 66 Temperature Measurement ....................................................... 28 Outline Dimensions ....................................................................... 67 Root Mean Square Measurement ............................................. 28 Ordering Guide .......................................................................... 67 Rev. A | Page 2 of 68 ADE7758 REVISION HISTORY 9/04—Changed from Rev. 0 to Rev. A Changed Hexadecimal Notation ...................................... Universal Changes to Features List...................................................................1 Changes to Specifications Table ......................................................5 Change to Figure 25 ........................................................................16 Additions to the Analog Inputs Section.......................................19 Added Figures 36 and 37; Renumbered Subsequent Figures ....19 Changes to Period Measurement Section ....................................26 Change to Peak Voltage Detection Section..................................26 Added Figure 60 ..............................................................................27 Change to the Current RMS Offset Compensation Section......29 Edits to Active Power Frequency Output Section.......................33 Added Figure 68; Renumbered Subsequent Figures ..................33 Changes to Reactive Power Frequency Output Section.............37 Added Figure 73; Renumbered Subsequent Figures ..................38 Change to Gain Calibration Using Pulse Output Example .......44 Changes to Equation 37 .................................................................45 Changes to Example—Phase Calibration of Phase A Using Pulse Output..................................................................45 Changes to Equations 56 and 57 ...................................................53 Addition to the ADE7758 Interrupts Section .............................54 Changes to Example-Calibration of RMS Offsets ......................54 Addition to Table 20 .......................................................................66 1/04—Revision 0: Initial Version Rev. A | Page 3 of 68 ADE7758 GENERAL DESCRIPTION (Continued from Page 1) The ADE7758 has a waveform sample register that allows access to the ADC outputs. The part also incorporates a detection circuit for short duration low or high voltage variations. The voltage threshold levels and the duration (number of half-line cycles) of the variation are user programmable. A zero-crossing detection is synchronized with the zero-crossing point of the line voltage of any of the three phases. This information can be used to measure the period of any one of the three voltage inputs. It is also used internally to the chip in the line cycle energy accumulation mode. This mode permits faster and more accurate calibration by synchronizing the energy accumulation with an integer number of line cycles. Data is read from the ADE7758 via the SPI serial interface. The interrupt request output (IRQ) is an open-drain, active low logic output. The IRQ output goes active low when one or more interrupt events have occurred in the ADE7758. A status register indicates the nature of the interrupt. The ADE7758 is available in a 24-lead SOIC package. Rev. A | Page 4 of 68 ADE7758 SPECIFICATIONS1, 2 AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter ACCURACY Active Energy Measurement Error (per Phase) Phase Error between Channels (PF = 0.8 Capacitive) (PF = 0.5 Inductive) AC Power Supply Rejection1 Output Frequency Variation DC Power Supply Rejection1 Output Frequency Variation Active Power Measurement Bandwidth IRMS Measurement Error IRMS Measurement Bandwidth VRMS Measurement Error VRMS Measurement Bandwidth ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) ADC Offset Error3 Gain Error1, 3 WAVEFORM SAMPLING Current Channels Signal-to-Noise Plus Distortion Bandwidth (−3 dB) Voltage Channels Signal-to-Noise Plus Distortion Bandwidth (−3 dB) REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS DIN, SCLK, CLKIN, and CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Specification Unit Test Conditions/Comments 0.1 % typ Over a dynamic range of 1000 to 1 ±0.05 ±0.05 °max °max 0.01 % typ 0.01 14 0.5 14 0.5 260 % typ kHz % typ kHz % typ Hz ±500 380 30 ±6 mV max kΩ min mV max % typ 62 14 dB typ kHz 62 180 dB typ Hz 2.7 2.3 10 V max V min pF max Line frequency = 45 Hz to 65 Hz, HPF on Phase lead 37° Phase lag 60° AVDD = DVDD = 5 V + 175 mV rms/120 Hz V1P = V2P = V3P = 100 mV rms AVDD = DVDD = 5 V ± 250 mV dc V1P = V2P = V3P = 100 mV rms Over a dynamic range of 500:1 Over a dynamic range of 20:1 See the Analog Inputs section Differential input Uncalibrated error, see the Terminology section External 2.5 V reference Sampling CLKIN/128, 10 MHz/128 = 78.1 kSPS See the Current Channel ADC section See the Voltage Channel ADC section 2.5 V + 8% 2.5 V – 8% Nominal 2.4 V at REFIN/OUT pin ±200 6 4 30 mV max µA max kΩ min ppm/°C typ 15 5 MHz max MHz min 2.4 0.8 ±3 10 V min V max µA max pF max All specifications CLKIN of 10 MHz Rev. A | Page 5 of 68 DVDD = 5 V ± 5% DVDD = 5 V ± 5% Typical 10 nA, VIN = 0 V to DVDD ADE7758 Parameter LOGIC OUTPUTS IRQ, DOUT, and CLKOUT Output High Voltage, VOH Output Low Voltage, VOL APCF and VARCF Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY AVDD DVDD AIDD DIDD Specification Unit 4 0.4 V min V max 4 1 V min V max 4.75 5.25 4.75 5.25 8 13 V min V max V min V max mA max mA max 1 See the Terminology section for a definition of the parameters. See the Typical Performance Characteristics. 3 See the Analog Inputs section. 2 Rev. A | Page 6 of 68 Test Conditions/Comments DVDD = 5 V ± 5% IRQ is open-drain, 10 kΩ pull-up resistor ISOURCE = 5 mA ISINK = 1 mA ISOURCE = 8 mA ISINK = 5 mA For specified performance 5 V − 5% 5 V + 5% 5 V − 5% 5 V + 5% Typically 5 mA Typically 9 mA ADE7758 TIMING CHARACTERISTICS1, 2 AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 2. Parameter Write Timing t1 t2 t3 t4 t5 t6 t7 t8 Read Timing t9 t10 t113 t124 t134 Specification Unit Test Conditions/Comments 50 50 50 10 5 900 50 100 ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) CS falling edge to first SCLK falling edge. SCLK logic high pulse width. SCLK logic low pulse width. Valid data setup time before falling edge of SCLK. Data hold time after SCLK falling edge. Minimum time between the end of data byte transfers. Minimum time between byte transfers during a serial write. CS hold time after SCLK falling edge. 1.1 50 30 100 10 100 10 µs (min) ns (min) ns (min) ns (max) ns (min) ns (max) ns (min) Minimum time between read command (i.e., a write to communication register) and data read. Minimum time between data byte transfers during a multibyte read. Data access time after SCLK rising edge following a write to the communications register. Bus relinquish time after falling edge of SCLK. Bus relinquish time after rising edge of CS. 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2 See the timing diagrams in Figure 3 and Figure 4 and the ADE7758 Serial Interface section. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 200µA 2.1V CL 50pF 1.6mA IOH 04443-0-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Timing Specifications Rev. A | Page 7 of 68 ADE7758 t8 CS t6 t3 t7 t7 SCLK t4 t2 1 DIN A6 A5 A4 t5 A3 A2 A1 DB7 A0 MOST SIGNIFICANT BYTE COMMAND BYTE DB0 DB7 DB0 LEAST SIGNIFICANT BYTE 04443-0-003 t1 Figure 3. Serial Write Timing CS t1 t13 t9 SCLK 0 A6 A5 A4 A3 A2 A1 A0 t12 t11 DOUT DB7 COMMAND BYTE DB0 MOST SIGNIFICANT BYTE Figure 4. Serial Read Timing Rev. A | Page 8 of 68 DB7 DB0 LEAST SIGNIFICANT BYTE 04443-0-004 DIN t10 ADE7758 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 24-Lead SOIC, Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) –0.3 V to +7 V –0.3 V to +7 V –0.3 V to +0.3 V –6 V to +6 V –0.3 V to AVDD + 0.3 V –0.3 V to DVDD + 0.3 V –0.3 V to DVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. –40°C to +85°C –65°C to +150°C 150°C 88 mW 53°C/W 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 9 of 68 ADE7758 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS APCF 1 24 DOUT DGND 2 23 SCLK DVDD 3 22 DIN AVDD 4 21 CS IAP 5 ADE7758 20 CLKOUT 19 CLKIN TOP VIEW IBP 7 (Not to Scale) 18 IRQ IBN 8 17 VARCF ICP 9 16 VAP ICN 10 15 VBP AGND 11 14 VCP REFIN/OUT 12 13 VN 04443-0-011 IAN 6 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic APCF 2 DGND 3 DVDD 4 AVDD 5, 6; 7, 8; 9, 10 IAP, IAN; IBP, IBN; ICP, ICN 11 AGND 12 REFIN/OUT 13, 14, 15, 16 VN, VCP, VBP, VAP Description Active Power Calibration Frequency (APCF) Logic Output. It provides active power information. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the APCFNUM and APCFDEN registers (see the Active Power Frequency Output section). This provides the ground reference for the digital circuitry in the ADE7758, i.e., the multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7758 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. However, high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance. Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7758. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7758. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The Typical Performance Characteristics graphs show the power supply rejection performance. This pin should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. Analog Inputs for Current Channel. This channel is used with the current transducer and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs sections). All inputs have internal ESD protection circuitry, and in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7758, i.e., ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, antialiasing filters, current, and voltage transducers. In order to keep ground noise around the ADE7758 to a minimum, the quiet ground plane should only be connected to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic capacitor. Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is referenced as the voltage channels in this document. These inputs are single-ended voltage inputs with the maximum signal level of ±0.5 V with respect to VN for specified operation. These inputs are voltage inputs with maximum input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs section). All inputs have internal ESD protection circuitry, and in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. Rev. A | Page 10 of 68 ADE7758 Pin No. 17 Mnemonic VARCF 18 IRQ 19 CLKIN 20 CLKOUT 21 CS 22 DIN 23 SCLK 24 DOUT Description Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and VARCFDEN registers (see the Reactive Power Frequency Output section). Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include: active energy register at half level, apparent energy register at half level, and waveform sampling up to 26 kSPS (see the ADE7758 Interrupts section). Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7758. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of a few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance requirements A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the ADE7758. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial bus with several other devices (see the ADE7758 Serial Interface section). Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the ADE7758 Serial Interface section). Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock (see the ADE7758 Serial Interface section). The SCLK has a Schmidt-trigger input for use with a clock source which has a slow edge transition time, for example, opto-isolator outputs. Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state, unless it is driving data onto the serial data bus (see the ADE7758 Serial Interface section). Rev. A | Page 11 of 68 ADE7758 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7758 is defined by the following formula Measuremen t Error = Energy Registered by ADE7758 – True Energy × 100% True Energy Phase Error between Channels The high-pass filter and digital integrator introduce a slight phase mismatch between the current and the voltage channel. The all-digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers. Power Supply Rejection This quantifies the ADE7758 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (175 mV rms/100 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typical Performance Characteristics section). However, when HPFs are switched on, the offset is removed from the current channels and the power calculation is not affected by this offset. Gain Error The gain error in the ADCs of the ADE7758 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC and Voltage Channel ADC sections). The difference is expressed as a percentage of the ideal code. Gain Error Match The gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1, 2, or 4. It is expressed as a percentage of the output ADC code obtained under a gain of 1. Rev. A | Page 12 of 68 ADE7758 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.20 PF = 1 0.4 0.15 0.3 PERCENT ERROR (%) PERCENT ERROR (%) 0.10 0.2 0.1 +25°C 0 –40°C –0.1 –0.2 PF = +0.5, –40°C 0.05 PF = –0.5, +25°C 0 –0.05 PF = +0.5, +85°C PF = +0.5, +25°C –0.10 04443-0-060 +85°C –0.4 –0.5 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 04443-0-063 –0.3 –0.15 –0.20 0.01 100 Figure 6. Active Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 9. Active Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with External Reference and Integrator Off 0.3 0.6 0.5 PF = +0.5, +25°C PF = +1, +25°C 0 –0.1 PF = –0.5, +25°C PF = +0.5, +85°C –0.2 PF = +0.5, –40°C –0.3 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) PF = 1 0.3 0.2 0.1 PF = 0.5 0 –0.1 –0.2 04443-0-065 0.1 PERCENT ERROR (%) WITH RESPECT TO 55Hz 0.4 04443-0-061 PERCENT ERROR (%) 0.2 –0.3 –0.4 45 100 Figure 7. Active Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with Internal Reference and Integrator Off 47 49 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 65 Figure 10. Active Energy Error as a Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off 0.3 0.10 PF = 1 PF = 1 0.08 0.2 0.1 GAIN = +4 0 –0.1 GAIN = +1 GAIN = +2 –0.3 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) VDD = 5.25V 0.02 –0.0 VDD = 5V –0.2 –0.04 –0.06 04443-0-062 –0.2 0.04 VDD = 4.75V 04443-0-066 PERCENT ERROR (%) WITH RESPECT TO 5V; 3A PERCENT ERROR (%) 0.06 –0.08 –0.10 0.01 100 Figure 8. Active Energy Error as a Percentage of Reading over Gain with Internal Reference and Integrator Off 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 11. Active Energy Error as a Percentage of Reading (Gain = +1) over Power Supply with Internal Reference and Integrator Off Rev. A | Page 13 of 68 ADE7758 0.3 0.25 PF = 1 0.20 0.2 0.15 0.10 PERCENT ERROR (%) ALL PHASES 0.05 0 –0.05 PHASE B PHASE C –0.10 –0.15 –0.25 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.1 PF = 0, +25°C PF = 0, –40°C –0.3 0.01 100 Figure 12. APCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off PF = 0, +85°C 0 –0.2 04443-0-067 –0.20 0.1 04443-0-070 PERCENT ERROR (%) PHASE A 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Temperature with External Reference and Integrator Off 0.4 0.3 PF = +0.866, –40°C 0.3 0.2 PF = –0.866, +25°C PERCENT ERROR (%) 0.1 PF = 0, +25°C 0 PF = 0, –40°C –0.1 –0.2 PF = 0, +25°C –0.1 PF = +0.866, +85°C –0.3 0.01 100 0.8 0.6 0.6 PERCENT ERROR (%) WITH RESPECT TO 55Hz PF = 0, +25°C 0.2 PF = –0.866, +25°C 0 –0.2 PF = +0.866, –40°C PF = +0.866, +25°C –0.4 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with External Reference and Integrator Off 0.8 0.4 PF = +0.866, +25°C –0.2 04443-0-068 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off PERCENT ERROR (%) 0 PF = 0, +85°C –0.3 –0.4 0.01 0.1 04443-0-071 PERCENT ERROR (%) 0.2 0.4 PF = 0 0.2 0 –0.2 PF = 0.866 –0.4 –0.6 –0.8 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.6 –0.8 45 100 Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with Internal Reference and Integrator Off 04443-0-072 04443-0-069 PF = +0.866, +85°C 47 49 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 65 Figure 17. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off Rev. A | Page 14 of 68 ADE7758 0.10 0.3 0.08 0.2 5.25V 0.04 PERCENT ERROR (%) 5V 0.02 0 –0.02 –0.04 0 +25°C –0.1 4.75V +85°C –0.06 –0.10 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.3 0.01 100 Figure 18. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Supply with Internal Reference and Integrator Off 04443-0-076 –0.2 04443-0-073 –0.08 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 21. Active Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.3 0.5 PF = 0 0.2 0.4 0.3 GAIN = +2 GAIN = +4 PERCENT ERROR (%) PERCENT ERROR (%) –40°C 0.1 0.1 0 GAIN = +1 –0.1 0.2 04443-0-074 –0.3 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 0 –0.1 PF = +1, +25°C PF = –0.5, +25°C –0.2 PF = +0.5, +85°C –0.4 –0.5 0.01 100 Figure 19. Reactive Energy Error as a Percentage of Reading over Gain with Internal Reference and Integrator Off PF = +0.5, +25°C 0.1 –0.3 –0.2 PF = +0.5, –40°C 04443-0-077 PERCENT ERROR (%) WITH RESPECT TO 5V; 3A 0.06 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 22. Active Energy Error as a Percentage of Reading (Gain = +4) over Power Factor with Internal Reference and Integrator On 0.8 0.4 PF = 1 0.6 0.3 PF = –0.866, –40°C PERCENT ERROR (%) PHASE C 0 –0.1 –0.2 PHASE B PHASE A 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) PF = 0, +25°C 0 –0.2 PF = +0.866, +25°C PF = –0.866, +25°C –0.4 –0.3 –0.4 0.01 0.2 –0.6 –0.8 0.01 100 Figure 20. VARCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off PF = –0.866, +85°C 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 04443-0-078 0.1 0.4 ALL PHASES 04443-0-075 PERCENT ERROR (%) 0.2 100 Figure 23. Active Energy Error as a Percentage of Reading (Gain = +4) over Power Factor with Internal Reference and Integrator On Rev. A | Page 15 of 68 ADE7758 0.4 0.8 PF = 0 0.6 0.3 0.4 –40°C PERCENT ERROR (%) 0.1 0 +25°C –0.1 –0.2 0 –0.2 PF = 0.5 –0.4 –0.6 PF = 1 –0.3 +85°C –0.5 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –1.0 –1.2 0.01 100 Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 27. IRMS Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.5 0.8 0.4 0.6 0.3 0.4 PERCENT ERROR (%) 0.2 0.1 0 PF = 0.5 –0.1 –0.2 PF = 1 0.2 PF = –0.5 0 PF = +1 –0.2 –0.4 –0.6 04443-0-080 –0.3 –0.4 –0.5 45 04443-0-082 04443-0-079 –0.8 –0.4 PERCENT ERROR (%) 0.2 47 49 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 04443-0-083 PERCENT ERROR (%) 0.2 –0.8 –1.0 0.1 65 Figure 25. Active Energy Error as a Percentage of Reading (Gain = +4) over Frequency with Internal Reference and Integrator On 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 28. IRMS Error as a Percentage of Reading (Gain = +4) with Internal Reference and Integrator On 1.2 0.4 1.0 0.3 0.8 0.4 PERCENT ERROR (%) PERCENT ERROR (%) 0.2 0.6 PF = 0 0.2 0 PF = 0.866 –0.2 0.1 0 –0.1 –0.2 –0.6 –0.8 45 47 49 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 04443-0-084 04443-0-081 –0.4 –0.3 –0.4 1 65 Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Frequency with Internal Reference and Integrator On Rev. A | Page 16 of 68 10 VOLTAGE (V) 100 Figure 29. VRMS Error as a Percentage of Reading (Gain = +1) with Internal Reference ADE7758 1.5 21 MEAN: 6.5149 SD: 2.816 18 1.0 15 0.5 +25°C HITS 0 12 9 –0.5 6 +85°C 3 04443-0-085 –1.0 –1.5 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 04443-0-089 PERCENT ERROR (%) –40°C 0 –2 100 Figure 30. Apparent Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 0 2 4 6 8 CH 1 PhB OFFSET (mV) 10 12 Figure 32. Phase B Channel 1 Offset Distribution 12 MEAN: 5.55393 SD: 3.2985 MEAN: 6.69333 SD: 2.70443 18 10 15 8 HITS HITS 12 6 9 4 6 0 –4 –2 0 2 4 6 8 CH 1 PhA OFFSET (mV) 10 04443-0-090 2 04443-0-088 3 0 12 2 Figure 31. Phase A Channel 1 Offset Distribution 4 6 8 10 CH 1 PhC OFFSET (mV) 12 14 Figure 33. Phase C Channel 1 Offset Distribution Rev. A | Page 17 of 68 ADE7758 VDD CURRENT 10µF TRANSFORMER I 100nF 4 RB 3 17 AVDD DVDD VARCF APCF 1 5 IAP 1kΩ 33nF 825Ω PS2501-1 1 4 2 3 TO FREQ. COUNTER ADE7758 1kΩ 6 IAN 22pF 33nF CLKOUT 20 7 IBP SAME AS IAP, IAN 10MHz CLKIN 19 8 IBN 22pF SAME AS IAP, IAN 9 ICP DOUT 24 10 ICN SCLK 23 1MΩ 220V DIN 22 33nF 1kΩ IRQ 18 SAME AS VAP 15 VBP SAME AS VAP 14 VCP CT TURN RATIO 1800:1 CHANNEL 2 GAIN = +1 REFIN/OUT 12 VN 13 1kΩ 100nF AGND DGND 11 10µF 2 33nF CHANNEL 1 GAIN RB 10Ω 5Ω 2.5Ω 1.25Ω 04443-0-086 1 2 4 8 TO SPI BUS ONLY USED FOR CALIBRATION CS 21 16 VAP Figure 34. Test Circuit for Integrator Off VDD di/dt SENSOR I 10µF 100nF 4 1kΩ 1kΩ 33nF 33nF 1kΩ 1kΩ 33nF 3 17 AVDD DVDD VARCF APCF 1 5 IAP 825Ω PS2501-1 1 4 2 3 TO FREQ. COUNTER ADE7758 6 IAN 22pF 33nF CLKOUT 20 7 IBP SAME AS IAP, IAN 10MHz CLKIN 19 8 IBN 22pF SAME AS IAP, IAN 9 ICP DOUT 24 10 ICN SCLK 23 1MΩ CS 21 16 VAP 1kΩ 33nF SAME AS VAP SAME AS VAP CHANNEL 1 GAIN = +8 CHANNEL 2 GAIN = +1 IRQ 18 15 VBP 14 VCP 1kΩ REFIN/OUT 12 VN 13 AGND DGND 11 100nF 10µF 2 33nF Figure 35. Test Circuit for Integrator On Rev. A | Page 18 of 68 04443-0-087 220V TO SPI BUS ONLY USED FOR CALIBRATION DIN 22 ADE7758 THEORY OF OPERATION ANALOG INPUTS The ADE7758 has a total of six analog inputs divided into two channels: current and voltage. The current channel consists of three pairs of fully differential voltage inputs: IAP and IAN, IBP and IBN, and ICP and ICN. These fully differential voltage input pairs have a maximum differential signal of ±0.5 V. The current channel has a programmable gain amplifier (PGA) with possible gain selection of 1, 2, or 4. In addition to the PGA, the current channels also have a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the gain register (see Figure 38). As mentioned previously, the maximum differential input voltage is ±0.5 V. However, by using Bit 3 and Bit 4 in the gain register, the maximum ADC input voltage can be set to ±0.5 V, ±0.25 V, or ±0.125 V on the current channels. This is achieved by adjusting the ADC reference (see the Reference Circuit section). Figure 36 shows the maximum signal levels on the current channel inputs. The maximum common-mode signal is ±25 mV as shown in Figure 36. Figure 37 shows the maximum signal levels on the voltage channel inputs. The maximum common-mode signal is ±25 mV as shown in Figure 36. V2 +500mV SINGLE-ENDED INPUT ±500mV MAX PEAK COMMON-MODE ±25mV MAX VCM Figure 37. Maximum Signal Levels, Voltage Channels, Gain = 1 The gain selections are made by writing to the gain register. Bit 0 to Bit 1 select the gain for the PGA in the fully differential current channel. The gain selection for the PGA in the singleended voltage channel is made via Bit 5 to Bit 6. Figure 38 shows how a gain selection for the current channel is made using the gain register. GAIN[7:0] GAIN (K) SELECTION IAP, IBP, ICP K × VIN VIN IAN, IBN, ICN Figure 39 shows how the gain settings in PGA 1 (current channel) and PGA 2 (voltage channel) are selected by various bits in the gain register. GAIN REGISTER* CURRENT AND VOLTAGE CHANNEL PGA CONTROL 7 6 5 4 3 2 1 0 IAP, IBP, OR ICP V1 IAN, IBN, OR ICN –500mV 04443-0-108 V2 Figure 36. Maximum Signal Levels, Current Channels, Gain = 1 The voltage channel has three single-ended voltage inputs: VAP, VBP, and VCP. These single-ended voltage inputs have a maximum input voltage of ±0.5 V with respect to VN. Both the current and voltage channel have a PGA with possible gain selections of 1, 2, or 4. The same gain is applied to all the inputs of each channel. INTEGRATOR ENABLE 0 = DISABLE 1 = ENABLE PGA 2 GAIN SELECT 00 = ×1 01 = ×2 10 = ×4 0 0 0 0 0 0 RESERVED 0 ADDRESS: 0x23 PGA 1 GAIN SELECT 00 = ×1 01 = ×2 10 = ×4 CURRENT INPUT FULL-SCALE SELECT 00 = 0.5V 01 = 0.25V 10 = 0.125V *REGISTER CONTENTS SHOW POWER-ON DEFAULTS 04443-A-013 0 VCM VCM VN AGND –500mV +500mV COMMON-MODE ±25mV MAX V2 VCM Figure 38. PGA in Current Channel V1 + V 2 DIFFERENTIAL INPUT V1 + V2 = 500mV MAX PEAK VAP, VBP, OR VCP 04443-0-109 The need for this filter is that it prevents aliasing. Aliasing is an artifact of all sampled systems. Input signals with frequency components higher than half the ADC sampling rate distort the sampled signal at a frequency below half the sampling rate. This will happen with all ADCs, regardless of the architecture. The combination of the high sampling rate ∑-∆ ADC used in the ADE7758 with the relatively low bandwidth of the energy meter allows a very simple low-pass filter (LPF) to be used as an antialiasing filter. A simple RC filter (single pole) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 833 kHz. This is usually sufficient to eliminate the effects of aliasing. 04443-0-012 ANTIALIASING FILTER Figure 39. ADE7758 Analog Gain Register Bit 7 of the gain register is used to enable the digital integrator in the current signal path. Setting this bit will activate the digital integrator (see the di/dt Current Sensor and Digital Integrator section). Rev. A | Page 19 of 68 ADE7758 CURRENT CHANNEL ADC Current Channel Sampling Figure 41 shows the ADC and signal processing path for the input IA of the current channels (same for IB and IC). In waveform sampling mode, the ADC outputs are signed twos complement 24-bit data-words at a maximum of 26.0 kSPS (thousand samples per second). With the specified full-scale analog input signal of ±0.5 V, the ADC produces its maximum output code value (see Figure 41). This diagram shows a fullscale voltage signal being applied to the differential inputs IAP and IAN. The ADC output swings between 0xD7AE14 (−2,642,412) and 0x2851EC (+2,642,412). The waveform samples of the current channel can be routed to the WFORM register at fixed sampling rates by setting the WAVSEL[2:0] bit in the WAVMODE register to 000 (binary). The phase in which the samples are routed is set by setting the PHSEL[1:0] bits in the WAVMODE register. Energy calculation remains uninterrupted during waveform sampling. When in waveform sample mode, one of four output sample rates may be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate may be 26.0 kSPS, 13.0 kSPS, 6.5 kSPS, or 3.3 kSPS (see Table 16). By setting the WSMP bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The timing is shown in Figure 40. The 24-bit waveform samples are transferred from the ADE7758 one byte (8-bits) at a time, with the most significant byte shifted out first. Current Waveform Gain Registers There is a multiplier in the signal path in the current channel for each phase. The current waveform can be changed by ±50% by writing a twos complement number to the 12-bit signed current waveform gain registers (AIGAIN[11:0], BIGAIN[11:0], and CIGAIN[11:0]). For example, if 0x7FF is written to those registers, the ADC output is scaled up by +50%. On the other hand, writing 0x800 scaled by the output –50%. The expression below describes mathematically the function of the current waveform gain registers. IRQ SCLK READ FROM WAVEFORM 12Hex 0 DOUT SGN CURRENT CHANNEL DATA–24 BITS Current Waveform = Figure 40. Current Channel Waveform Sampling ⎛ Content of Current Gain Register ⎞ ADC Output × ⎜1 + ⎟ 212 ⎝ ⎠ The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see ADE7758 Interrupts). Changing the content of AIGAIN[11:0], BIGAIN[11:0], or CIGAIN[11:0] affects all calculations based on its current, i.e., it affects the phase’s active/reactive/apparent energy as well as its current rms calculation. In addition, waveform samples are also scaled accordingly. GAIN[4:3] 2.42V, 1.21V, 0.6V REFERENCE IAP PGA1 VIN GAIN[7] AIGAIN[11:0] GAIN[1:0] ×1, ×2, ×4 DIGITAL INTEGRATOR* ADC HPF CURRENT RMS (IRMS) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION IAN 50Hz CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (50Hz AND AIGAIN[11:0] = 0x000) 0x34D1B8 CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE 0x2851EC 0V 0x000000 ANALOG INPUT RANGE 0x000000 0xCB2E48 60Hz CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (60Hz AND AIGAIN[11:0] = 0x000) 0x2BE893 0xD7AE14 ADC OUTPUT WORD RANGE 0x000000 0xD4176D Figure 41. Current Channel Signal Path Rev. A | Page 20 of 68 04443-A-014 VIN 0.5V/GAIN 0.25V/GAIN 0.125V/GAIN 04443-0-015 DIN ADE7758 di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR 80 The di/dt sensor detects changes in the magnetic field caused by the ac current. Figure 42 shows the principle of a di/dt current sensor. 82 81 PHASE (Degrees) MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT) 83 84 85 86 87 88 04443-0-092 89 04443-0-017 90 + EMF (ELECTROMOTIVE FORCE) – INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt) 91 10 Figure 42. Principle of a di/dt Current Sensor 100 1k FREQUENCY (Hz) 10k Figure 44. Combined Phase Response of the Digital Integrator and Phase Compensator 4 3 2 1 0 –1 40 04443-0-093 The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7758 has a builtin digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched on by default when the ADE7758 is powered up. Setting the MSB of the GAIN[7:0] register turns on the integrator. Figure 43 to Figure 46 show the magnitude and phase response of the digital integrator. 5 MAGNITUDE (dB) The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. 45 50 55 60 FREQUENCY (Hz) 65 70 Figure 45. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) 20 89.80 89.85 –10 89.90 PHASE (Degrees) 0 –20 –30 89.95 90.00 –40 –50 10 100 1k FREQUENCY (Hz) 90.05 04443-0-094 04443-0-091 GAIN (dB) 10 10k 90.10 40 Figure 43. Combined Gain Response of the Digital Integrator and Phase Compensator 45 50 55 60 FREQUENCY (Hz) 65 Figure 46. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) Rev. A | Page 21 of 68 70 ADE7758 Note that the integrator has a −20 dB/dec attenuation and approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt sensor has a 20 dB/dec gain associated with it and generates significant high frequency noise. A more effective antialiasing filter is needed to avoid noise due to aliasing (see the Theory of Operation section). When the digital integrator is switched off, the ADE7758 can be used directly with a conventional current sensor, such as a current transformer (CT) or a low resistance current shunt. Note that the number of half-line cycles is based on counting the zero crossing of the voltage channel. The ZXSEL[2:0] bits in the LCYCMODE register determine which voltage channels are used for the zero-crossing detection. The same signal is also used for line cycle energy accumulation mode if activated (see the Line Cycle Accumulation Mode Register (0x17) section). OVERCURRENT DETECTION INTERRUPT Figure 48 illustrates the behavior of the overcurrent detection. CURRENT PEAK WAVEFORM BEING MONITORED (SELECTED BY PKIRQSEL[2:0] IN MMODE REGISTER) PEAK CURRENT DETECTION IPINTLVL[7:0] The ADE7758 can be programmed to record the peak of the current waveform and produce an interrupt if the current exceeds a preset limit. Peak Current Detection Using the PEAK Register The peak absolute value of the current waveform within a fixed number of half-line cycles is stored in the IPEAK register. Figure 47 illustrates the timing behavior of the peak current detection. PKI INTERRUPT FLAG (BIT 15 OF STATUS REGISTER) L2 READ RSTATUS REGISTER 04443-0-023 PKI RESET LOW WHEN RSTATUS REGISTER IS READ L1 Figure 48. ADE7758 Overcurrent Detection NO. OF HALF LINE CYCLES SPECIFIED BY LINECYC[15:0] REGISTER CONTENT OF IPEAK[7:0] 00 L1 L2 L1 04443-0-022 CURRENT WAVEFORM (PHASE SELECTED BY PEAKSEL[2:0] IN MMODE REGISTER) Figure 47. Peak Current Detection Using the IPEAK Register Note that the content of the IPEAK register is equivalent to Bit 14 to Bit 21 of the current waveform sample. At full-scale analog input, the current waveform sample is 0x2851EC . The IPEAK at full-scale input is therefore expected to be 0xA1. In addition, multiple phases can be activated for the peak detection simultaneously by setting multiple bits to logic high among the PEAKSEL[2:4] bits in the MMODE register. These bits select the phase for both voltage and current peak measurements. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, that is, the voltage and current peak are independently processed (see the Peak Current Detection section). Note that the content of the IPINTLVL[7:0] register is equivalent to Bit 14 to Bit 21 of the current waveform sample. Therefore, setting this register to A1 (hex) represents putting peak detection at full-scale analog input. Figure 48 shows a current exceeding a threshold. The overcurrent event is recorded by setting the PKI flag (Bit 15) in the interrupt status register. If the PKI enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low (see the ADE7758 Interrupts section). Similar to peak level detection, multiple phases can be activated for peak detection. If any of the active phase produces waveform samples above the threshold, the PKI flag in the interrupt status register is set. The phase of which overcurrent is monitored is set by the PKIRQSEL[2:0] bits in the MMODE register (see Table 15). VOLTAGE CHANNEL ADC Figure 49 shows the ADC and signal processing chain for the input VA in the voltage channel (same for VB and VC). Rev. A | Page 22 of 68 ADE7758 PHASE CALIBRATION VAP GAIN[6:5] ×1, ×2, ×4 PHCAL[6:0] + PGA – VA TO ACTIVE AND REACTIVE ENERGY CACLULATION Φ TO VOLTAGE RMS CALCULATION AND WAVEFORM SAMPLING ADC LPF1 VN 50Hz LPF OUTPUT WORD RANGE 0x2797 VA 0x0 ANALOG INPUT RANGE 0.5V GAIN 0x2852 0xD869 0x0 0V 60Hz 0xD7AE LPF OUTPUT WORD RANGE 0x2748 04443-A-024 0x0 0xD8B8 Figure 49. ADC and Signal Processing in Voltage Channel 0 0 (60Hz; –0.2dB) –20 (60Hz; –13°) –40 –20 –60 –30 Voltage Channel Sampling The waveform samples on the voltage channels can also be routed to the WFORM register. However, before passing to the WFORM register, the ADC outputs pass through a single-pole, low-pass filter (LPF1) with a cutoff frequency at 260 Hz. Figure 50 shows the magnitude and phase response of LPF1. This filter attenuates the signal slightly. For example, if the line frequency is 60 Hz, the signal at the output of LPF1 is attenuated by 3.575%. The waveform samples are 16-bit, twos complement data ranging between 0x2748 (+10,056d) and 0xD8B8 (−10,056d). The data are sign extended to 24 bit in the WFORM register. H(f ) = 1 ⎛ 60 Hz ⎞ ⎟ 1+ ⎜ ⎜ 260 H z ⎟ ⎝ ⎠ = 0.974 = −0.225 dB 2 –80 10 100 FREQUENCY (Hz) –40 1k GAIN (dB) –10 04443-0-005 PHASE (Degrees) For active and reactive energy measurements, the output of the ADC passes directly to the multipliers and is not filtered. This solution avoids the much larger multibit multiplier and does not affect the accuracy of the measurement. A HPF is not implemented on the voltage channel to remove the dc offset because the HPF on the current channel alone should be sufficient to eliminate error due to ADC offsets in the power calculation. However, ADC offset in the voltage channels produces large errors in the voltage rms calculation and affects the accuracy of the apparent energy calculation. Figure 50. Magnitude and Phase Response of LPF1 Note that LPF1 does not affect the active and reactive energy calculation because it is used only in the waveform sampling signal path. However, waveform samples are used for the voltage rms calculation and the subsequent apparent energy accumulation. WAVSEL[2:0] bits in the WAVMODE register should be set to 001 (binary) to start voltage waveform sampling. PHSEL[1:0] bits control the phase from which the samples are routed. When in waveform sampling mode, one of four output sample rates can be chosen by changing Bit 5 and Bit 6 of the WAVMODE register (see Table 16). The available output sample rates are 26.0 kSPS, 13.5 kSPS, 6.5 kSPS, or 3.3 kSPS. By setting the WSMP bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. Figure 40 shows the timing. The 24-bit waveform samples are transferred from the ADE7758 one byte (8 bits) at a time, with the most significant byte shifted out first. The sign of the register is extended in the upper 8 bits. The timing is the same as that for the current channels (see Figure 40). Rev. A | Page 23 of 68 ADE7758 crossing timeout register (ZXTOUT[15:0], Address 0x1B), every time a zero crossing is detected on its associated input. The default value of ZXTOUT is 0xFFFF. If the internal register decrements to 0 before a zero crossing at the corresponding input is detected, it indicates an absence of a zero crossing in the time determined by the ZXTOUT[15:0]. The ZXTOx detection bit of the corresponding phase in the interrupt status register is then switched on (Bit 9 to Bit 11). An active low on the IRQ output also appears if the ZXTOx mask bit for the corresponding phase in the interrupt mask register is set to Logic 1. Figure 52 shows the mechanism of the zero-crossing timeout detection when the line voltage A stays at a fixed dc level for more than CLKIN/384 × ZXTOUT[15:0] seconds. ZERO-CROSSING DETECTION The ADE7758 has zero-crossing detection circuits for each of the voltage channels (VAN, VBN, or VCN). Figure 51 shows how the zero-cross signal is generated from the output of the ADC of the voltage channel. REFERENCE GAIN[6:5] ×1, ×2, ×4 VAN, VBN, VCN PGA ZEROCROSSING DETECTOR ADC LPF1 f–3dB = 260Hz 24.8° @ 60Hz 1.0 0.908 ANALOG VOLTAGE WAVEFORM (VAN, VBN, OR VCN) LPF1 OUTPUT 16-BIT INTERNAL REGISTER VALUE ZXTOUT[15:0] 04443-0-031 IRQ VOLTAGE CHANNEL A READ RSTATUS Figure 51. Zero-Crossing Detection on Voltage Channels When one phase crosses from negative to positive, the corresponding flag in the interrupt status register (Bit 9 to Bit 11) is set to Logic 1. An active low in the IRQ output also appears if the corresponding ZX bit in the interrupt mask register is set to Logic 1. Note that only zero crossing from negative to positive will generate an interrupt. The flag in the interrupt status register is reset to 0 when the interrupt status register with reset (RSTATUS) is read. Each phase has its own interrupt flag and mask bit in the interrupt register. Zero-Crossing Timeout Each zero-crossing detection has an associated internal timeout register (not accessible to the user). This unsigned, 16-bit register is decreased by 1 every 384/CLKIN seconds. The registers are reset to a common user programmed value, i.e., the zero- READ RSTATUS 04443-0-032 ZXTOA DETECTION BIT The zero-crossing interrupt is generated from the output of LPF1. LPF1 has a single pole at 260 Hz (CLKIN = 10 MHz). As a result, there is a phase lag between the analog input signal of the voltage channel and the output of LPF1. The phase response of this filter is shown in the Voltage Channel Sampling section. The phase lag response of LPF1 results in a time delay of approximately 1.1 ms (@ 60 Hz) between the zero-crossing signal on the voltage inputs of the zero-crossing signal. Note that the zero-crossing signal is used for the line cycle accumulation mode, zero-crossing interrupt, and line period/frequency measurement. Figure 52. Zero-Crossing Timeout Detection PHASE COMPENSATION When the HPF in the current channel is disabled, the phase error between the current channel (IA, IB, or IC) and the corresponding voltage channel (VA, VB, or VC) is negligible. When the HPF is enabled, the current channels have phase response (see Figure 53 and Figure 54). Figure 55 is the magnitude response of the filter. The phase response is almost 0 from 45 Hz to 1 kHz. The frequency band is sufficient for the requirements of typical energy measurement applications. However, despite being internally phase compensated, the ADE7758 must work with transducers that may have inherent phase errors. For example, a current transformer (CT) with a phase error of 0.1° to 0.3° is not uncommon. These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7758 provides a means of digitally calibrating these small phase errors. The ADE7758 allows a small time delay or time advance to be introduced into the signal processing chain in order to compensate for the small phase errors. Rev. A | Page 24 of 68 ADE7758 0.20 The phase calibration registers (APHCAL, BPHCAL, and CPHCAL) are twos complement, 7-bit signed registers that can vary the time advance/delay in the voltage channel signal path from –151.2 µs to +75.6 µs (CLKIN = 10 MHz). One LSB is equivalent to 1.2 µs of time delay or 2.4 µs of time advance. With a line frequency of 50 Hz, this gives a phase resolution of 0.026° at the fundamental, i.e., 360° × 1.2 µs × 60 Hz, in the positive direction and 0.052° in the negative direction. This corresponds to a total correction range of −2.72° to +1.36° at 50 Hz. PHASE (Degrees) 0.15 0.05 0 –0.10 40 04443-0-096 –0.05 Figure 56 illustrates how the phase compensation is used to remove a 0.1° phase lead in IA of the current channel from the external current transducer. In order to cancel the lead (0.1°) in the current channel of Phase A, a phase lead must be introduced into the corresponding voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead of 0.104°. The phase lead is achieved by introducing a time advance into VA. A time advance of −4.8 µs is made by writing −4 (0x3C) to the time delay block (APHCAL[7:0]), thus reducing the amount of time delay by 4.8 µs or equivalently, 360° × 4.8 µs × 60 Hz = 0.104° at 60 Hz. 45 50 55 60 FREQUENCY (Hz) 65 70 Figure 54. Phase Response of the HPF and Phase Compensation (40 Hz to 70 Hz) 0.10 PHASE (Degrees) 0.08 90 80 70 60 0.06 0.04 0.02 0 50 40 04443-0-097 PHASE (Degrees) 0.10 –0.02 30 44 46 48 50 52 FREQUENCY (Hz) 54 20 Figure 55. Gain Response of HPF and Phase Compensation (44 Hz to 56 Hz) 04443-0-095 10 0 0 100 200 300 400 500 600 FREQUENCY (Hz) 700 800 900 1k Figure 53. Phase Response of the HPF and Phase Compensation (10 Hz to 1 kHz) IAP HPF PGA1 IA ADC IAN ACTIVE AND REACTIVE ENERGY CALCULATION RANGE OF PHASE CALIBRATION VAP PGA2 VA DIGITAL INTEGRATOR ADC +1.36°, –2.72° @ 50Hz; 0.022°, 0.043° +1.63°, –3.28° @ 60Hz; 0.026°, 0.052° VN 6 0 1 1 1 1 1 0 0 V1 0.1° APHCAL[6:0] –151.2µs TO +75.6µs VA VA DELAYED BY 4.8µs IA (–0.104° @ 60Hz) 0x7C 60Hz 60Hz Figure 56. Phase Calibration on Voltage Channels Rev. A | Page 25 of 68 04443-A-029 V2 56 ADE7758 PERIOD MEASUREMENT The ADE7758 provides the period or frequency measurement of the line voltage. The period is measured on the phase specified by Bit 0 to Bit 1 of the MMODE register. The period register is an unsigned 12-bit FREQ register and is updated every 4 periods of the selected phase. Bit 7 of the LCYCMODE selects whether the period register displays the frequency or the period. Setting this bit to logic high causes the register to display the period. The default setting is logic low, which causes the register to display the frequency. When set to measure the period, the resolution of this register is 96/CLKIN per LSB (9.6 µs/LSB when CLKIN is 10 MHz), which represents 0.06% when the line frequency is 60 Hz. At 60 Hz, the value of the period register is 1737d. At 50 Hz, the value of the period register is 2084d. When set to measure frequency, the value of the period register is approximately 960d at 60 Hz and 800d at 50 Hz. This is equivalent to 0.0625 Hz/LSB. LINE VOLTAGE SAG DETECTION section). The phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers. SAG LEVEL SET The contents of the single-byte SAG level register, SAGLVL[0:7], are compared to the absolute value of Bit 6 to Bit 13 from the voltage waveform samples. For example, the nominal maximum code of the voltage channel waveform samples with a full-scale signal input at 60 Hz is 0x249C (see the Voltage Channel Sampling section). Bit 13 to Bit 6 are 0x92. Therefore, writing 0x92 to the SAG level register puts the SAG detection level at full scale and sets the SAG detection to its most sensitive value. The detection is made when the content of the SAGLVL[7:0] register is greater than the incoming sample. Writing 0x00 puts the SAG detection level at 0. The detection of a decrease of an input voltage is in this case disabled. PEAK VOLTAGE DETECTION The ADE7758 can record the peak of the voltage waveform and produce an interrupt if the current exceeds a preset limit. Peak Voltage Detection Using the VPEAK Register The ADE7758 can be programmed to detect when the absolute value of the line voltage of any phase drops below a certain peak value, for a number of half cycles. Each phase of the voltage channel is controlled simultaneously. This condition is illustrated in Figure 57. The peak absolute value of the voltage waveform within a fixed number of half-line cycles is stored in the VPEAK register. Figure 58 illustrates the timing behavior of the peak voltage detection. L2 VAP, VBP, OR VCP L1 FULL-SCALE SAGLVL[7:0] NO. OF HALF LINE CYCLES SPECIFIED BY LINECYC[15:0] REGISTER SAGCYC[7:0] = 0x06 6 HALF CYCLES READ RSTATUS REGISTER CONTENT OF VPEAK[7:0] 04443-A-033 SAG INTERRUPT FLAG (BIT 3 TO BIT 5 OF STATUS REGISTER) SAG EVENT RESET LOW WHEN VOLTAGE CHANNEL EXCEEDS SAGLVL[7:0] Figure 57. ADE7758 SAG Detection Figure 57 shows a line voltage fall below a threshold which is set in the SAG level register (SAGLVL[7:0]) for nine half cycles. Since the SAG cycle register indicates a six half-cycle threshold (SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corresponding phase in the interrupt status register (Bit 1 to Bit 3 in the interrupt status register). If the SAG enable bit is set to Logic 1 for this phase (Bit 1 to Bit 3 in the interrupt mask register), the IRQ logic output goes active low (see the ADE7758 Interrupts 00 L1 L2 L1 04443-0-034 VOLTAGE WAVEFORM (PHASE SELECTED BY PEAKSEL[2:4] IN MMODE REGISTER) Figure 58. Peak Voltage Detection Using the VPEAK Register Note that the content of the VPEAK register is equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform sample. At full-scale analog input, the voltage waveform sample at 60 Hz is 0x249C. The VPEAK at full-scale input is, therefore, expected to be 0x92. In addition, multiple phases can be activated for the peak detection simultaneously by setting multiple bits to logic high among the PEAKSEL[2:4] bits in the MMODE register. These bits select the phase for both voltage and current peak measurements. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, i.e., the voltage and current peak are independently processed (see the Peak Current Detection section). Rev. A | Page 26 of 68 ADE7758 Note that the number of half-line cycles is based on counting the zero crossing of the voltage channel. The ZXSEL[2:0] bits in the LCYCMODE register determine which voltage channels are used for the zero-crossing detection. The same signal is also used for line cycle energy accumulation mode if activated (see the Line Cycle Accumulation Mode Register (0x17) section). voltage input should be wired to the VCP pin and the phase C voltage input should be wired to the VBP pin. B = –120°C A = 0°C C = 120°C Overvoltage Detection Interrupt Figure 59 illustrates the behavior of the overvoltage detection. VOLTAGE WAVEFORMS VOLTAGE PEAK WAVEFORM BEING MONITORED (SELECTED BY PKIRQSEL[5:7] IN MMODE REGISTER) ZERO CROSSINGS VPINTLVL[7:0] A B C A B C A B C C B A C B A C SEQERR BIT OF STATUS REGISTER IS NOT SET B SEQERR BIT OF STATUS REGISTER IS SET C = –120°C A = 0°C B = 120°C VOLTAGE WAVEFORMS READ RSTATUS REGISTER ZERO CROSSINGS 04443-A-051 PKV INTERRUPT FLAG (BIT 14 OF STATUS REGISTER) 04443-0-035 PKV RESET LOW WHEN RSTATUS REGISTER IS READ A Figure 60. Phase Sequence Detection Figure 59. ADE7758 Overvoltage Detection Note that the content of the VPINTLVL[7:0] register is equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform samples; therefore, setting this register to 0x92 represents putting the peak detection at full-scale analog input. Figure 59 shows a voltage exceeding a threshold. By setting the PKV flag (Bit 14) in the interrupt status register, the overvoltage event is recorded. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low (see the ADE7758 Interrupts section). Multiple phases can be activated for peak detection. If any of the active phase produces waveform samples above the threshold, the PKV flag in the interrupt status register is set. The phase in which overvoltage is monitored is set by the PKIRQSEL[5:7] bits in the MMODE register (see Table 15). POWER-SUPPLY MONITOR The ADE7758 also contains an on-chip power-supply monitor. The analog supply (AVDD) is monitored continuously by the ADE7758. If the supply is less than 4 V ± 5%, the ADE7758 goes into an inactive state, that is, no energy is accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down. The power-supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. Figure 61 shows the behavior of the ADE7758 when the voltage of AVDD falls below the power-supply monitor threshold. The power supply and decoupling for the part should be designed such that the ripple at AVDD does not exceed 5 V ± 5% as specified for normal operation. AVDD PHASE SEQUENCE DETECTION 5V 4V 0V TIME ADE7758 INTERNAL CALCULATIONS Rev. A | Page 27 of 68 INACTIVE ACTIVE INACTIVE Figure 61. On-Chip Power-Supply Monitoring 04443-0-036 The ADE7758 has on-chip phase sequence error detection interrupt. If the zero crossing of Phase A is not followed by Phase C but by Phase B, the SEQERR bit (Bit 19) in the STATUS register is set. If SEQERR, Bit 19, is set in the mask register, the IRQ logic output goes active low (see the ADE7758 Interrupts section). The following figure depicts how the interrupt is issued in two different configurations. Note that if it is desired to have the interrupt occur when Phase A is followed by Phase B and not Phase C, then the analog inputs for Phase B and phase C should be swapped. In this case, the Phase B ADE7758 REFERENCE CIRCUIT The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs in the ADE7758. However, the current channels have three input range selections (full scale is selectable among 0.5 V, 0.25 V, and 0.125 V). This is achieved by dividing the reference internally by 1, ½, and ¼. The reference value is used for the ADC in the current channels. Note that the full-scale selection is only available for the current inputs. The REFIN/OUT pin can be overdriven by an external source, for example, an external 2.5 V reference. Note that the nominal reference value supplied to the ADCs is now 2.5 V and not 2.42 V. This has the effect of increasing the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V. The voltage of the ADE7758 reference drifts slightly with temperature—see the Specifications section for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Because the reference is used for all ADCs, any x% drift in the reference results in a 2x% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and typically much smaller than the drift of other components on a meter. Alternatively, the meter can be calibrated at multiple temperatures. The ADE7758 temperature register varies with power supply. It is recommended to use the temperature register only in applications with a fixed, stable power supply. Typical error with respect to power supply variation is show in Table 5. Table 5. Temperature Register Error with Power Supply Variation Depending on the nominal value of the register, some finite temperature may cause the register to roll over. This should be compensated in the MCU. 5V 214 0 5.25 V 211 −1.40 5.5 V 208 −2.80 Root mean square (rms) is a fundamental measurement of the magnitude of an ac signal. Its definition can be both practical and mathematical. Defined practically, the rms value assigned to an ac signal is the amount of dc required to produce an equivalent amount of power in the load. Mathematically the rms value of a continuous signal f(t) is defined as FRMS = 1 T ∫0 T f 2 (t )dt (1) For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. FRMS = Temperature Register = Temperature (°C) − 70 4.75 V 216 0.93 ROOT MEAN SQUARE MEASUREMENT TEMPERATURE MEASUREMENT The ADE7758 also includes an on-chip temperature sensor. A temperature measurement is made every 4/CLKIN seconds. The output from the temperature sensing circuit is connected to an ADC for digitizing. The resultant code is processed and placed in the temperature register (TEMP[7:0]). This register can be read by the user and has an address of 0x11 (see the ADE7758 Serial Interface section). The contents of the temperature register are signed (twos complement) with a resolution of 3°C/LSB. The offset of this register may vary from part to part significantly. To calibrate this register, the nominal value should be measured, and the equation should be adjusted accordingly. For example, if the temperature register produces a code of 0x00 when the ambient temperature is approximately 70°C, the value of the register is 4.5 V 219 2.34 Register Value % Error 1 N N ∑ f 2 [n] (2) n=1 The method used to calculate the rms value in the ADE7758 is to low-pass filter the square of the input signal (LPF3) and take the square root of the result (see Figure 62). With i(t) = 2 × IRMS × sin( ω t) then i2(t) = IRMS2 − IRMS2× cos (ω t) The rms calculation is simultaneously processed on the six analog input channels. Each result is available in separate registers. While the ADE7758 measures nonsinusoidal signals, it should be noted that the voltage rms measurement, and therefore the apparent energy, are band-limited to 160 Hz. The current rms, as well as the active power, have a bandwidth of 14 kHz. Current RMS Calculation Figure 62 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel. The current channel rms value is processed from the samples used in the current channel waveform sampling mode. The current rms values are stored in unsigned 24-bit registers (AIRMS, BIRMS, and CIRMS). One LSB of the current rms register is Rev. A | Page 28 of 68 ADE7758 equivalent to one LSB of the current waveform sample. The update rate of the current rms measurement is CLKIN/12. and CVRMS). The 256 LSBs of the voltage rms register is approximately equivalent to one LSB of a voltage waveform sample. The update rate of the voltage rms measurement is CLKIN/12. AIRMSOS[11:0] 217 216 215 0x1D3781 0x0 0x00 0xD7AE14 LPF3 X2 + + AIRMS[24:0] 04443-A-016 CURRENT SIGNAL FROM HPF OR INTEGRATOR (IF ENABLED) Figure 62. Current RMS Signal Processing With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d (see the Current Channel ADC section). The equivalent rms values of a full-scale sinusoidal signal at 60 Hz is 1,914,753 (0x1D3781). The accuracy of the current rms is typically 0.2% error from the full-scale input down to 1/500 of the full-scale input. Additionally, this measurement has a bandwidth of 14 kHz. With the specified full-scale ac analog input signal of 0.5 V, the LPF1 produces an output code that is approximately 63% of its full-scale value , i.e., ±9,372d, at 60 Hz (see the Voltage Channel ADC section). The equivalent rms value of a full-scale ac signal is approximately 1,639,101 (0x1902BD) in the VRMS register. The accuracy of the VRMS measurement is typically 0.5% error from the full-scale input down to 1/20 of the full-scale input. Additionally, this measurement has a bandwidth of 160 Hz. VRMSOS[11:0] SGN 216 215 214 AVRMSGAIN[11:0] LPF1 where IRMS0 is the rms measurement without offset correction. Voltage Channel RMS Calculation Figure 63 shows the details of the signal path for the rms calculation on Phase A of the voltage channel. The voltage channel rms value is processed from the waveform samples after the low-pass filter LPF1. The output of the voltage channel ADC can be scaled by ±50% by changing VRMSGAIN[11:0] registers to perform an overall rms voltage calibration. The VRMSGAIN registers scale the rms calculations as well as the apparent energy calculation, since apparent power is the product of the voltage and current rms values. The voltage rms values are stored in unsigned 24-bit registers (AVRMS, BVRMS, 26 AVRMS[23:0] LPF3 50Hz VOLTAGE SIGNAL–V(t) 0.5 GAIN 50Hz LPF OUTPUT WORD RANGE 0x193504 0x25A2 60Hz 0x0 IRMS = IRMS0 2 + 16,384 × IRMSOS 27 + + X2 VAN Current RMS Offset Compensation The ADE7758 incorporates a current rms offset compensation for each phase (AIRMSOS, BIRMSOS, and CIRMSOS). These are 12-bit signed registers that can be used to remove offsets in the current rms calculations. An offset may exist in the rms calculation due to input noises that are integrated in the dc component of I2(t). The offset calibration allows the contents of the IRMS registers to be maintained at 0 when no current is being consumed. One LSB of the current rms offset register is equivalent to 16,384 (decimal) of the square of the current rms register. Assuming that the maximum value from the current rms calculation is 1,868,467d with full-scale ac inputs, one LSB of the current rms offset represents 0.94% of the measurement error at −60 dB down of full scale. For details on how to calibrate the current rms measurement, see the Calibration section. 28 0xDA5E 0x0 0x1902BD 60Hz LPF OUTPUT WORD RANGE 0x0 0x249C 0x0 0xDB64 04443-A-030 SGN 225 224 223 0x2851EC Figure 63. Voltage RMS Signal Processing Voltage RMS Offset Compensation The ADE7758 incorporates a voltage rms offset compensation for each phase (AVRMSOS, BVRMSOS, and CVRMSOS). These are 12-bit signed registers that can be used to remove offsets in the voltage rms calculations. An offset may exist in the rms calculation due to input noises and offsets in the input samples. It should be noted that the offset calibration does not allow the contents of the VRMS registers to be maintained at 0 when no voltage is applied. This is caused by noise in the voltage rms calculation, which limits the usable range between full scale and 1/50th of full scale. One LSB of the voltage rms offset is equivalent to 64 LSBs of the voltage rms register. Assuming that the maximum value from the voltage rms calculation is 1,639,101d with full-scale ac inputs, then 1 LSB of the voltage rms offset represents 0.042% of the measurement error at 1/10 of full scale. VRMS = VRMS0 + VRMSOS × 64 where VRMS0 is the rms measurement without the offset correction. Rev. A | Page 29 of 68 ADE7758 Voltage RMS Gain Adjust The ADC gain in each phase of the voltage channel can be adjusted for the rms calculation by using the voltage rms gain registers (AVRMSGAIN, BVRMSGAIN, and CVRMSGAIN). The gain of the voltage waveforms before LPF1 is adjusted by writing twos complement, 12-bit words to the voltage rms gain registers. The expression below shows how the gain adjustment is related to the contents of the voltage gain register. filter) to obtain the average active power information on each phase. Figure 64 shows this process. The active power of each phase accumulates in the corresponding 16-bit watt-hour register (AWATTHR, BWATTHR, or CWATTHR). The input to each active energy register can be changed depending on the accumulation mode setting (see Table 17). INSTANTANEOUS POWER SIGNAL p(t) = VRMS × IRMS – VRMS × IRMS × cos(2ωt) 0x19999A ACTIVE REAL POWER SIGNAL = VRMS × IRMS Content of VRMS Register = VRMSGAIN ⎞ ⎛ Nominal RMS Values without Gain × ⎜1 + ⎟ 212 ⎝ ⎠ VRMS × IRMS 0xCCCCD For example, when 0x7FF is written to the voltage gain register, the ADC output is scaled up by 50%. 0x00000 0x7FF = 2047d, 2047/212 = 0.5 VOLTAGE v(t) = 2 × VRMS × sin(ωt) ACTIVE POWER CALCULATION Electrical power is defined as the rate of energy flow from source to load. It is given by the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. Equation 5 gives an expression for the instantaneous power signal in an ac system. Figure 64. Active Power Calculation Because LPF2 does not have an ideal “brick wall” frequency response (Figure 65), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated over time to calculate the energy. v (t ) = 2 × VRMS × sin (ω t ) (3) 0 i(t ) = 2 × IRMS × sin (ω t ) (4) –4 –8 dB p(t ) = v (t ) × i (t ) (5) The average power over an integral number of line cycles (n) is given by the expression in Equation 6. 1 nT p= p (t )dt = VRMS × IRMS nT ∫0 –12 –16 –20 04443-0-038 where VRMS = rms voltage, IRMS = rms current. p (t) = IRMS × VRMS – IRMS × VRMS × cos (2 ω t) 04443-A-037 CURRENT i(t) = 2 × IRMS × sin(ωt) Similarly, 0x800 = –2047d (signed twos complement) and the ADC output is scaled by –50%. –24 (6) 1 3 8 10 30 FREQUENCY (Hz) Figure 65. Frequency Response of the LPF Used to Filter Instantaneous Power in Each Phase where t is the line cycle period. P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 5, that is, VRMS × IRMS. This is the relationship used to calculate the active power in the ADE7758 for each phase. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals in each phase. The dc component of the instantaneous power signal in each phase (A, B, and C) is then extracted by LPF2 (the low-pass Rev. A | Page 30 of 68 100 ADE7758 Active Power Gain Calibration Sign of Active Power Calculation Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s watt gain register (AWG, BWG, or CWG). The watt gain registers are twos complement, signed registers and have a resolution of 0.024%/LSB. The following equation describes mathematically the function of the watt gain registers. Note that the average active power is a signed calculation. If the phase difference between the current and voltage waveform are more than 90°, the average power becomes negative. Negative power indicates that energy is being placed back on the grid. The ADE7758 has a sign detection circuitry for active power calculation. The REVPAP bit (Bit 17) in the interrupt status register is set if the average power from any one of the phases changes sign. The phases monitored are selected by TERMSEL bits in the COMPMODE register (see Table 17). The TERMSEL bits are also used to select which phases are included in the APCF and VARCF pulse outputs. If the REVPAP bit is set in the mask register, the IRQ logic output goes active low (see the ADE7758 Interrupts section). Note that this bit is set whenever there are sign changes, i.e., the REVPAP bit is set for both a positive-to-negative change or a negative-to-positive change of the sign bit. The APCFNUM [15:13] indicate reverse power on each of the individual phases. Bit 15 will be set if the sign of the power on Phase A is negative, Bit 14 for Phase B, and Bit 13 for Phase C. Average Power Data = LPF2 Output × Watt Gain Register ⎞ ⎛ ⎟ ⎜1 + 212 ⎠ ⎝ The output is scaled by −50% when the watt gain registers contents are set to 0x800 and the output is increased by +50% by writing 0x7FF to the watt gain register. This register can be used to calibrate the active power (or energy) calculation in the ADE7758 for each phase. Active Power Offset Calibration The ADE7758 also incorporates a watt offset register on each phase (AWATTOS, BWATTOS, and CWATTOS). These are signed twos complement, 12-bit registers that are used to remove offsets in the active power calculations. An offset may exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. One LSB in the active power offset register is equivalent to 1/16 LSB in the active power multiplier output. At full-scale input, if the output from the multiplier is 0xCCCCD (838,861d), then 1 LSB in the LPF2 output is equivalent to 0.0075% of measurement error at −60 dB down of full scale at current channel. At −60 dB down on full scale (the input signal level is 1/1000 of full-scale signal inputs), the average word value from LPF2 is 838.861 (838,861/1,000). One LSB is equivalent to 1/838.861/16 × 100% = 0.0075% of the measured value. The active power offset register has a correction resolution equal to 0.0075% at −60 dB. No-Load Threshold The ADE7758 has an internal no-load threshold on each phase. The no-load threshold can be activated by setting the NOLOAD bit (Bit 7) of the COMPMODE register. If the active power falls below 0.005% of full-scale input, the energy is not accumulated in that phase. As stated, the average multiplier output with fullscale input is 0xCCCCD. Therefore, if the average multiplier output falls below 0x2A, the power is not accumulated to avoid creep in the meter. The no-load threshold is implemented only on the active energy accumulation. The reactive and apparent energies do not have the no-load threshold option. Active Energy Calculation As stated earlier, power is defined as the rate of energy flow. This relationship can be expressed mathematically as Equation 7. Power = dEnergy dt (7) Conversely, Energy is given as the integral of power. Energy = ∫ p (t )dt Rev. A | Page 31 of 68 (8) ADE7758 WATTOS[11:0] WATTHR[15:0] HPF DIGITAL INTEGRATOR I SIGN 26 MULTIPLIER 20 15 2–1 2–2 2–3 2–4 0 AWG[11:0] LPF2 + + CURRENT SIGNAL–i(t) 40 + % 0x2851EC 0 + 0x00 WDIV[7:0] AVERAGE POWER SIGNAL–P 0xD7AE14 V T TOTAL ACTIVE POWER IS ACCUMULATED (INTEGRATED) IN THE ACTIVE ENERGY REGISTER VOLTAGE SIGNAL–v(t) 0x2852 0xCCCCD 04443-A-039 000x 0xD7AE 0x00000 TIME (nT) Figure 66. ADE7758 Active Energy Accumulation ⎫ ⎧∞ Energy = ∫ p (t )dt = Lim ⎨ ∑ p (nT ) × T ⎬ T →0 ⎩n = 0 ⎭ (9) where n is the discrete time sample number and T is the sample period. Figure 66 shows a signal path of this energy accumulation. The average active power signal is continuously added to the internal active energy register. This addition is a signed operation. Negative energy is subtracted from the active energy register. Note the values shown in Figure 65 are the nominal full-scale values, i.e., the voltage and current inputs at the corresponding phase are at their full-scale input level. The average active power is divided by the content of the watt divider register before it is added to the corresponding watt-hr accumulation registers. When the value in the WDIV[7:0] register is 0 or 1, active power is accumulated without division. WDIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the watt-hr accumulation registers overflow. to the WDIV register and therefore can be increased by a maximum factor of 255. Note that the active energy register content can roll over to fullscale negative (0x8000) and continue increasing in value when the active power is positive (see Figure 66). Conversely, if the active power is negative, the energy register would under flow to full-scale positive (0x7FFF) and continue decreasing in value. By setting the AEHF bit (Bit 0) of the interrupt mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when Bit 14 of any one of the three watt-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative). Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the watt-hr accumulation registers, i.e., the registers are reset to 0 after a read operation. WATT GAIN = 0x7FF CONTENTS OF WATTHR ACCUMULATION REGISTER Figure 67 shows the energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves show the minimum time it takes for the watt-hr accumulation register to overflow when the watt gain register of the corresponding phase equals to 0x7FF, 0x000, and 0x800. The watt gain registers are used to carry out a power calibration in the ADE7758. As shown, the fastest integration time occurs when the watt gain registers are set to maximum full scale, i.e., 0x7FF. This is the time it takes before overflow can be scaled by writing Rev. A | Page 32 of 68 WATT GAIN = 0000 WATT GAIN = 0800 0x7FFF 0x3FFF 0x0000 0.13 0.52 0.79 1.05 1.31 1.58 0xC000 0x8000 TIME (Sec) Figure 67. Energy Register Roll-Over Time for Full-Scale Power (Minimum and Maximum Power Gain) 04443-A-040 The ADE7758 achieves the integration of the active power signal by continuously accumulating the active power signal in the internal 41-bit energy registers. The watt-hr registers (AWATTHR, BWATTHR, and CWATTHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 9 expresses the relationship ADE7758 The discrete time sample period (T) for the accumulation register is 0.4 µs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD (see Figure 64 and Figure 66). The maximum value which can be stored in the watt-hr accumulation register before it overflows is 215 − 1 or 0x7FFF. Because the average word value is added to the internal register, which can store 240 − 1 or 0xFF, FFFF, FFFF before it overflows, the integration time under these conditions with WDIV = 0 is calculated as Time = 0xFF, FFFF, FFFF × 0.4 μs = 0.524 second 0xCCCCD When WDIV is set to a value different from 0, the time before overflow is scaled accordingly as shown in Equation 10. Time = Time (WDIV = 0 ) × WDIV [7 : 0 ] (10) Energy Accumulation Mode Different gain calibration parameters are offered in the ADE7758 to cover the calibration of the meter in different configurations. It should be noted that in CONSEL Mode 0d the IGAIN and WGAIN registers have the same effect on the end result. However, changing IGAIN also changes all other calculations that use the current waveform. In other words, changing IGAIN changes the active, reactive, and apparent energy, as well as the RMS current calculation results. Active Power Frequency Output Pin 1 (APCF) of the ADE7758 provides frequency output for the total active power. After initial calibration during manufacturing, the manufacturer or end customer will often verifies the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency that is proportional to the energy or active power under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 68 illustrates the energyto-frequency conversion in the ADE7758. The active power accumulated in each watt-hr accumulation register (AWATTHR, BWATTHR, or CWATTHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 6. INPUT TO BWATTHR REGISTER INPUT TO CWATTHR REGISTER Table 6. Inputs to Watt-Hr Accumulation Registers CONSEL[1, 0] 00 01 10 11 AWATTHR VA × IA VA × (IA – IB) VA × (IA – IB) Reserved BWATTHR VB × IB 0 0 Reserved CWATTHR VC × IC VC × (IC – IB) VC × IC Reserved Note that the contents of the watt-hr accumulation registers are affected by both the current gain register (IGAIN) and the watt gain register of the corresponding phase. IGAIN should not be used when using Mode 0 of CONSEL, COMPMODE[0:1]. Depending on the poly phase meter service, the appropriate formula should be chosen to calculate the active energy. The American ANSI C12.10 standard defines the different configurations of the meter. Table 7 describes which mode should be chosen in these different configurations. Table 7. Meter Form Configuration ANSI Meter Form 5S/13S 3-Wire Delta 6S/14S 4-Wire Wye 8S/15S 4-Wire Delta 9S/16S 4-Wire Wye CONSEL (d) 0 1 2 0 TERMSEL (d) 3, 5, or 6 7 7 7 APCFNUM[11:0] INPUT TO AWATTHR REGISTER + + + DFC ÷ ÷4 APCFDEN[11:0] APCF 04443-0-041 Integration Time Under Steady Load Figure 68. ADE7758 Active Power Frequency Output A digital-to-frequency converter (DFC) is used to generate the APCF pulse output from the total active power. TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AWATTHR, BWATTHR, and CWATTHR registers in the total active power calculation. The total active power is signed addition. However, setting the ABS bit (Bit 5) in the COMPMODE register enables the absolute only mode, that is, only the absolute value of the active power is considered. The output from the DFC is divided down by a pair of frequency division registers before sending to the APCF pulse output. Namely, APCFDEN/APCFNUM pulses are needed at the DFC output before the APCF pin outputs a pulse. Under steady load conditions, the output frequency is directly proportional to the total active power. The pulse width of APCF is 64 × CLKIN if APCFNUM and APCFDEN are both equal. If APCFDEN is greater than APCFNUM, the pulse width depends on APCFDEN. The pulse width in this case is T × (APCFDEN/2), where T is the period of the APCF pulse and APCFDEN/2 is rounded to the nearest whole number. An exception to this is when the period is greater than 180 ms. In this case, the pulse width is fixed at 90 ms. Rev. A | Page 33 of 68 ADE7758 The maximum output frequency (APCFNUM = 0x00 and APCFDEN = 0x00) with full-scale ac signals on one phase is approximately 16 kHz. From Equation 12, ⎡ ⎢ VRMS × IRMS E (t ) = VRMS × IRMS × t – ⎢⎢ 2 ⎢ 4πf t 1 + (2 f1 ) 1 ⎢⎣ 82 The ADE7758 incorporates two registers to set the frequency of APCF (APCFNUM[11:0] and APCFDEN[11:0]). These are unsigned 12-bit registers that can be used to adjust the frequency of APCF by 1/212 to 1 with a step of 1/212. For example, if the output frequency is 1.562 kHz, while the contents of CFDIV are 0 (0x000), then the output frequency can be set to 6.103 Hz by writing 0xFF to the CFDEN register. ⎤ ⎥ ⎥ × cos(4 πf t ) 1 ⎥ ⎥ ⎥⎦ (13) From Equation 13, it can be seen that there is a small ripple in the energy calculation due to the sin(2ωt) component. Figure 69 shows this. The ripple gets larger with larger loads. Choosing a lower output frequency for APCF during calibration by using a large APCFDEN value and keeping APCFNUM relatively small can significantly reduce the ripple. Also, averaging the output frequency over a longer period of time achieves the same results. If 0 is written to any of the frequency division registers, the divider would use 1 in the frequency division. In addition, the ratio APCFNUM/ APCFDEN should be set not greater than one to ensure proper operation. In other words, the APCF output frequency cannot be higher than the frequency on the DFC output. E(t) Vlt The output frequency has a slight ripple at a frequency equal to twice the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal (see the Active Power Calculation section). Equation 5 gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 11. VI 4π×f1 1 + 2f1 2 × sin(4π × f1× t) 8 04443-0-042 – t Figure 69. Output Frequency Ripple H( f ) = 1 2 1+ f Line Cycle Active Energy Accumulation Mode (11) The ADE7758 is designed with a special energy accumulation mode that simplifies the calibration process. By using the onchip zero-crossing detection, the ADE7758 updates the watt-hr accumulation registers after an integer number of zero crossings (Figure 70). The line active energy accumulation mode for watthr accumulation is activated by setting the LWATT bit (Bit 0) of the LCYCMODE register. The total energy over an integer number of half-line cycles is written to the watt-hr accumulation registers after the LINECYC number of zero crossings have been detected. When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. 82 The active power signal (output of the LPF2) can be rewritten as p(t ) = VRMS × IRMS ⎡ ⎤ ⎢ ⎥ ⎢ VRMS × IRMS ⎥ × cos(4 πf t ) 1 ⎢ ⎥ 2 ⎢ 1 + (2 f1 ) ⎥ ⎢⎣ 82 ⎥⎦ (12) where f1 is the line frequency, for example, 60 Hz. WATTOS[11:0] WG[11:0] WDIV[7:0] 40 + ACTIVE POWER + % 0 + + ZXSEL0* 15 ZERO-CROSSING DETECTION (PHASE A) 0 WATTHR[15:0] ZXSEL1* ZERO-CROSSING DETECTION (PHASE B) ACCUMULATE ACTIVE POWER FOR LINECYC NUMBER OF ZERO-CROSSINGS; WATT-HR ACCUMULATION REGISTERS ARE UPDATED ONCE EVERY LINECYC NUMBER OF ZERO-CROSSINGS CALIBRATION CONTROL ZXSEL2* LINECYC[15:0] 04443-0-043 ZERO-CROSSING DETECTION (PHASE C) *ZXSEL[0:2] ARE BITS 3 TO 5 IN THE LCYCMODE REGISTER Figure 70. ADE7758 Line Cycle Active Energy Accumulation Mode Rev. A | Page 34 of 68 ADE7758 Phase A, Phase B, and Phase C zero crossings are, respectively, included when counting the number of half-line cycles by setting ZXSEL[0:2] bits (Bit 3 to Bit 5) in the LCYCMODE register. Any combination of the zero crossings from all three phases can be used for counting the zero crossing. Only one phase should be selected at a time for inclusion in the zero crossings count during calibration (see the Calibration section). where V = rms voltage, I = rms current, θ = total phase shift caused by the reactive elements in the load. Then the instantaneous reactive power q(t) can be expressed as The number of zero crossings is specified by the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7758 can accumulate active power for up to 65535 combined zero crossings. Note that the internal zero crossing counter is always active. By setting the LWATT bit, the first energy accumulation result is therefore incorrect. Writing to the LINECYC register when the LWATT bit is set resets the zero-crossing counter, thus ensuring that the first energy accumulation result is accurate. where i′(t ) is the current waveform phase shifted by 90°. Note that q(t) can be rewritten as At the end of an energy calibration cycle, the LENERGY bit (Bit 12) in the STATUS register is set. If the corresponding mask bit in the interrupt mask register is enabled, the IRQ output also goes active low; thus, the IRQ can also be used to signal the end of a calibration. Because active power is integrated on an integer number of half line cycles in this mode, the sinusoidal component is reduced to 0. This eliminates any ripple in the energy calculation. Therefore, total energy accumulated using the line-cycle accumulation mode is (14) where t is the accumulation time. Note that line cycle active energy accumulation uses the same signal path as the active energy accumulation. The LSB size of these two methods is equivalent. Using the line cycle accumulation to calculate the kWh/LSB constant results in a value that can be applied to the WATTHR registers when the line accumulation mode is not selected (see the Calibration section). π⎞ π⎞ ⎛ ⎛ q(t ) = VI cos⎜ – θ – ⎟ – VI cos⎜ 2ωt – θ – ⎟ 2⎠ 2⎠ ⎝ ⎝ q(t ) = VI sin(θ) + VI sin(2ωt – θ) The average reactive power over an integral number of line cycles (n) is given by the expression in Equation 18. Q= 1 nT nT ∫ q(t )dt = V × I × sin (θ) where T is the period of the line cycle. Q is referred to as the average reactive power. The instantaneous reactive power signal q(t) is generated by multiplying the voltage signals and the 90° phase-shifted current in each phase. The dc component of the instantaneous reactive power signal in each phase (A, B, and C) is then extracted by a low-pass filter to obtain the average reactive power information on each phase. This process is illustrated in Figure 71. The reactive power of each phase is accumulated in the corresponding 16-bit VARhour register (AVARHR, BVARHR, or CVARHR). The input to each reactive energy register can be changed depending on the accumulation mode setting (see Table 17). The frequency response of the LPF in the reactive power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 65). INSTANTANEOUS REACTIVE POWER SIGNAL q(t) = VRMS × IRMS × sin(φ) + VRMS × IRMS × sin(2ωt+θ) A load that contains a reactive element (inductor or capacitor) produces a phase difference between the applied ac voltage and the resulting current. The power associated with reactive elements is called reactive power and its unit is VAR. Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase shifted by 90°. Equation 17 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90°. AVERAGE REACTIVE POWER SIGNAL = VRMS × IRMS × sin(θ) VRMS × IRMS × sin(φ) 00000h θ VOLTAGE v(t) = 2 × VRMS × sin(ωt–θ) (15) i(t ) = 2 I sin(ωt ) π⎞ ⎛ i′(t ) = 2 I sin⎜ ωt + ⎟ 2⎠ ⎝ (18) 0 REACTIVE POWER CALCULATION v (t ) = 2 V sin(ωt – θ) (17) CURRENT i(t) = 2 × IRMS × sin(ωt) 04443-0-044 E (t ) = VRMS × IRMS × t q(t ) = v (t ) × i′(t ) Figure 71. Reactive Power Calculation (16) The low-pass filter is nonideal so the reactive power signal has some ripple. This ripple is sinusoidal and has a frequency equal Rev. A | Page 35 of 68 ADE7758 to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated over time to calculate the reactive energy. The phase-shift filter has –90° phase shift when the integrator is enabled and +90° phase shift when the integrator is disabled. In addition, the filter has a nonunity magnitude response. Because the phase-shift filter has a large attenuation at high frequency, the reactive power is primarily for the calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation. Note that because of the magnitude characteristic of the phase shifting filter, the LSB weight of the reactive power calculation is slightly different from that of the active power calculation (see the Energy Registers Scaling section). phases changes. The phases monitored are selected by TERMSEL bits in the COMPMODE register (see Table 17). If the REVPRP bit is set in the mask register, the IRQ logic output goes active low (see the ADE7758 Interrupts section). Note that this bit is set whenever there is a sign change, i.e., the bit is set for both a positive-to-negative change or a negative-to-positive change of the sign bit. Table 8. Sign of Reactive Power Calculation Φ1 Between 0 to +90 Between −90 to 0 Between 0 to +90 Between −90 to 0 Integrator Off Off On On Sign of Reactive Power Positive Negative Positive Negative ____________________________________________________ Reactive Power Gain Calibration 1 The average reactive power from the LPF output in each phase can be scaled by ±50% by writing to the phase’s VAR gain register (AVARG, BVARG, or CVARG). The VAR gain registers are twos complement, signed registers, and have a resolution of 0.024%/LSB. The function of the VAR gain registers is expressed below. Φ is defined as the phase angle of the voltage signal minus the current signal, i.e., Φ is positive if the load is inductive and negative if the load is capacitive. Reactive Energy Calculation Reactive energy is defined as the integral of reactive power. Reactive Energy = ∫ q(t )dt Average Reactive Power = VAR Gain Register ⎞ ⎛ LPF2 Output × ⎜1 + ⎟ 212 ⎝ ⎠ The output is scaled by –50% when the VAR gain registers contents are set to 0x800 and the output is increased by +50% by writing 0x7FF to the VAR gain register. This register can be used to calibrate the reactive power (or energy) calculation in the ADE7758 for each phase. Similar to active power, the ADE7758 achieves the integration of the reactive power signal by continuously accumulating the reactive power signal in the internal 41-bit accumulation registers. The VAR-hr registers (AVARHR, BVARHR, and CVARHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 20 expresses the relationship ⎧∞ ⎫ Reactive Energy = ∫ q(t )dt = Lim ⎨ ∑ q(nT ) × T ⎬ T →0 ⎩n = 0 ⎭ Reactive Power Offset Calibration The ADE7758 incorporates a VAR offset register on each phase (AVAROS, BVAROS, and CVAROS). These are signed twos complement, 12-bit registers that are used to remove offsets in the reactive power calculations. An offset may exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no reactive power is being consumed. The offset registers’ resolution is the same as the active power offset registers (see the Apparent Power Offset Calibration section). Sign of Reactive Power Calculation Note that the average reactive power is a signed calculation. As stated previously, the phase shift filter has –90° phase shift when the integrator is enabled and +90° phase shift when the integrator is disabled. Table 8 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation. The ADE7758 has a sign detection circuit for the reactive power calculation. The REVPRP bit (Bit 18) in the interrupt status register is set if the average reactive power from any one of the (19) (20) where n is the discrete time sample number and T is the sample period. Figure 72 shows the signal path of the reactive energy accumulation. The average reactive power signal is continuously added to the internal reactive energy register. This addition is a signed operation. Negative energy is subtracted from the reactive energy register. The average reactive power is divided by the content of the VAR divider register before they are added to the corresponding VAR-hr accumulation registers. When the value in the VARDIV[7:0] register is 0 or 1, the reactive power is accumulated without any division. VARDIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the VAR-hr accumulation registers overflow. Similar to reactive power, the fastest integration time occurs when the VAR gain registers are set to maximum full scale, i.e., 0x7FF. The time it takes before overflow can be scaled by writing to the VARDIV register and therefore it can be increased by a maximum factor of 255. Rev. A | Page 36 of 68 ADE7758 VAROS[11:0] HPF 90° PHASE SHIFTING FILTER VARHR[15:0] SIGN 26 20 π I 2 MULTIPLIER 0 VARG[11:0] LPF2 + CURRENT SIGNAL–i(t) 15 2–1 2–2 2–3 2–4 + % 40 + 0x2851EC 0 + 0x00 VARDIV[7:0] 0xD7AE14 V TOTAL REACTIVE POWER IS ACCUMULATED (INTEGRATED) IN THE VAR-HR ACCUMULATION REGISTERS VOLTAGE SIGNAL–v(t) 04443-A-045 0x2852 0x00 0xD7AE Figure 72. ADE7758 Reactive Energy Accumulation When overflow occurs, the VAR-hr accumulation registers content can rollover to full-scale negative (0x8000) and continue increasing in value when the reactive power is positive. Conversely, if the reactive power is negative the VAR-hr accumulation registers content can roll over to full-scale positive (0x7FFF) and continue decreasing in value. Energy Accumulation Mode By setting the REHF bit (Bit 1) of the mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when Bit 14 of any one of the three VAR-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative). Table 9. Inputs to VAR-Hr Accumulation Registers Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the VAR-hr accumulation registers, i.e., the registers are reset to 0 after a read operation. Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 µs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs, and a 90° phase difference between the voltage and the current signal (the largest possible reactive power), and the VAR gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD. The maximum value that can be stored in the reactive energy register before it overflows is 215 − 1 or 0x7FFF. As the average word value is first added to the internal register, which can store 240 − 1 or 0xFF, FFFF, FFFF before it overflows, the integration time under these conditions with VARDIV = 0 is calculated as Time = 0xFF, FFFF, FFFF × 0.4 μs = 0.5243 second 0xCCCCD When VARDIV is set to a value different from 0, the time before overflow are scaled accordingly as shown in Equation 21. Time = Time (VARDIV = 0 ) × VARDIV (21) The reactive power accumulated in each VAR-hr accumulation register (AVARHR, BVARHR, or CVARHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 9. CONSEL[1, 0] 00 01 10 11 AVARHR VA × IA’ VA(IA’ – IB’) VA(IA’ – IB’) Reserved BVARHR VB × IB 0 0 Reserved CVARHR VC × IC’ VC (IC’ – IB’) VC × IC’ Reserved Note that IA’/IB’/IC’ are the current phase shifted current waveform. The contents of the VAR-hr accumulation registers are affected by both the current gain register (IGAIN) and the VAR gain register of the corresponding phase. Reactive Power Frequency Output Pin 17 (VARCF) of the ADE7758 provides frequency output for the total reactive power. Similar to APCF, this pin provides an output frequency that is directly proportional to the total reactive power. The pulse width of VARPCF is 64 × CLKIN if VARCFNUM and VARCFDEN are both equal. If VARCFDEN is greater than VARCFNUM, the pulse width depends on VARCFDEN. The pulse width in this case is T × (VARCFDEN/2), where T is the period of the VARCF pulse and VARCFDEN/2 is rounded to the nearest whole number. An exception to this is when the period is greater than 180 ms. In this case, the pulse width is fixed at 90 ms. A digital-to-frequency converter (DFC) is used to generate the VARCF pulse output from the total reactive power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to be included in the total reactive power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVARHR, BVARHR, and CVARHR registers in the total active power calculation. The total reactive power is signed addition. However, setting the SAVAR bit (Bit 6) in the COMPMODE register enables absolute value calculation. Rev. A | Page 37 of 68 ADE7758 If the active power of that phase is positive, no change is made to the sign of the reactive power. However, if the sign of the active power is negative in that phase, the sign of its reactive power is inversed before summing and creating VARCF pulses. This mode should be used in conjunction with the absolute value mode for active power (Bit 5 in the COMPMODE register) for APCF pulses. Table 10 shows the effect of setting the ABS and SAVAR bits of the COMPMODE register. The effects of setting the ABS and SAVAR bits of the COMPMODE register results as follows when ABS = 1 and SAVAR = 1: If watt > 0 The line cycle reactive energy accumulation mode is activated by setting the LVAR bit (Bit 1) in the LCYCMODE register. The total reactive energy accumulated over an integer number of zero crossings is written to the VAR-hr accumulation registers after the LINECYC number of zero crossings has been detected. The operation of this mode is similar to watt-hr accumulation (see the Line Cycle Active Energy Accumulation Mode section). When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. APPARENT POWER CALCULATION APCF = Watts VARCF = VAR APCF = |Watts| VARCF = -VAR If watt < 0 Line Cycle Reactive Energy Accumulation Mode Apparent power is defined as the amplitude of the vector sum of the active and reactive powers. Figure 74 shows what is typically referred to as the power triangle. APPARENT POWER INPUT TO AVARHR REGISTER + VARCFNUM[11:0] 0 DFC INPUT TO BVAHR REGISTER INPUT TO CVAHR REGISTER ÷ ÷4 VARCF 1 INPUT TO AVAHR REGISTER + + + VARCFDEN[11:0] VACF BIT (BIT 7) OF WAVMODE REGISTER 04443-0-047 INPUT TO CVARHR REGISTER REACTIVE POWER + + 04443-0-046 INPUT TO BVARHR REGISTER θ Figure 73. ADE7758 Reactive Power Frequency Output The output from the DFC is divided down by a pair of frequency division registers before sending to the APCF pulse output. Namely, VARCFDEN/VARCFNUM pulses are needed at the DFC output before the VARCF pin outputs a pulse. Under steady load conditions, the output frequency is directly proportional to the total reactive power. Figure 68 illustrates the energy-to-frequency conversion in the ADE7758. Note that the input to the DFC can be selected between the total reactive power and total apparent power. Therefore, the VARCF pin can output frequency that is proportional to the total reactive power or total apparent power. The selection is made by setting the VACF bit (Bit 7) in the WAVMODE register. Setting this bit to logic high switches the input to the total apparent power. The default value of this bit is logic low. Therefore, the default output from the VARCF pin is the total reactive power. All other operations of this frequency output are similar to that of the active power frequency output (see the Active Power Frequency Output section). ACTIVE POWER Figure 74. Power Triangle There are two ways to calculate apparent power, namely the arithmetical approach or the vectorial method. The arithmetical method uses the product of the voltage rms value and current rms value to calculate apparent power. Equation 22 describes the arithmetical approach mathematically. S = VRMS × IRMS (22) where S is the apparent power, and VRMS and IRMS are the rms voltage and current, respectively. The vectorial method uses the square root of the sum of the active and reactive power, after the two are individually squared. Equation 23 shows the calculation used in the vectorial approach. S = P2 + Q2 (23) where S is the apparent power, P is the active power, and Q is the reactive power. Rev. A | Page 38 of 68 ADE7758 For a pure sinusoidal system, the two approaches should yield the same result. The apparent energy calculation in the ADE7758 uses the arithmetical approach. However, the line cycle energy accumulation mode in the ADE7758 enables energy accumulation between active and reactive energies over a synchronous period of time, thus the vectorial method can be easily implemented in the external MCU (see the Line Cycle Active Energy Accumulation Mode section). Note that apparent power is always positive regardless of the direction of the active or reactive energy flows. The rms value of the current and voltage in each phase is multiplied to produce the apparent power of the corresponding phase. The output from the multiplier is then low-pass filtered to obtain the average apparent power. The frequency response of the LPF in the apparent power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 65). Apparent Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s VAGAIN register (AVAG, BVAG, or CVAG). The VAGAIN registers are twos complement, signed registers and have a resolution of 0.024%/LSB. The function of the VAGAIN registers is expressed below mathematically. Average Apparent Power = VAGAIN Register ⎞ ⎛ LPF 2 Output × ⎜1 + ⎟ 212 ⎠ ⎝ The output is scaled by –50% when the VAR gain registers contents are set to 0x800 and the output is increased by +50% by writing 0x7FF to the watt gain register. This register can be used to calibrate the apparent power (or energy) calculation in the ADE7758 for each phase. Apparent Power Offset Calibration Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the Current RMS Calculation and Voltage Channel RMS Calculation sections). The voltage and current rms values are then multiplied together in the apparent power signal processing. As no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement in each phase should be done by calibrating each individual rms measurement (see the Calibration section). accumulating the apparent power signal in the internal 40-bit, unsigned accumulation registers. The VA-hr registers (AVAHR, BVAHR, and CVAHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 25 below expresses the relationship ⎧ ∞ ⎫ Apparent Energy = ∫ S(t ) dt = Lim ⎨ ∑ S (nT ) × T ⎬ (25) T →0 ⎩ n = 0 ⎭ where n is the discrete time sample number and T is the sample period. Figure 75 shows the signal path of the apparent energy accumulation. The apparent power signal is continuously added to the internal apparent energy register. The average apparent power is divided by the content of the VA divider register before they are added to the corresponding VA-hr accumulation registers. When the value in the VADIV[7:0] register is 0 or 1, apparent power is accumulated without any division. VADIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the VA-hr accumulation registers overflow. Similar to active or reactive power accumulation, the fastest integration time occurs when the VAGAIN registers are set to maximum full scale, i.e., 0x7FF. When overflow occurs, the VA-hr accumulation registers contents can roll over to 0 and continue increasing in value. By setting the VAEHF bit (Bit 2) of the mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when the MSB of any one of the three VA-hr accumulation registers has changed, indicating that the accumulation register is half full. Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the VA-hr accumulation registers, i.e., the registers are reset to 0 after a read operation. Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 µs (4/CLKIN). With full-scale, 60 Hz sinusoidal signals on the analog inputs and the VAGAIN registers set to 0x000, the average word value from each LPF2 is 0xB9954. The maximum value that can be stored in the apparent energy register before it overflows is 216 − 1 or 0xFFFF. As the average word value is first added to the internal register, which can store 241 − 1 or 0x1FF, FFFF, FFFF before it overflows, the integration time under these conditions with VADIV = 0 is calculated as Time = Apparent Energy Calculation Apparent energy is defined as the integral of apparent power. Apparent Energy = ∫ S(t) dt (24) 0x1FF, FFFF, FFFF × 0.4 μs = 1.157 second 0xB9954 When VADIV is set to a value different from 0, the time before overflow is scaled accordingly as shown in Equation 26. Similar to active and reactive energy, the ADE7758 achieves the integration of the apparent power signal by continuously Rev. A | Page 39 of 68 Time = Time(VADIV = 0 ) × VADIV (26) ADE7758 VARHR[15:0] 15 IRMS MULTIPLIER 0 VAG[11:0] LPF2 CURRENT RMS SIGNAL % 0x1C82B 40 + 0 + VADIV[7:0] 0x00 VRMS APPARENT POWER IS ACCUMULATED (INTEGRATED) IN THE VA-HR ACCUMULATION REGISTERS VOLTAGE RMS SIGNAL 0x17F263 50Hz 0x0 04443-A-048 0x174BAC 60Hz 0x0 Figure 75. ADE7758 Apparent Energy Accumulation Table 10. Inputs to VA-Hr Accumulation Registers CONSEL[1, 0] 00 AVAHR VARMS × IARMS BVAHR VBRMS × IBRMS CVAHR VCRMS × ICRMS 01 VARMS × IARMS VARMS + VCRMS × IBRMS 2 VCRMS × ICRMS 10 11 VARMS × IARMS Reserved VBRMS × IBRMS Reserved VCRMS × ICRMS Reserved Note: VARMS/VBRMS/VCRMS are the rms voltage waveform, and IARMS/IBRMS/ICRMS are the rms values of the current waveform. Energy Accumulation Mode The apparent power accumulated in each VA-hr accumulation register (AVAHR, BVAHR, or CVAHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 10. The contents of the VA-hr accumulation registers are affected by both the gain registers for the current (IGAIN) and rms voltage gain (VRMSGAIN), as well as the VAGAIN register of the corresponding phase. IGAIN should not be used when using CONSEL Mode 0, COMPMODE[0:1]. Apparent Power Frequency Output Pin 17 (VARCF) of the ADE7758 can provide frequency output for the total apparent power. By setting the VACF bit (Bit 7) of the WAVMODE register, this pin provides an output frequency that is directly proportional to the total apparent power. A digital-to-frequency converter (DFC) is used to generate the pulse output from the total apparent power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVAHR, BVAHR, and CVAHR registers in the total active power calculation. A pair of frequency divider registers, namely VARCFDEN and VARCFNUM, can be used to scale the output frequency of this pin. Note that either VAR or apparent power can be selected at one time for this frequency output (see the Reactive Power Frequency Output section). Line Cycle Apparent Energy Accumulation Mode The line cycle apparent energy accumulation mode is activated by setting the LVA bit (Bit 2) in the LCYCMODE register. The total apparent energy accumulated over an integer number of zero crossings is written to the VA-hr accumulation registers after the LINECYC number of zero crossings has been detected. The operation of this mode is similar to watt-hr accumulation (see the Line Cycle Active Energy Accumulation Mode section). When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. Note that this mode is especially useful when the user chooses to perform the apparent energy calculation using the vectorial method. By setting LWATT and LVAR bits (Bit 0 and Bit 1) of the LCYCMODE register, the active and reactive energies are accumulated over the same period of time. Therefore, the MCU can perform the squaring of the two terms and then take the square root of their sum to determine the apparent energy over the same period of time. Rev. A | Page 40 of 68 ADE7758 ENERGY REGISTERS SCALING CALIBRATION The ADE7758 provides measurements of active, reactive, and apparent energies that use separate signal paths and filtering for calculation. The differences in the data paths can result in small differences in LSB weight between the active, reactive, and apparent energy registers. These measurements are internally compensated so that the scaling is nearly one to one. The relationship between the registers is shown in Table 11. A reference meter or an accurate source is required to calibrate the ADE7758 energy meter. When using a reference meter, the ADE7758 calibration output frequencies, APCF and VARCF, are adjusted to match the frequency output of the reference meter under the same load conditions. Each phase must be calibrated separately in this case. When using an accurate source for calibration, one can take advantage of the line cycle accumulation mode and calibrate the three phases simultaneously. Table 11. Energy Registers Scaling Frequency of 60 Hz Integrator Off VAR = 1.004 × WATT VA = 1.00058 × WATT Frequency of 50 Hz VAR = 1.0054 × WATT VA = 1.0085 × WATT Integrator On VAR = 1.0059 × WATT VA = 1.00058 × WATT VAR = 1.0064 × WATT VA = 1.00845 × WATT There are two objectives in calibrating the meter: to establish the correct impulses/kW-hr constant on the pulse output and to obtain a constant that relates the LSBs in the energy and rms registers to Watt/VA/VAR hours, amps, or volts. Additionally, calibration compensates for part-to-part variation in the meter design as well as phase shifts and offsets due to the current sensor and/or input networks. Calibration Using Pulse Output WAVEFORM SAMPLING MODE The waveform samples of the current and voltage waveform, as well as the active, reactive, and apparent power multiplier outputs, can all be routed to the WAVEFORM register by setting the WAVSEL[2:0] bits (Bit 2 to Bit 4) in the WAVMODE register. The phase in which the samples are routed is set by setting the PHSEL[1:0] bits (Bit 0 and Bit 1) in the WAVMODE register. All energy calculation remains uninterrupted during waveform sampling. Four output sample rates may be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate may be 26.0 kSPS, 13.0 kSPS, 6.5 kSPS, or 3.3 kSPS (see Table 16). By setting the WSMP bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The 24-bit waveform samples are transferred from the ADE7758 one byte (8 bits) at a time, with the most significant byte shifted out first. The ADE7758 provides a pulsed output proportional to the active power accumulated by all three phases, called APCF. Additionally, the VARCF output is proportional to either the reactive energy or apparent energy accumulated by all three phases. The following section describes how to calibrate the gain, offset, and phase angle using the pulsed output information. The equations are based on the pulse output from the ADE7758 (APCF or VARCF) and the pulse output of the reference meter or CFEXPECTED. Figure 76 shows a flow chart of how to calibrate the ADE7758 using the pulse output. Since the pulse outputs are proportional to the total energy in all three phases, each phase must be calibrated individually. Writing to the registers is fast in order to reconfigure the part for calibrating a different phase, therefore Figure 76 shows a method that calibrates all phases at a given test condition before changing the test condition. The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see the ADE7758 Interrupts section). Rev. A | Page 41 of 68 ADE7758 CALIBRATE IRMS OFFSET START CALIBRATE VRMS OFFSET YES ALL PHASES VA AND WATT GAIN CAL? MUST BE DONE BEFORE VA GAIN CALIBRATION NO SET UP PULSE OUTPUT FOR A, B, OR C YES ALL PHASES GAIN CAL VAR? NO SET UP FOR PHASE A, B, OR C ALL PHASES PH CAL? YES NO CALIBRATE WATT AND VA GAIN @ PF = 1 WATT AND VA CAN BE CALIBRATED SIMUTANEOUSLY @ PF = 1 BECAUSE THEY HAVE SEPARATE PULSE OUTPUTS CALIBRATE VAR GAIN @ PF = 0 SET UP PULSE OUTPUT FOR A, B, OR C YES ALL PH VAR OFFSET CAL? CALIBRATE PHASE @ PF = 0.5 NO SET UP PULSE OUTPUT FOR A, B, AND C YES ALL PH WATT OFFSET CAL? NO CALIBRATE VAR OFFSET @ IMIN SET UP PULSE OUTPUT FOR A, B, AND C 04443-0-098 END CALIBRATE WATT OFFSET @ IMIN Figure 76. Calibration Using Pulse Output Gain Calibration Using Pulse Output Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. The registers used for watt gain calibration are CFNUM (0x45), CFDEN (0x46), and xWG (0x2A to 0x2C). Equations 32 through 34 show how these registers affect the Wh/LSB constant and the APCF pulses. For calibrating VAR gain, the registers in Equations 32 through 34 should be replaced by VARCFNUM (0x47), VARCFDEN (0x48), and xVARG (0x2D to 0x2F). For VAGAIN, they should be replaced by VARCFNUM (0x47), VARCFDEN (0x48), and xVAG (0x30 to 0x32). Figure 77 shows the steps for gain calibration of watts, VA, or VAR using the pulse outputs. Rev. A | Page 42 of 68 ADE7758 STEP 1 ENABLE CF AND VARCF PULSE OUTPUTS START STEP 1A SELECT VA FOR VARCF OUTPUT STEP 2 SET GAIN REGISTERS: XWG, XVAG, XVARG TO LOGIC 0 YES ALL PHASES VA AND WATT GAIN CAL? NO STEP 3 SELECT VAR FOR VARCF OUTPUT YES SET UP PULSE OUTPUT FOR PHASE A, B, OR C ALL PHASES VAR GAIN CALIBRATED? NO NO STEP 3 STEP 4 SET UP PULSE OUTPUT FOR PHASE A, B, OR C END NO CFNUM/VARCFNUM SET TO CALCULATE VALUES? VARCFNUM/ VARCFDEN SET TO CALCULATED VALUES? YES STEP 5 SET CFNUM/VARCFNUM AND CFDEN/VARCFDEN TO CALCULATED VALUES SET UP SYSTEM FOR ITEST, VNOM PF = 1 STEP 6 MEASURE % ERROR FOR APCF AND VARCF YES STEP 7 STEP 4 STEP 5 SET UP SYSTEM FOR ITEST, VNOM PF = 0 SET VARCFNUM/VARCFDEN TO CALCULATED VALUES STEP 6 MEASURE % ERROR FOR VARCF CALCULATE AND WRITE TO XWG, XVAG CALCULATE Wh/LSB AND VAh/LSB CONSTANTS STEP 7 CALCULATE kVARh/LSB CONSTANT 04443-0-099 CALCULATE AND WRITE TO XVARG Figure 77. Gain Calibration Using Pulse Output Step 1: Enable the pulse output by setting Bit 2 of the OPMODE register (0x13) to Logic 0. This bit enables both the APCF and VARCF pulses. Step 1a: VAR and VA share the VARCF pulse output. WAVMODE[7], Address (0x15), should be set to choose between VAR or VA pulses on the output. Setting the bit to Logic 1 selects VA. The default is Logic 0 or VARCF pulse output. Step 2: Ensure the xWG/xVARG/xVAG are set to Logic 0. Step 3: Disable the Phase B and Phase C contribution to the APCF and VARCF pulses. This is done by the TERMSEL[2:4] bits of the COMPMODE register (0x16). Setting Bit 2 to Logic 1 and Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in the pulse outputs. Step 4: Set APCFNUM(0x45) and APCFDEN(0x46) to the calculated value to perform a coarse adjustment on the imp/kWh ratio. For VAR/VA calibration, VARCFNUM (0x47) and VARCFDEN(0x48) should be set to the calculated value. The pulse output frequency with one phase at full-scale inputs Rev. A | Page 43 of 68 ADE7758 is approximately 16 kHz. A sample set of meters could be tested to find a more exact value of the pulse output at full scale. To calculated the values for APCFNUM/APCFDEN and VARCFNUM/VARCFDEN use the following formulas APCFNOMINAL = 16 kHz × APCFEXPECTED = VNOM VFULLSCALE × ITEST I FULLSCALE MC × ITEST × VNOM × cos (θ) 1,000 × 3,600 ⎛ APCFNOMINAL ⎞ APCFDEN = INT ⎜ ⎟ ⎝ APCFEXPECTED ⎠ APCF EXPECTED= (27) xWG = – (33) When APCF is calibrated, the xWATTHR registers have the same Wh/LSB from meter to meter if the meter constant and the APCFNUM/APCFDEN ratio remain the same. The Wh/LSB constant is Wh = LSB 1 MC APCFDEN 1 4 × × × 1,000 APCFNUM WDIV (34) Example—Watt Gain Calibration of Phase A Using Pulse Output (30) For this example, ITEST = 10 A, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 1, and Frequency = 50 Hz. Set APCFNUM(0x45) and APCFDEN(0x46) to the calculated value to perform a coarse adjustment on the imp/kWh ratio. Using Equations 27 through 29. Step 5: Set the test system for ITEST, VNOM, and the unity power factor. For VAR calibration, the power factor should be set to 0 in this step. For watt and VA, the unity power factor should be used. VAGAIN can be calibrated at the same time as WGAIN because VAGAIN can be calibrated at the unity power factor, and both pulse outputs can be measured simultaneously. However, when calibrating VAGAIN at the same time as WGAIN, the rms offsets should be calibrated first (see the Calibration of IRMS and VRMS Offset section). Step 6: Measure the percent error in the pulse output, APCF and/or VARCF, from the reference meter: APCF – CFREF × 100% CFREF % Error 0.0244% Step 8: Return to Step 2 to calibrate Phase B and Phase C gain. Because the CFNUM and CFDEN values can be calculated from the meter design, these values can be written to the part automatically during production calibration. % Error = APCFNUM[11 : 0] ⎛ xWG[11 : 0] ⎞ × ⎜1 + ⎟ APCFDEN[11 : 0] ⎝ 212 ⎠ (32) (29) The equations for calculating the VARCFNUM and VARCFDEN during VAR calibration are similar, with one exception MC × ITEST × VNOM × sin(θ) 1,000 × 3,600 APCFNOMINAL × (28) where MC is the meter constant, ITEST is the test current, VNOM is the nominal voltage that the meter is tested at, and VFULLSCALE and IFULLSCALE are the values of current and voltage, which correspond to the full scale ADC inputs of the ADE7758. θ is the angle between the current and the voltage channel, and the APCFEXPECTED value is equivalent to the reference meter output under the test conditions. VARCFEXPECTED = Step 7: Calculate xWG adjustment. One LSB change in xWG (12 bits) changes the WATTHR register by 0.0244% and therefore APCF by 0.0244%. The same relationship holds true for VARCF. (31) APCFNOMINAL = 16 kHz × APCFEXPECTED = 220 10 × = 0.542 kHz 500 130 3,200 × 10 × 220 1,000 × 3,600 × cos(0 ) = 1.96 Hz ⎛ 542 Hz ⎞ ⎟ = 277 APCFDEN = INT ⎜ ⎜ 1.96 Hz ⎟ ⎝ ⎠ With ITEST, VNOM, and the unity power factor, the example ADE7758 meter shows 1.92 Hz on the pulse output. This is equivalent to a 2.04% error from the reference meter value using Equation 31. where CFREF = APCFEXPECTED = the pulse output of the reference meter. Rev. A | Page 44 of 68 % Error = 1.92 Hz – 1.96 Hz 1.96 Hz × 100% = 2.04% ADE7758 The AWG value is calculated to be 84 d using Equation 33, which means the value 0x3F should be written to AWG. xWG = – Step 4: Calculate the Phase Error in degrees using the following equation: 2.04% = 84 0.0244% ⎛ CF Phase Error (° ) = – Arc sin⎜⎜ ERROR 3 ⎝ Phase Calibration Using Pulse Output The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758’s phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section). Because a current transformer is a source of phase error, a fixed nominal value may be decided on to load into the xPHCAL registers at power-up. During calibration, this value can be adjusted for CT-to-CT error. Figure 78 shows the steps involved in calibrating the phase using the pulse output. ⎞ ⎟⎟ ⎠ (35) Step 5: Calculate xPHCAL 1 Period( s ) Phase Error (°) – 2.4 μs × 360° × xPHCAL = (36) If it is not known, the period is available in the ADE7758’s frequency register, FREQ (0x10). Equation 37 shows how to determine the value that needs to be written to xPHCAL using the period register measurement. In Equation 37, the 2.4 µs is for phase errors that are negative. For positive phase errors, the 2.4 µs is replaced by 4.8 µs (see the Phase Compensation section). START 1 ⎛ Error ⎞ 9.6 µs 360° × = Arc sin⎜⎜ ⎟⎟ × xPHCAL ⎝ 3 ⎠ 2.4 µs FREQ[11 : 0 ] YES ALL PHASES PHASE ERROR CALIBRATED? (37) NO Example—Phase Calibration of Phase A Using Pulse Output STEP 1 SET UP PULSE OUTPUT FOR PHASE A, B, OR C AND ENABLE CF OUTPUTS END For this example, ITEST = 10 A, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 0.5 inductive, and Frequency = 50 Hz. STEP 2 SET UP SYSTEM FOR ITEST, VNOM, PF = 0.5 With ITEST, VNOM, and 0.5 inductive power factor, the example ADE7758 meter shows 0.9821Hz on the pulse output. This is equivalent to 0.215% error from the reference meter value using Equation 31. STEP 3 MEASURE % ERROR IN APCF The Phase Error in degrees using Equation 35 is −0.07°. STEP 4 ⎛ 0.00215 ⎞ Phase Error (°) = – Arc sin⎜⎜ ⎟ = – 0.07° 3 ⎟⎠ ⎝ CALCULATE PHASE ERROR (DEGREES) If at 50 Hz the FREQ register = 2083d, the value that should be written to APHCAL (0x15) is 0x15 using Equation 37. NO PERIOD OF SYSTEM KNOWN? YES APHCAL = 04443-0-100 STEP 5 MEASURE PERIOD USING FREQ REGISTER CALCULATE AND WRITE TO XPHCAL Figure 78. Phase Calibration Using Pulse Output Step 1: Step 1 and Step 3 from the gain calibration should be repeated to configure the ADE7758 pulse output. Step 2: Set the test system for ITEST, VNOM, and 0.5 power factor. Step 3: Measure the percent error in the pulse output, APCF, from the reference meter using Equation 31. 1 = 20.66 = 21 9.6µ s 360° × 0.07° × 2.4µ s 2083 Power Offset Calibration Using Pulse Output Power offset calibration should be used for outstanding performance over a wide dynamic range (1,000:1). Calibration of the power offset is done at or close to the minimum current where the desired accuracy is required. The ADE7758 has power offset registers for watts and VAR (xWATTOS and xVAROS). Offsets in the VA measurement are compensated by adjusting the rms offset registers (see the Calibration of IRMS and VRMS Offset section). Figure 79 shows the steps to calibrate the power offsets using the pulse outputs. Rev. A | Page 45 of 68 ADE7758 STEP 1 ENABLE CF OUTPUT START STEP 2 SET OFFSET REGISTERS XWATTOS, XVAROS TO LOGIC 0 YES ALL PHASES WATT OFFSET AND VA OFFSET CALIBRATED? NO SET UP APCF PULSE OUTPUT FOR PHASE A, B, OR C YES ALL PHASES VAR OFFSET CALIBRATED? SET UP VARCF PULSE OUTPUT FOR PHASE A, B, OR C STEP 4 STEP 3 SET UP SYSTEM FOR IMIN, VNOM, PF = 0 STEP 5 END STEP 6. REPEAT STEP 3 TO STEP 5 FOR XVAROS STEP 3 SET UP SYSTEM FOR IMIN, VNOM, PF = 1 NO MEASURE % ERROR FOR APCF CALCULATE AND WRITE TO XWATTOS STEP 4 MEASURE % ERROR FOR VARCF MEASURE PERIOD USING PERIOD REGISTER 04443-0-101 STEP 5 CALCULATE AND WRITE TO XVAROS Figure 79. Offset Calibration Using Pulse Output xVAROS = Step 1: Repeat Step 1 and Step 3 from the gain calibration to configure the ADE7758 pulse output. – (%VARCFERROR × VARCFEXPECTED ) × Step 2: Set the xWATTOS and xVAROS registers to Logic 0. Step 3: Set the test system for ITEST = IMIN, VNOM, and unity power factor. For Step 6, set the test system for ITEST = IMIN, VNOM, and zero-power factor. where Q is defined in Equation 40 and Equation 41. For xWATTOS Step 4: Measure the percent error in the pulse output, APCF or VARCF, from the reference meter using Equation 31. Step 5: Calculate xWATTOS using Equation 38 (for xVAROS use Equation 39). Q= Q= 4 2 APCFDEN × Q APCFNUM (38) 1 1 CLKIN × 25 × 4 4 2 (40) For xVAROS xWATTOS = – (% APCFERROR × APCFEXPECTED ) × 24 VARCFDEN × Q VARCFNUM (39) CLKIN 1 202 1 × 24 × × 4 2 ⎛ PERIOD ⎞ 4 ⎜ ⎟ 4 ⎝ ⎠ (41) where PERIOD is measured from the FREQ (0x10) register. Step 6: Repeat Step 3 to Step 5 for xVAROS calibration. Rev. A | Page 46 of 68 ADE7758 Example—Offset Calibration of Phase a Using Pulse Output START For this example, ITEST = 50 mA, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 1, Frequency = 50 Hz, and CLKIN = 10 MHz. CAL IRMS OFFSET CAL VRMS OFFSET With ITEST, VNOM, and unity power factor, the example ADE7758 meter shows 0.009773 Hz on the APCF pulse output and 0.009773 Hz on the VARCF pulse output. This is equivalent to 0.24% for the watt measurement and 0.24% for the VAR measurement. Using Equations 38 through 41, the values 0xFFB and 0xFFA should be written to AWATTOS (0x39) and VAROS (0x3C), respectively. CAL WATT AND VA GAIN ALL PHASES @ PF = 1 CAL VAR GAIN ALL PHASES @ PF = 0 CALIBRATE PHASE ALL PHASES @ PF = 0.5 For AWATTOS: Q= 10 E 6 1 1 × 25 × = 0.0186 4 4 2 CALIBRATE ALL PHASES WATT OFFSET @ IMIN AND PF = 1 For AVAROS: CALIBRATE ALL PHASES VAR OFFSETS @ IMIN AND PF = 0 10 E 6 1 202 1 × 24 × × = 0.014 2083 4 4 2 4 END 24 227 AWATTOS = –(0.0024 × 0.00975) × × = – 4.5 0.0186 1 AVAROS = –(0.0024 × 0.00975) × 24 227 × = –6 0.014 1 04443-0-103 Q= Figure 80. Calibration Using Line Accumulation Gain Calibration Using Line Accumulation Calibration Using Line Accumulation Line cycle accumulation mode configures the nine energy registers such that the amount of energy accumulated over an integer number of half line cycles appears in the registers after the LINECYC interrupt. The benefit of using this mode is that the sinusoidal component of the active energy is eliminated. Figure 80 shows a flow chart of how to calibrate the ADE7758 using the line accumulation mode. Calibration of all phases and energies can be done simultaneously using this mode to save time during calibration. Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. Step 0: Before performing the gain calibration, the CFNUM/CFDEN (0x45/0x46) and VARCFNUM/VARCFDEN (0x47/0x48) values can be set to achieve the correct impulses/kWh, impulses/kVAh, or impulses/kVARh using the same method outlined in Step 4 in the Gain Calibration Using Pulse Output section. The calibration of xWG/xVARG/xVAG (0x2A through 0x32) is done with the line accumulation mode. Figure 81 shows the steps involved in calibrating the gain registers using the line accumulation mode. Rev. A | Page 47 of 68 ADE7758 STEP 0 SET CFNUM/CFDEN AND VARCFNUM/VARCFDEN STEP 1 SET XWG/XVAR/XVAG TO LOGIC 0 STEP 2 SET LYCMODE REGISTER STEP 3 CHOOSE ACCUMULATION TIME (LINECYC) STEP 4 SET MASK FOR LENERGY INTERRUPT STEP 5 SET UP SYSTEM FOR ITEST, VNOM, PF = 1 CALIBRATE WATT AND VA @ PF = 1 STEP 10 SET UP TEST SYSTEM FOR ITEST, VNOM, PF = 0 STEP 11 YES FREQUENCY KNOWN? RESET STATUS REGISTER STEP 7 RESET STATUS REGISTER STEP 8 STEP 6 READ FREQUENCY REGISTER READ ALL XWATTHR AND XVAHR AFTER LENERGY STEP 8A STEP 12 READ ALL XVARHR AFTER LENERGY INTERRUPT STEP 13 CALCULATE XVARG STEP 14 CALCULATE XWG STEP 8B CALCULATE XVAG WRITE TO XVARG STEP 15 CALCULATE WH/LSB, VAH/LSB, VARH/LSB STEP 9 WRITE TO XWG AND XVAG END 04443-0-104 NO Figure 81. Gain Calibration Using Line Accumulation Step 1: Set xWG, xVARG, and xVAG to Logic 0. Step 2: Set up ADE7758 for line accumulation by writing 0x3F to LCYCMODE. This enables the line accumulation mode on the xWATTHR, xVAHR, and xVARHR (0x01 to 0x03) registers by setting the LWATT, LVAR, and LVA bits, LCYCMODE[0:2] (0x17), to Logic 1. It also sets the ZXSEL bits, LCYCMODE[3:5], to Logic 1 to enable the zero-crossing detection on all phases for line accumulation. Additionally, the FREQSEL bit, LCYCMODE[7], is set to Logic 0 so that FREQ (0x10) stores the line frequency. When using the line accumulation mode, the RSTREAD bit of LCYCMODE should be set to 0 to disable the read with reset mode. Step 3: Set the number of half-line cycles for line accumulation by writing to LINECYC (0x1C). Step 4: Set the LENERGY bit, MASK[12] (0x18), to Logic 1 to enable the interrupt that signals the end of the line cycle accumulation. Step 5: Set the test system for ITEST, VNOM, and unity power factor (calibrate watt and VA simultaneously and first). Step 6: Read the FREQ (0x10) register if the frequency is unknown. Step 7: Reset the interrupt status register by reading RSTATUS (0x1A). Rev. A | Page 48 of 68 ADE7758 Step 8: Read all six xWATTHR (0x01 to 0x03) and xVAHR (0x07 to 0x09) energy registers after the LENERGY interrupt and store the values. Step 8a: Calculate the values to be written to xWG registers according to the following equation. xWG 4 × MC × ITEST × VTEST × cos (θ ) = × 1,000 × 3,600 212 AccumTime × WDIV xWATTHR[11 : 0] (42) LINECYC [15 : 0] 2 × Line Frequency × No. of Phases Selected (43) MC is the meter constant, θ is the angle between the current and voltage, Line Frequency is read from the FREQ register or is known, and the No. of Phases Selected are the number of ZXSEL bits set to Logic 1 in LCYCMODE (0x17). To set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kW-hr ratio, use Equation 27 to Equation 29: APCFNOMINAL = 16 kH z × APCFEXPECTED = APCFDEN = INT (44) Step 9: Write to xWG and xVAG. Step 10: Set the test system for ITEST, VNOM, and zero power factor (calibrate VAR gain). Step 12: Read the xVARHR (0x04 to 0x06) after the LENERGY interrupt and store the values. Step 13: Calculate the values to be written to the xVARG registers (to adjust VARCF to the expected value). 220 10 × = 0.54 500 130 3,200 × 10 × 220 1,000 × 3,600 541 Hz 1.95 Hz × cos(θ ) = 1.95 Hz = 227 Under the test conditions above, the AWATTHR register value is 24008d after the LENERGY interrupt. Using Equation 42 and Equation 43, the value to be written to AWG is 02d. Step 11: Repeat Step 7. AccumTime = 0 x 1 FF = 1.7 s 2 × 50 × 3 xWG = 212 × 4 × 3,200 × 10 × 220 × 1 1.7 s × × 1 = 2.268 1,000 × 3,600 24,008 Using Equation 46, the Wh/LSB constant is 10 × 220 × 1.7 Wh = = 4.33 × 10–5 LSB 3,600 × 24,008 xVAG 4 × MC × ITEST × VTEST × sin(θ ) × = 1,000 × 3,600 212 (45) Step 14: Write to xVARG. Step 15: Calculate the Wh/LSB, VARh/LSB, and VAh/LSB constants. Wh ITEST × VNOM × AccumTime = LSB 3,600 × xWATTHR (48) For this example, ITEST = 10 A, VNOM = 220 V, Power Factor = 1, Frequency = 50 Hz, LINECYC (0x1C) is set to 1FF, and MC = 3200 imp/kWhr. xVAG 4 × MC × ITEST × VTEST × cos (θ ) = × 1,000 × 3,600 212 AccumTime × VADIV xVAHR[11 : 0] VARh ITEST × VNOM × AccumTime = LSB 3,600 × xVARHR This example only shows Phase A watt calibration. The steps outlined in the Gain Calibration Using Line Accumulation section show how to calibrate watt, VA, and VAR. All three phases can be calibrated simultaneously because there are nine energy registers. Step 8b: Calculate the values to be written to the xVAG registers according to the following equation. AccumTime × VADIV xVAHR[11 : 0] (47) Example—Watt Gain Calibration Using Line Accumulation where Accumulation Time is AccumTime = VAh ITEST × VNOM × AccumTime = LSB 3,600 × xVAHR (46) Phase Calibration Using Line Accumulation The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758’s phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section). Since a current transformer is a source of phase error, a fixed nominal value may be decided on to load into the xPHCAL (0x3F to 0x41) registers at power-up. During calibration, this value can be adjusted for CT-to-CT error. Rev. A | Page 49 of 68 ADE7758 Step 6: Calculate xPHCAL and write to the xPHCAL registers (0x3F to 0x41). Figure 82 shows the steps involved in calibrating the phase using the line accumulation mode. STEP 1 SET LCYCMODE, LINECYC AND MASK REGISTERS xPHCAL = 1 Period( s ) Phase Error (°) – 2.4 µs × 360° × (51) STEP 2 The period is available in the ADE7758 frequency register if it is not known. Equation 37 shows how to determine the value written to xPHCAL using the period register measurement (see the Phase Calibration Using Pulse Output section). In Equation 37, the 2.4 µs is for phase errors that are negative. For positive phase error, the 2.4 µs is replaced by 4.8 µs (see the Phase Compensation section). SET UP SYSTEM FOR ITEST, VNOM, PF = 0.5 STEP 3 RESET STATUS REGISTER STEP 4 READ ALL XWATTHR REGISTERS AFTER LENERGY INTERRUPT Example—Phase Calibration Using Line Accumulation STEP 5 This example shows only Phase A phase calibration. All three PHCAL registers can be calibrated simultaneously using the same method. STEP 6 CALCULATE AND WRITE TO ALL XPHCAL REGISTERS 04443-0-105 CALCULATE PHASE ERROR IN DEGREES FOR ALL PHASES For this example, ITEST = 10 A, VNOM = 220 V, Power Factor = 0.5 inductive, and Frequency = 50 Hz. Figure 82. Phase Calibration Using Line Accumulation Step 1: If the values were changed after gain calibration, Step 1, Step 3, and Step 4 from the gain calibration should be repeated to configure the LCYCMODE and LINECYC registers. With ITEST, VNOM, and 0.5 inductive power factor, the example ADE7758 meter shows 12036d in the AWATTHR (0x01) register. For unity power factor (after gain calibration), the meter shows 24020d in the AWATTHR register. This is equivalent to 26 LSBs of error. Step 2: Set the test system for ITEST, VNOM, and 0.5 power factor. The Phase Error in degrees using Equation 50 is −0.07°. Step 3: Reset the interrupt status register by reading RSTATUS (0x1A). Step 4: The xWATTHR registers should be read after the LINECYC interrupt. Measure the percent error in the energy register readings (AWATTHR, BWATTHR, and CWATTHR) compared to the energy register readings at unity power factor (after gain calibration) using Equation 49. The readings at unity power factor should have been repeated after the gain calibration and stored for use in the phase calibration routine. Error = xWATTHRPF = 1 2 xWATTHRPF = 1 2 xWATTHRPF = 5 – (50) Using Equation 37, the value written to APHCAL (0x3F), if at 50 Hz the FREQ (0x10) register = 2083d, is 21d. ⎛ ⎞ 1 ⎟ 2.4 µ s × 360° × ⎜ ⎜ 2083 × 9.6 µ s ⎟ ⎝ ⎠ = 21 APHCAL = .07° Power Offset Calibration Using Line Accumulation (49) Step 5: Calculate the Phase Error in degrees using the following equation. ⎛ Error ⎞ Phase Error (° ) = – Arcsin⎜ ⎟ ⎝ 3 ⎠ ⎛ 0.00215 ⎞ Phase Error (°) = –Arc sin⎜ ⎟ = –0.07° 3 ⎠ ⎝ Power offset calibration should be used for outstanding performance over a wide dynamic range (1,000:1). Calibration of the power offset is done at or close to the minimum current. The ADE7758 has power offset registers for watts and VAR, xWATTOS (0x39 to 0x3B) and xVAROS (0x3C to 0x3E). Offsets in the VA measurement are compensated by adjusting the rms offset registers (see the Calibration of IRMS and VRMS Offset section). Figure 83 shows the steps to calibrate the power offsets using the line accumulation mode. Rev. A | Page 50 of 68 ADE7758 STEP 1 SET LCYCMODE, LINECYC AND MASK REGISTERS STEP 2 SET UP SYSTEM FOR ITEST, VNOM @ PF = 1 STEP 6 STEP 3 RESET STATUS REGISTER STEP 4 FOR STEP 10 READ ALL XVARHR AFTER LENERGY INTERRUPT YES STEP 7 CALCULATE XWATTOS FOR ALL PHASES STEP 8 WRITE TO ALL XWATTOS REGISTERS STEP 5 READ ALL XWATTHR REGISTERS AFTER LENERGY INTERRUPT TESTED @ IMIN? SET UP SYSTEM FOR IMIN, VNOM @ PF = 1 FOR STEP 10, PF = 0 NO FOR STEP 10, CALCULATE XVAROS FOR ALL PHASES FOR STEP 10, WRITE TO ALL XVAROS REGISTERS STEP 9 STEP 10 REPEAT STEP 3 TO STEP 8 FOR XVARHR, XVAROS CALIBRATION 04443-0-107 SET UP SYSTEM FOR ITEST, VNOM @ PF = 0 END Figure 83. Power Offset Calibration Using Line Accumulation Step 1: If the values were changed after gain calibration, Step 1, Step 3, and Step 4 from the gain calibration should be repeated to configure the LCYCMODE, LINECYC, and MASK registers. Step 7: Calculate the value to be written to the xWATTOS registers according to the following equations. Offset = Step 2: Set the test system for ITEST, VNOM, and unity power factor. Step 3: Reset the interrupt status register by reading RSTATUS (0x1A). Step 4: Read all xWATHR energy registers (0x01 to 0x03) after the LENERGY interrupt and store the values. xWATTHR I MIN × ITEST – xWATTHR I TEST × I MIN I MIN – ITEST (52) xWATTOS[11 : 0] = Offset × 4 × 229 AccumTime × CLKIN (53) Step 4a: Read the FREQ (0x10) register if the frequency is unknown. where Accumulation Time is defined in Equation 43 and xWATTHRITEST is the value in the energy register at ITEST, and xWATTHRIMIN is the value in the energy register at IMIN. Step 5: Set the test system for IMIN, VNOM, and unity power factor. Step 8: Write to all xWATTOS registers (0x39 to 0x3B). Step 6: Repeat Step 3 and Step 4. Step 9: Set the test system for ITEST, VNOM, and zero power factor (calibrate VAR gain). Step 10: Repeat Steps 3, 4, and 5. Rev. A | Page 51 of 68 ADE7758 Calibration of IRMS and VRMS Offset Step 11: Calculate the value written to the xVAROS registers according to the following equations. Offset = xVARHR × ITEST – xVARHR × I MIN I MIN – ITEST xVAROS[11 : 0] + Offset × 4 × 229 AccumTime × CLKIN (54) (55) Example—Power Offset Calibration Using Line Accumulation This example only shows Phase A of the phase active power offset calibration. Both active and reactive power offset for all phases can be calibrated simultaneously using the method explained in the Power Offset Calibration Using Line Accumulation section. For this example, ITEST = 10 A, IMIN = 100 mA, VNOM = 220 V, Power Factor = unity, Frequency = 50 Hz, and LINECYC = 0xFFF. At ITEST, the example ADE7758 meter shows 192489d in the AWATTHR (0x01) register after gain calibration at 0xFFF line cycles. At IMIN, the meter shows 1919d in the AWATTHR register. By using Equation 52, this is equivalent to the 6 LSBs of offset, therefore, using Equation 53, the value written to AWATTOS is 94d. Offset = IRMSOS and VRMSOS are used to cancel noise and offset contributions from the inputs. The calibration method is the same whether calibrating using the pulse outputs or line accumulation. Reading the registers is required for this calibration since there is no rms pulse output. The rms offset calibration should be performed before VAGAIN calibration. The rms offset calibration also removes offset from the VA calculation. For this reason, no VA offset register exists in the ADE7758. The low-pass filter used to obtain the rms measurements is not ideal, therefore it is recommended to synchronize the readings with the zero crossings of the voltage waveform and to average a few measurements when reading the rms registers. The ADE7758 IRMS measurement is linear over a 500:1 range, and the VRMS measurement is linear over a 20:1 range. To measure the voltage VRMS offset (xVRMSOS), measure rms values at two different nonzero current levels, for example, VNOM and VNOM/20. To measure the current rms offset (IRMSOS), measure rms values at two different nonzero current levels, for example, ITEST and IMAX/500). This translates to three test conditions: ITEST and VNOM, IMAX/500 and VNOM, ITEST and VNOM/20. Figure 84 shows a flow chart for calibrating the rms measurements. 1919 × 10 – 192,489 × 0.1 = 5.95 0.1 – 10 AWATTOS = 6×4 13.65 × 10 MHz × 229 = 94.39 Rev. A | Page 52 of 68 ADE7758 START STEP 1 SET CONFIGURATION REGISTERS FOR ZERO CROSSING ON ALL PHASES STEP 2 SET INTERRUPT MASK FOR ZERO CROSSING ON ALL PHASES STEP 4A YES TESTED ALL PHASES? CHOOSE N n=0 NO STEP 3 NO TESTED ALL CONDITIONS? 2 n = N? STEP 4E CALCULATE THE AVERAGE OF N SAMPLES n=n+1 SET UP SYSTEM FOR ITEST, VNOM 3 SET UP SYSTEM FOR IMAX/500, VNOM STEP 4B RESET INTERRUPT STATUS REGISTER SET UP SYSTEM FOR ITEST, VNOM/20 STEP 4 INTERRUPT? NO STEP 4D READ RMS REGISTERS READ XIRMS XVRMS 04443-0-102 WRITE TO XVRMSOS XIRMSOS END STEP 4C YES STEP 5 YES 1 Figure 84. RMS Calibration Routine Step 1: Set configuration registers for zero crossings on all phases by writing the value 0x38 to the LCYCMODE register (0x17). This sets all of the ZXSEL bits to Logic 1. Step 2: Set the interrupt mask register for zero-crossing detection on all phases by writing 0xE00 to the MASK[0:24] register (0x18). This sets all of the ZX bits to Logic 1. Step 4d. Read the xIRMS (0x0A) and xVRMS (0x0C) registers. These values will be averaged in Step 4e. Step 4e: Average the N samples of xIRMS and xVRMS. The averaged values will be used in Step 5. Step 5: Write to the xVRMSOS (0x36 to 0x38) and xIRMSOS (0x33 to 0x35) registers according to the following equations. IRMSOS = Step 3: Set up the calibration system for one of the three test conditions: ITEST and VNOM, IMAX/500 and VNOM, ITEST and VNOM/20. Step 4: Read the rms registers after the zero-crossing interrupt and take an average of N samples. This is recommended to get the most stable rms readings. This procedure is detailed in Figure 84—Steps 4a through 4e. − (I 2 × I MAX/X −RMS 2 ) – (I MAX/X 2 × ITEST −RMS 2 ) 1 × TEST 16,384 I MAX/X 2 – ITEST 2 (56) where ITEST-RMS and IMAX/X-RMS are the rms register values without the offset correction for the input ITEST and IMAX/X, respectively. Step 4a. Choose the number of samples, N, to be averaged. VRMSOS = Step 4b. Reset the interrupt status register by reading RSTATUS (0x1A). Step 4c. Wait for the zero-crossing interrupt. When the zerocrossing interrupt occurs, move to Step 4d. 1 VNOM × VNOM/20 −RMS – VNOM/20 × VNOM −RMS × 64 VNOM/20 – VNOM (57) where VNOM-RMS and VNOM/20-RMS are the rms register values without the offset correction for the input VNOM and VNOM/20-RMS, respectively. Rev. A | Page 53 of 68 ADE7758 Example—Calibration of RMS Offsets ADE7758 INTERRUPTS For this example, ITEST = 10 A, IMAX = 100 A, VNOM = 220 V, VFULLSCALE = 500 V, Power Factor = 1, and Frequency = 50 Hz. The ADE7758 interrupts are managed through the interrupt status register (STATUS[23:0], Address 0x19) and the interrupt mask register (MASK[23:0], Address 0x18). When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is set to a Logic 1 (see Table 20). If the mask bit for this interrupt in the interrupt mask register is Logic 1, then the IRQ logic output goes active low. The flag bits in the interrupt status register are set irrespective of the state of the mask bits. To determine the source of the interrupt, the system master (MCU) should perform a read from the reset interrupt status register with reset. This is achieved by carrying out a read from RSTATUS, Address 0x1A. The IRQ output goes logic high on completion of the interrupt status register read command (see the Interrupt Timing section). When carrying out a read with reset, the ADE7758 is designed to ensure that no interrupt events are missed. If an interrupt event occurs just as the interrupt status register is being read, the event is not lost and the IRQ logic output is guaranteed to go logic high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. Note that the reset interrupt bit in the status register is high for only one clock cycle; then it goes back to 0. With ITEST and VNOM, the example ADE7758 meter shows 0x34266 in the AIRMS (0x0A) register and 0x10B0A3 in the AVRMS (0x0D) register. At IMAX/500, the example meter shows 0x19F in AIRMS. At VNOM/20, the example meter shows 0xD65B in the AVRMS register. These are the average value of 20 samples synchronous to the zero crossings of all three phases. Using this data, −3d is written to AVRMSOS (0x33) and −1004d is written to AIRMSOS (0x36) registers according to the Equation 56 and Equation 57. xIRMSOS = −1 × 16,384 (102 × 4152 ) – (0.22 × 213,6062 ) = − 1103.88 = − 1104 (0.2 – 102 ) xVRMSOS = 1 (220 × 54875) – (11 × 1,093,795) × = − 3.047 = − 3 (11 – 220) 64 This example shows the calculations and measurements for Phase A only. However, all three xIRMS and xVRMS registers can be read simultaneously to compute the values for each xIRMSOS and xVRMSOS register. CHECKSUM REGISTER The ADE7758 has a checksum register CHECKSUM[7:0] (0x7E) to ensure the data bits received in the last serial read operation are not corrupted. The 8-bit checksum register is reset before the first bit (MSB of the register to be read) is put on the DOUT pin. During a serial read operation, when each data bit becomes available on the rising edge of SCLK, the bit is added to the checksum register. In the end of the serial read operation, the content of the checksum register is equal to the sum of all the ones in the register previously read. Using the checksum register, the user can determine if an error has occurred during the last read operation. Note that a read to the checksum register also generates a checksum of the checksum register itself. CONTENT OF REGISTERS (N-BYTES) CHECKSUM REGISTER ADDR: 0x7E Figure 85. Checksum Register for Serial Interface Read 04443-0-049 DOUT USING THE ADE7758 INTERRUPTS WITH AN MCU Figure 87 shows a timing diagram that illustrates a suggested implementation of ADE7758 interrupt management using an MCU. At time t1, the IRQ line goes active low indicating that one or more interrupt events have occurred in the ADE7758. The IRQ logic output should be tied to a negative edge triggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its interrupt service routine (ISR). On entering the ISR, all interrupts should be disabled using the global interrupt mask bit. At this point, the MCU external interrupt flag can be cleared in order to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from the reset interrupt status register with reset is carried out. (This causes the IRQ line to be reset logic high (t2)—see the Interrupt Timing section.) The reset interrupt status register contents are used to determine the source of the interrupt(s) and hence the appropriate action to be taken. If a subsequent interrupt event occurs during the ISR (t3) that event is recorded by the MCU external interrupt flag being set again. On returning from the ISR, the global interrupt mask bit is cleared (same instruction cycle) and the external interrupt flag uses the MCU to jump to its ISR once again. This ensures that the MCU does not miss any external interrupts. The reset bit in the status register is an exception to this, and is only high for one clock cycle after a reset event. Rev. A | Page 54 of 68 ADE7758 INTERRUPT TIMING the ADE7758 is the only device on the serial bus. However, with CS tied low, all initiated data transfer operations must be fully completed. The LSB of each register must be transferred because there is no other way of bringing the ADE7758 back into communications mode without resetting the entire device, i.e., performing a software reset using Bit 6 of the OPMODE[7:0] register, Address 0x13. The functionality of the ADE7758 is accessible via several on-chip registers (see Figure 86). The contents of these registers can be updated or read using the onchip serial interface. After a falling edge on CS, the ADE7758 is placed in communications mode. In communications mode, the ADE7758 expects the first communication to be a write to the internal communications register. The data written to the communications register contains the address and specifies the next data transfer to be a read or a write command. Therefore, all data transfer operations with the ADE7758, whether a read or a write, must begin with a write to the communications register. ADE7758 SERIAL INTERFACE The ADE7758 has a built-in SPI interface. The serial interface of the ADE7758 is made of four signals: SCLK, DIN, DOUT, and CS. The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt trigger input structure that allows slow rising (and falling) clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is shifted into the ADE7758 at the DIN logic input on the falling edge of SCLK. Data is shifted out of the ADE7758 at the DOUT logic output on a rising edge of SCLK. The CS logic input is the chip select input. This input is used when multiple devices share the serial bus. A falling edge on CS also resets the serial interface and places the ADE7758 in communications mode. The CS input should be driven low for the entire data transfer operation. Bringing CS high during a data transfer operation aborts the transfer and place the serial bus in a high impedance state. The CS logic input may be tied low if t1 COMMUNICATIONS REGISTER DIN DOUT REGISTER NO. 1 IN OUT REGISTER NO. 2 IN OUT REGISTER NO. 3 IN OUT REGISTER NO. n–1 IN OUT REGISTER NO. n IN OUT REGISTER ADDRESS DECODE 04443-0-052 The ADE7758 Serial Interface section should be reviewed first before reviewing this interrupt timing section. As previously described, when the IRQ output goes low, the MCU ISR must read the interrupt status register in order to determine the source of the interrupt. When reading the interrupt status register contents, the IRQ output is set high on the last falling edge of SCLK of the first byte transfer (read interrupt status register command). The IRQ output is held high until the last bit of the next 8-bit transfer is shifted out (interrupt status register contents)—see Figure 87. If an interrupt is pending at this time, the IRQ output goes low again. If no interrupt is pending, the IRQ output remains high. Figure 86. Addressing ADE7758 Registers via the Communications Register t2 MCU INTERRUPT FLAG SET t3 PROGRAM SEQUENCE JUMP TO ISR GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUS WITH RESET (0x1A) ISR RETURN GLOBAL INTERRUPT MASK RESET ISR ACTION (BASED ON STATUS CONTENTS) 04443-A-050 IRQ JUMP TO ISR Figure 87. ADE7758 Interrupt Management CS t1 t9 SCLK DIN 0 0 0 1 0 0 0 1 t11 DOUT t12 DB15 DB8 DB7 DB0 STATUS REGISTER CONTENTS IRQ Figure 88. ADE7758 Interrupt Timing Rev. A | Page 55 of 68 04443-0-051 READ STATUS REGISTER COMMAND ADE7758 The communications register is an 8-bit write-only register. The MSB determines whether the next data transfer operation is a read or a write. The seven LSBs contain the address of the register to be accessed. See Table 12 for a more detailed description. MSB of this byte transfer must be set to 1, indicating that the next data transfer operation is a write to the register. The seven LSBs of this byte contain the address of the register to be written to. The ADE7758 starts shifting in the register data on the next falling edge of SCLK. All remaining bits of register data are shifted in on the falling edge of the subsequent SCLK pulses (see Figure 91). Figure 89 and Figure 90 show the data transfer sequences for a read and write operation, respectively. On completion of a data transfer (read or write), the ADE7758 once again enters into communications mode, i.e., the next instruction followed must be a write to the communications register. As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7758, data is transferred to all onchip registers one byte at a time. After a byte is transferred into the serial port, there is a finite time duration before the content in the serial port buffer is transferred to one of the ADE7758 on-chip registers. Although another byte transfer to the serial port can start while the previous byte is being transferred to the destination register, this second-byte transfer should not finish until at least 900 ns after the end of the previous byte transfer. This functionality is expressed in the timing specification t6 (see Figure 91). If a write operation is aborted during a byte transfer (CS brought high), then that byte is not written to the destination register. CS SCLK COMMUNICATIONS REGISTER WRITE 0 ADDRESS DOUT MULTIBYTE 04443-0-053 DIN READ DATA Figure 89. Reading Data from the ADE7758 via the Serial Interface CS 04443-0-054 SCLK COMMUNICATIONS REGISTER WRITE DIN 1 ADDRESS MULTIBYTE READ DATA Destination registers may be up to 3 bytes wide (see the Accessing the ADE7758 On-Chip Registers section). Therefore, the first byte shifted into the serial port at DIN is transferred to the most significant byte (MSB) of the destination register. If the destination register is 12 bits wide, for example, a two-byte data transfer must take place. The data is always assumed to be right justified; therefore, in this case, the four MSBs of the first byte would be ignored and the four LSBs of the first byte written to the ADE7758 would be the four MSBs of the 12-bit word. Figure 92 illustrates this example. Figure 90. Writing Data to the ADE7758 via the Serial Interface A data transfer is completed when the LSB of the ADE7758 register being addressed (for a write or a read) is transferred to or from the ADE7758. ADE7758 SERIAL WRITE OPERATION The serial write sequence takes place as follows. With the ADE7758 in communications mode and the CS input logic low, a write to the communications register takes place first. The t8 CS t6 t3 t7 t7 SCLK t4 t2 1 DIN A6 A5 A4 t5 A3 A2 A1 A0 DB7 DB0 DB7 MOST SIGNIFICANT BYTE COMMAND BYTE DB0 LEAST SIGNIFICANT BYTE Figure 91. Serial Interface Write Timing Diagram DIN X X X X DB11 DB10 DB9 DB8 DB7 MOST SIGNIFICANT BYTE DB6 DB5 DB4 DB3 DB2 LEAST SIGNIFICANT BYTE Figure 92. 12-Bit Serial Write Operation Rev. A | Page 56 of 68 DB1 DB0 04443-0-056 SCLK 04443-0-055 t1 ADE7758 read has been completed. The DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse. The read operation may be aborted by bringing the CS logic input high before the data transfer is completed. The DOUT output enters a high impedance state on the rising edge of CS. ADE7758 SERIAL READ OPERATION During a data read operation from the ADE7758, data is shifted out at the DOUT logic output on the rising edge of SCLK. As was the case with the data write operation, a data read must be preceded with a write to the communications register. When an ADE7758 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. This allows the ADE7758 to modify its on-chip registers without the risk of corrupting data during a multibyte transfer. With the ADE7758 in communications mode and CS logic low, an 8-bit write to the communications register first takes place. The MSB of this byte transfer must be a 0, indicating that the next data transfer operation is a read. The seven LSBs of this byte contain the address of the register that is to be read. The ADE7758 starts shifting out of the register data on the next rising edge of SCLK (see Figure 93). At this point, the DOUT logic output switches from a high impedance state and starts driving the data bus. All remaining bits of register data are shifted out on subsequent SCLK rising edges. The serial interface enters communications mode again as soon as the Note that when a read operation follows a write operation, the read command (i.e., write to communications register) should not happen for at least 1.1 µs after the end of the write operation. If the read command is sent within 1.1 µs of the write operation, the last byte of the write operation may be lost. CS t1 t13 t9 SCLK 0 A6 A5 A4 A3 A2 A1 A0 t12 t11 DOUT DB7 COMMAND BYTE DB0 MOST SIGNIFICANT BYTE Figure 93. Serial Interface Read Timing Diagram Rev. A | Page 57 of 68 DB7 DB0 LEAST SIGNIFICANT BYTE 04443-0-057 DIN t10 ADE7758 ACCESSING THE ADE7758 ON-CHIP REGISTERS COMMUNICATIONS REGISTER All ADE7758 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. For a full description of the serial interface protocol, see the ADE7758 Serial Interface section. The communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7758 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. Table 12 outlines the bit designations for the communications register. Table 12. Communications Register Bit Location 0 to 6 Bit Mnemonic A0 to A6 7 W/R Description The seven LSBs of the communications register specify the register for the data transfer operation. Table 13 lists the address of each ADE7758 on-chip register. When this bit is a Logic 1, the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7758. When this bit is a Logic 0, the data transfer operation immediately following the write to the communications register is interpreted as a read operation. DB7 W/R DB6 DB5 DB4 DB3 DB2 DB1 DB0 A6 A5 A4 A3 A2 A1 A0 Table 13. ADE7758 Register List Address [A6:A0] 0x00 0x01 Name Reserved AWATTHR R/W1 – R Length Default Value 16 0 0x02 0x03 0x04 BWATTHR CWATTHR AVARHR R R R 16 16 16 0 0 0 0x05 0x06 0x07 BVARHR CVARHR AVAHR R R R 16 16 16 0 0 0 0x08 0x09 0x0A BVAHR CVAHR AIRMS R R R 16 16 24 0 0 0 0x0B 0x0C 0x0D 0x0E BIRMS CIRMS AVRMS BVRMS R R R R 24 24 24 24 0 0 0 0 Description Reserved. Watt-Hour Accumulation Register for Phase A. Active power is accumulated over time in this read-only register. The AWATTHR register can hold a maximum of 0.52 seconds of active energy information with full-scale analog inputs before it overflows (see the Active Energy Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine how the active energy is processed from the six analog inputs. Watt-Hour Accumulation Register for Phase B. Watt-Hour Accumulation Register for Phase C. VAR-Hour Accumulation Register for Phase A. Reactive power is accumulated over time in this read-only register. The AVARHR register can hold a maximum of 0.52 seconds of reactive energy information with full-scale analog inputs before it overflows (see the Reactive Energy Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine how the reactive energy is processed from the six analog inputs. VAR-Hour Accumulation Register for Phase B. VAR-Hour Accumulation Register for Phase C. VA-Hour Accumulation Register for Phase A. Apparent power is accumulated over time in this read-only register. The AVAHR register can hold a maximum of 1.15 seconds of apparent energy information with full-scale analog inputs before it overflows (see the Apparent Energy Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine how the apparent energy is processed from the six analog inputs. VA-Hour Accumulation Register for Phase B. VA-Hour Accumulation Register for Phase C. Phase A Current Channel RMS Register. The register contains the rms component of the Phase A input of the current channel. The source is selected by data bits in the mode register. Phase B Current Channel RMS Register. Phase C Current Channel RMS Register. Phase A Voltage Channel RMS Register. Phase B Voltage Channel RMS Register. Rev. A | Page 58 of 68 ADE7758 Address [A6:A0] 0x0F 0x10 Name CVRMS FREQ R/W1 R R Length 24 12 Default Value 0 0 0x11 TEMP R 8 0 0x12 WFORM R 24 0 0x13 OPMODE R/W 8 4 0x14 MMODE R/W 8 0xFC 0x15 WAVMODE R/W 8 0 0x16 COMPMODE R/W 8 0x1C 0x17 LCYCMODE R/W 8 0x78 0x18 MASK R/W 24 0 0x19 STATUS R 24 0 0x1A RSTATUS R 24 0 0x1B ZXTOUT R/W 16 0xFFFF 0x1C LINECYC R/W 16 0xFFFF 0x1D SAGCYC R/W 8 0xFF 0x1E SAGLVL R/W 8 0 0x1F VPINTLVL R/W 8 0xFF 0x20 IPINTLVL R/W 8 0xFF 0x21 VPEAK R 8 0 0x22 IPEAK R 8 0 Description Phase C Voltage Channel RMS Register. Frequency of the Line Input Estimated by the Zero-Crossing Processing. It can also display the period of the line input. Bit 7 of the LCYCMODE register determines if the reading is frequency or period. Default is frequency. Data Bit 0 and Bit 1 of the MMODE register determine the voltage channel used for the frequency or period calculation. Temperature Register. This register contains the result of the latest temperature conversion. Please refer to the Temperature Measurement section for details on how to interpret the content of this register. Waveform Register. This register contains the digitized waveform of one of the six analog inputs or the digitized power waveform. The source is selected by Data Bit 0 to Bit 4 in the WAVMODE register. Operational Mode Register. This register defines the general configuration of the ADE7758 (see Table 14). Measurement Mode Register. This register defines the channel used for period and peak detection measurements (see Table 15). Waveform Mode Register. This register defines the channel and sampling frequency used in the waveform sampling mode (see Table 16). This register configures the formula applied for the energy and line active energy measurements (see Table 17). This register configures the Line Cycle Accumulation Mode for WATT-HR, VAR-HR, and VA-Hr (see Table 18). The IRQ Mask Register. It determines if an interrupt event generates an activelow output at the IRQ pin (see the ADE7758 Interrupts section). The IRQ Status Register. This register contains information regarding the source of the ADE7758 interrupts (see the ADE7758 Interrupts section). Same as the STATUS Register, except that its contents are reset to 0 (all flags cleared) after a read operation. Zero-Cross Timeout Register. If no zero crossing is detected within the time period specified by this register, the interrupt request line (IRQ) goes active low for the corresponding line voltage. The maximum timeout period is 2.3 seconds (see the Zero-Crossing Detection section). Line Cycle Register. The content of this register sets the number of half-line cycles that the active, reactive, and apparent energies are accumulated for in the line accumulation mode. SAG Line Cycle Register. This register specifies the number of consecutive halfline cycles where voltage channel input may fall below a threshold level. This register is common to the three line voltage SAG detection. The detection threshold is specified by the SAGLVL register (see the Line Voltage SAG Detection section). SAG Voltage Level. This register specifies the detection threshold for the SAG event. This register is common to all three phases’ line voltage SAG detections. See the description of SAGCYC register for details. Voltage Peak Level Interrupt Threshold Register. This register sets the level of the voltage peak detection. Bit 5 to Bit 7 of the MMODE register determine which phases are to be monitored. If the selected voltage phase exceeds this level, the PKV flag in the IRQ status register is set. Current Peak Level Interrupt Threshold Register. This register sets the level of the current peak detection. Bit 5 to Bit 7 of the MMODE register determine which phases to are be monitored. If the selected current phase exceeds this level, the PKI flag in the IRQ status register is set. Voltage Peak Register. This register contains the value of the peak voltage waveform that has occurred within a fixed number of half-line cycles. The number of half-line cycles is set by the LINECYC register. Current Peak Register. This register holds the value of the peak current waveform that has occurred within a fixed number of half-line cycles. The number of halfline cycles is set by the LINECYC register. Rev. A | Page 59 of 68 ADE7758 Address [A6:A0] 0x23 Name GAIN R/W1 R/W Length 8 Default Value 0 0x24 AVRMSGAIN R/W 12 0 0x25 0x26 0x27 BVRMSGAIN CVRMSGAIN AIGAIN R/W R/W R/W 12 12 12 0 0 0 0x28 0x29 0x2A BIGAIN CIGAIN AWG R/W R/W R/W 12 12 12 0 0 0 0x2B 0x2C 0x2D BWG CWG AVARG R/W R/W R/W 12 12 12 0 0 0 0x2E 0x2F 0x30 BVARG CVARG AVAG R/W R/W R/W 12 12 12 0 0 0 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F BVAG CVAG AVRMSOS BVRMSOS CVRMSOS AIRMSOS BIRMSOS CIRMSOS AWATTOS BWATTOS CWATTOS AVAROS BVAROS CVAROS APHCAL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 12 12 12 12 12 12 12 12 12 12 12 12 12 12 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x40 0x41 0x42 0x43 0x44 0x45 BPHCAL CPHCAL WDIV VARDIV VADIV APCFNUM R/W R/W R/W R/W R/W R/W 7 7 8 8 8 16 0 0 0 0 0 0 0x46 APCFDEN R/W 12 0x3F Description PGA Gain Register. This register is used to adjust the gain selection for the PGA in the current and voltage channels (see the Analog Inputs section). Phase A VRMS Gain Register. The range of the voltage rms calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. Phase B VRMS Gain Register. Phase C VRMS Gain Regsiter. Phase A Current Gain Register. The range of the current rms calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. Adjusting this register also scales the watt and VAR calculation. Not for use with Mode 0 of CONSEL, COMPMODE[0:1]. Phase B Current Gain Register. Phase C Current Gain Regsiter. Phase A Watt Gain Register. The range of the watt calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. Phase B Watt Gain Register. Phase C Watt Gain Register. Phase A VAR Gain Register.The range of the VAR calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. Phase B VAR Gain Register. Phase C VAR Gain Register. Phase A VA Gain Register. The range of the VA calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244% / LSB. Phase B VA Gain Register. Phase C VA Gain Register. Phase A Voltage RMS Offset Correction Register. Phase B Voltage RMS Offset Correction Register. Phase C Voltage RMS Offset Correction Register. Phase A Current RMS Offset Correction Register. Phase B Current RMS Offset Correction Register. Phase C Current RMS Offset Correction Register. Phase A Watt Offset Calibration Register. Phase B Watt Offset Calibration Register. Phase C Watt Offset Calibration Register. Phase A VAR Offset Calibration Register. Phase B VAR Offset Calibration Register. Phase C VAR Offset Calibration Register. Phase A Phase Calibration Register. The phase relationship between the current and voltage channel can be adjusted by writing to this signed 7-bit register (see the Phase Compensation section). Phase B Phase Calibration Register. Phase C Phase Calibration Register. Active Energy Register Divider. Reactive Energy Register Divider. Apparent Energy Register Divider. Active Power CF Scaling Numerator Register. The content of this register is used in the numerator of the APCF output scaling. Bits [15:13] indicate reverse polarity active power measurement for Phase A, Phase B, and Phase C in order, i.e., Bit 15 is Phase A, Bit 14 is Phase B, etc. Active Power CF Scaling Denominator Register. The content of this register is used in the denominator of the APCF output scaling. Rev. A | Page 60 of 68 ADE7758 Address [A6:A0] 0x47 Name VARCFNUM R/W1 R/W Length 16 Default Value 0 0x48 VARCFDEN R/W 12 0x3F 0x49 to 0x7D 0x7E RESERVED − − − CHKSUM R 8 − 0x7F VERSION R 8 − 1 Description Reactive Power CF Scaling Numerator Register. The content of this register is used in the numerator of the VARCF output scaling. Bits [15:13] indicate reverse polarity reactive power measurement for Phase A, Phase B, and Phase C in order, i.e., Bit 15 is Phase A, Bit 14 is Phase B, and so on. Reactive Power CF Scaling Denominator Register. The content of this register is used in the denominator of the VARCF output scaling. Reserved. Checksum Register. The content of this register represents the sum of all the ones in the last register read from the SPI port. Version of the Die. R/W: Read/write capability of the register. R: Read-only register. R/W: Register that can be both read and written. OPERATIONAL MODE REGISTER (0x13) The general configuration of the ADE7758 is defined by writing to the OPMODE register. Table 14 summarizes the functionality of each bit in the OPMODE register. Table 14. OPMODE Register Bit Location 0 1 2 3 to 5 Bit Mnemonic DISHPF DISLPF DISCF DISMOD Default Value 0 0 1 0 6 SWRST 0 7 RESERVED 0 Description The HPFs (high-pass filter) in all current channel inputs are disabled when this bit is set. The LPFs (low-pass filter) in all current channel inputs are disabled when this bit is set. The frequency outputs APCF and VARCF are disabled when this bit is set. By setting these bits, ADE7758’s ADCs can be turned off. In normal operation, these bits should be left at Logic 0. DISMOD[2:0] Description 0 0 0 Normal operation. 1 0 0 Redirect the voltage inputs to the signal paths for the current channels and the current inputs to the signal paths for the voltage channels. 0 0 1 Switch off only the current channel ADCs. 1 0 1 Switch off current channel ADCs and redirect the current input signals to the voltage channel signal paths. 0 1 0 Switch off only the voltage channel ADCs. 1 1 0 Switch off voltage channel ADCs and redirect the voltage input signals to the current channel signal paths. 0 1 1 Put the ADE7758 in sleep mode. 1 1 1 Put the ADE7758 in power-down mode. Software Chip Reset. A data transfer to the ADE7758 should not take place for at least 18 µs after a software reset. This should be left at 0. Rev. A | Page 61 of 68 ADE7758 MEASUREMENT MODE REGISTER (0x14) The configuration of the PERIOD and peak measurements made by the ADE7758 is defined by writing to the MMODE register. Table 15 summarizes the functionality of each bit in the MMODE register. Table 15. MMODE Register Bit Location 0 to 1 Bit Mnemonic FREQSEL Default Value 0 2 to 4 PEAKSEL 7 5 to 7 PKIRQSEL 7 Description These bits are used to select the source of the measurement of the voltage line frequency. FREQSEL1 FREQSEL0 Source 0 0 Phase A 0 1 Phase B 1 0 Phase C 1 1 Reserved These bits select the phases used for the voltage and current peak registers. Setting Bit 2 switches the IPEAK and VPEAK registers to hold the absolute values of the largest current and voltage waveform (over a fixed number of half-line cycles) from Phase A. The number of half-line cycles is determined by the content of the LINECYC register. At the end of the LINECYC number of half-line cycles, the content of the registers is replaced with the new peak values. Similarly, setting Bit 3 turns on the peak detection for Phase B and Bit 4 is for Phase C. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, i.e., the voltage and current peak are independently processed (see the Peak Current Detection section). These bits select the phases used for the peak interrupt detection. Setting Bit 5 switches on the monitoring of the absolute current and voltage waveform to Phase A. Similarly, setting Bit 6 turns on the waveform detection for Phase B and Bit 7 is for Phase C. Note that more than one bit can be set for detection on multiple phases. If the absolute values of the voltage or current waveform samples in the selected phases exceeds the preset level specified in the PKVLVL or PKILVL registers, the corresponding bit(s) in the STATUS registers are set (see the Peak Current Detection section). WAVEFORM MODE REGISTER (0x15) The waveform sampling mode of the ADE7758 is defined by writing to the WAVMODE register. Table 16 summarizes the functionality of each bit in the WAVMODE register. Table 16. WAVMODE Register Bit Location 0 to 1 Bit Mnemonic PHSEL Default Value 0 2 to 4 WAVSEL 0 5 to 6 DTRT 0 7 VACF 0 Description These bits are used to select the phase of the waveform sample. PHSEL[1:0] Source 0 0 Phase A 0 1 Phase B 1 0 Phase C 1 1 Reserved These bits are used to select the type of waveform. WAVSEL[2:0] Source 0 0 0 Current 0 0 1 Voltage 0 1 0 Active Power Multiplier Output 0 1 1 Reactive Power Multiplier Output 1 0 0 VA Multiplier Output -OthersReserved These bits are used to select the data rate. DTRT[1:0] Update Rate 0 0 26.0 kSPS (CLKIN/3/128) 0 1 13.0 kSPS (CLKIN/3/256) 1 0 6.5 kSPS (CLKIN/3/512) 1 1 3.3 kSPS (CLKIN/3/1024) Setting this bit to Logic 1 switches the VARCF output pin to an output frequency that is proportional to the total apparent power (VA). In the default state, Logic 0, the VARCF pin outputs a frequency proportional to the total reactive power (VAR). Rev. A | Page 62 of 68 ADE7758 COMPUTATIONAL MODE REGISTER (0x16) The computational method of the ADE7758 is defined by writing to the COMPMODE register. Table 17 summarizes the functionality of each bit in the COMPMODE register. Table 17. COMPMODE Register Bit Location 0 to 1 Bit Mnemonic CONSEL Default Value 0 2 to 4 TERMSEL 7 5 ABS 0 6 SAVAR 0 7 NOLOAD 0 Description These bits are used to select the input to the energy accumulation registers. Registers CONSEL[1, 0] = 00 CONSEL[1, 0] = 01 AWATTHR VA × IA VA × (IA – IB) BWATTHR VB × IB 0 CWATTHR VC × IC VC × (IC – IB) CONSEL[1, 0] = 10 VA × (IA–IB) 0 VC × IC AVARHR BVARHR CVARHR VA × IA VB × IB VC × IC VA × (IA – IB) 0 VC × (IC – IB) VA × (IA–IB) 0 VC × IC AVAHR BVAHR CVAHR VARMS × IARMS VBRMS × IBRMS VCRMS × ICRMS VARMS × IARMS (VARMS + VCRMS)/2 × IBRMS VCRMS × ICRMS VARMS × ARMS VARMS × IBRMS VCRMS × ICRMS CONSEL[1, 1] is reserved. Note: IA, IB, and IC are IA, IB, and IC phase shifted by –90°, respectively. These bits are used to select the phases to be included in the APCF and VARCF pulse outputs. Setting Bit 2 enables Phase A (the inputs to AWATTHR and AVARHR registers) to be included. Bit 3 and Bit 4 are for Phase B and Phase C, respectively. Setting all three bits enables the sum of all three phases to be included in the frequency outputs (see the Active Power Frequency Output and the Reactive Power Frequency Output sections). Setting this bit places the APCF output pin in absolute only mode. Namely, the APCF output frequency is proportional to the sum of the absolute values of the watt-hour accumulation registers (AWATTHR, BWATTHR, and CWATTHR). Note that this bit only affects the APCF pin and has no effect on the content of the corresponding registers. Setting this bit places the VARCF output pin in the signed adjusted mode. Namely, the VARCF output frequency are proportional to the sign-adjusted sum of the VAR-hour accumulation registers (AVARHR, BVARHR, and CVARHR). The sign of the VAR is determined from the sign of the watt calculation from the corresponding phase, i.e., the sign of the VAR is flipped if the sign of the watt is negative, and if the watt is positive, there is no change to the sign of the VAR. Note that this bit only affects the VARCF pin and has no effect on the content of the corresponding registers. Setting this bit activates the no-load threshold in the ADE7758. Rev. A | Page 63 of 68 ADE7758 LINE CYCLE ACCUMULATION MODE REGISTER (0x17) The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register. Table 18 summarizes the functionality of each bit in the LCYCMODE register. Table 18. LCYCMODE Register Bit Location Bit Mnemonic Default Value 0 LWATT 0 1 LVAR 0 2 LVA 0 3 to 5 ZXSEL 7 6 RSTREAD 1 7 FREQSEL 0 Description Setting this bit places the watt-hour accumulation registers (AWATTHR, BWATTHR, and CWATTHR registers) into line-cycle accumulation mode. Setting this bit places the VAR-hour accumulation registers (AVARHR, BVARHR, and CVARHR registers) into line-cycle accumulation mode. Setting this bit places the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR registers) into line-cycle accumulation mode. These bits select the phases used for counting the number of zero crossings in the line-cycle accumulation mode. Bit 3, Bit 4, and Bit 5 select Phase A, Phase B, and Phase C, respectively. More than one phase can be selected for the zero-crossing detection, and the accumulation time is shortened accordingly. Setting this bit enables the read-with-reset for all the WATTHR, VARHR, and VAHR registers for all three phases, i.e., a read to those registers resets the registers to 0 after the content of the registers have been read. This bit should be set to Logic 0 when the LWATT, LVAR, or LVA bits are set to Logic 1. Setting this bit causes the FREQ (0x10) register to display the period, instead of the frequency of the line input. Rev. A | Page 64 of 68 ADE7758 INTERRUPT MASK REGISTER (0x18) When an interrupt event occurs in the ADE7758, the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the MASK register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. Table 19 describes the function of each bit in the interrupt mask register. Table 19. Function of Each Bit in the Interrupt Mask Register Bit Location Interrupt Flag Default Value 0 AEHF 0 1 REHF 0 2 VAEHF 0 3 4 5 6 7 8 SAGA SAGB SAGC ZXTOA ZXTOB ZXTOC 0 0 0 0 0 0 9 ZXA 0 10 ZXB 0 11 ZXC 0 12 13 LENERGY RESERVED 0 0 14 PKV 0 15 PKI 0 16 WFSM 0 17 REVPAP 0 18 REVPRP 0 19 SEQERR 0 Description Enables an interrupt when there is a change in Bit 14 of any one of the three WATTHR registers, i.e., the WATTHR register is half full. Enables an interrupt when there is a change in Bit 14 of any one of the three VARHR registers, i.e., the VARHR register is half full. Enables an interrupt when there is a 0 to 1 transition in the MSB of any one of the three VAHR registers, i.e., the VAHR register is half full. Enables an interrupt when there is a SAG on the line voltage of the Phase A. Enables an interrupt when there is a SAG on the line voltage of the Phase B. Enables an interrupt when there is a SAG on the line voltage of the Phase C. Enables an interrupt when there is a zero-crossing timeout detection on Phase A. Enables an interrupt when there is a zero-crossing timeout detection on Phase B. Enables an interrupt when there is a zero-crossing timeout detection on Phase C. Enables an interrupt when there is a zero crossing in the voltage channel of Phase A (see the Zero-Crossing Detection section). Enables an interrupt when there is a zero crossing in the voltage channel of Phase B (see the Zero-Crossing Detection section). Enables an interrupt when there is a zero crossing in the voltage channel of Phase C (see the Zero-Crossing Detection section). Enables an interrupt when the energy accumulations over LINECYC are finished. Reserved. Enables an interrupt when the voltage input selected in the MMODE register is above the value in the PKVLVL register. Enables an interrupt when the current input selected in the MMODE register is above the value in the PKILVL register. Enables an interrupt when data is present in the WAVEMODE register. Enables an interrupt when there is a sign change in the watt calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. Enables an interrupt when there is a sign change in the VAR calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. Enables an interrupt when the zero crossing from Phase A is not followed by the zero crossing of Phase C but with that of Phase B. Rev. A | Page 65 of 68 ADE7758 INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is set logic high. The IRQ pin goes active low if the corresponding bit in the interrupt mask register is set logic high. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the source of the interrupt. All the interrupts in the interrupt status register stay at their logic high state after an event occurs. The state of the interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read. Table 20. Interrupt Status Register Bit Location Interrupt Flag Default Value 0 AEHF 0 1 REHF 0 2 VAEHF 0 3 4 5 SAGA SAGB SAGC 0 0 0 6 ZXTOA 0 7 ZXTOB 0 8 ZXTOC 0 9 10 11 ZXA ZXB ZXC 0 0 0 12 LENERGY 0 13 RESET 1 14 PKV 0 15 PKI 0 16 WFSM 0 17 REVPAP 0 18 REVPRP 0 19 SEQERR 0 Event Description Indicates that an interrupt was caused by a change in Bit 14 among any one of the three WATTHR registers, i.e., the WATTHR register is half full. Indicates that an interrupt was caused by a change in Bit 14 among any one of the three VARHR registers, i.e., the VARHR register is half full. Indicates that an interrupt was caused by a 0-to-1 transition in Bit 15 among any one of the three VAHR registers, i.e., the VAHR register is half full. Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A. Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B. Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C. Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A. Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B. Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C. Indicates a detection of a rising edge zero crossing in the voltage channel of the Phase A. Indicates a detection of a rising edge zero crossing in the voltage channel of the Phase B. Indicates a detection of a rising edge zero crossing in the voltage channel of the Phase C. In line energy accumulation, it indicates the end of an integration over an integer number of half-line cycles (LINECYC), see the Calibration section. Indicates that the 5 V power supply is below 4 V. Enables a software reset of the ADE7758 and sets the registers back to their default values. This bit in the STATUS or RSTATUS register is logic high for only one clock cycle after a reset event. Indicates that an interrupt was caused when the selected voltage input is above the value in the PKVLVL register. Indicates that an interrupt was caused when the selected current input is above the value in the PKILVL register. Indicates that new data is present in the waveform register. Indicates that an interrupt was caused by a sign change in the watt calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. Indicates that an interrupt was caused by a sign change in the VAR calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. Indicates that an interrupt was caused by a zero crossing from Phase A not followed by the zero crossing of Phase C but by that of Phase B. Rev. A | Page 66 of 68 ADE7758 OUTLINE DIMENSIONS 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 1 12 10.65 (0.4193) 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) × 45° 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 1.27 (0.0500) BSC 0.10 0.51 (0.020) 0.31 (0.012) 8° SEATING 0° 0.33 (0.0130) PLANE 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 94. 24-Lead Wide Body Small Outline Package [SOIC] (RW-24) Dimensions shown in millimeters (inches) ORDERING GUIDE Model ADE7758ARW ADE7758ARWRL ADE7758ARWZ1 ADE7758ARWZRL1 EVAL-ADE7758EB 1 Temperature Range −40°C to + 85°C −40°C to + 85°C −40°C to + 85°C −40°C to + 85°C Description 24-Lead Wide Body SOIC 24-Lead Wide Body SOIC 24-Lead Wide Body SOIC 24-Lead Wide Body SOIC Evaluation Board Z = Pb-free part. Rev. A | Page 67 of 68 Package Option RW-24 RW-24 (13” Reel) RW-24 RW-24 (13” Reel) ADE7758 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04443–0–9/04(A) Rev. A | Page 68 of 68