ENPIRION EP5352Q 500/600/800ma synchronous buck regulators with integrated inductor Datasheet

EP5352Q/EP5362Q/EP5382Q
500/600/800mA Synchronous Buck Regulators
With Integrated Inductor
RoHS Compliant
VIN
Product Overview
UVLO
Thermal Limit
Current Limit
ENABLE
Soft Start
P-Drive
(-)
Logic
VOUT
PWM
Comp
(+)
N-Drive
GND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Switch
Error
Amp
VFB
(+)
DAC
VREF
Voltage
Select
The Ultra-Low-Profile EP53X2Q product family is
targeted to applications where board area and
profile are critical. EP53X2Q is a complete power
conversion solution requiring only two low cost
ceramic MLCC caps.
Inductor, MOSFETS,
PWM, and compensation are integrated into a
tiny 5mm x 4mm x 1.1mm QFN package. The
EP53x2Q family is engineered to simplify design
and to minimize layout constraints.
High
switching frequency and internal type III
compensation provides superior transient
response. With a 1.1 mm profile, the EP53x2 is
perfect for space and height limited applications.
A 3-pin VID output voltage select scheme
provides seven pre-programmed output voltages
along with an option for external resistor divider.
Output voltage can be programmed on-the-fly to
provide fast, dynamic voltage scaling.
Package Boundry
VS0 VS1 VS2
Product Highlights
• Revolutionary integrated inductor
• Very small solution foot print*
• Fully RoHS compliant; MSL 3 260°C reflow
• Only two low cost components required
• 5mm x 4mm x1.1mm QFN package
• Wide 2.4V to 5.5V input range
• 500, 600, 800 mA output current versions
• Less than 1 μA standby current
• 4 MHz switching frequency
• Fast transient response
• Very low ripple voltage; 5mVp-p typical
• 3 Pin VID Output Voltage select
• External divider option
• Dynamically adjustable output
• Designed for Low noise/EMI
• Short circuit, UVLO, and thermal protection
Typical Application Circuit
VSense
ENABLE
VIN
Vin
2.2uF
Voltage
Select
VOUT
Vout
10μF
VFB
VS0
VS1
VS2
GND
Figure 1. Typical application circuit.
Applications
•
•
•
•
•
•
Area constrained applications
Mobile multimedia, smartphone & PDA
Mobile and Cellular platforms
VoIP and Video phones
Personal Media Players
FPGA, DSP, IO & Peripherals
*Optimized PCB layout Gerber files downloadable from the Enpirion website to assure first pass design success.
03132
4/28/2009
Rev:B
EP5382Q/EP5362Q/EP5352Q
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
VIN
Input Supply Voltage
Voltages on: ENABLE, VSENSE, VS0-VS2
Voltage on: VFB
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
TSTG
MIN
-0.3
-0.3
-0.3
-65
MAX
7.0
VIN + 0.3
2.7
150
260
2000
UNITS
V
V
V
°C
°C
V
Recommended Operating Conditions
PARAMETER
Input Voltage Range
Output Voltage Range
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL
VIN
VOUT
TA
TJ
MIN
2.4
0.6
-40
-40
MAX
5.5
VIN-0.45
+85
+125
UNITS
V
V
°C
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Shutdown
Thermal Shutdown Hysteresis
SYMBOL
θJA
θJC
TJ-TP
TYP
65
15
+150
15
UNITS
°C/W
°C/W
°C
°C
Electrical Characteristics
NOTE: TA = 25°C unless otherwise noted. Typical values are at VIN = 3.6V.
EP5352QI, EP5362QI: CIN = 2.2μF, COUT=10uF.
EP5382QI: CIN = 4.7μF, COUT=10uF.
PARAMETER
Operating Input Voltage
Under Voltage Lockout
UVLO Hysteresis
SYMBOL
VIN
VUVLO
VOUT Initial Accuracy
VOUT
VOUT Variation for all
Causes
VOUT
Feedback Pin Voltage
VFB
Feedback Pin Input Current
IFB
Feedback Pin Voltage
VFB
Dynamic Voltage Slew Rate
Vslew
©Enpirion 2009 all rights reserved, E&OE
03132
TEST CONDITIONS
MIN
2.4
MAX
5.5
2.3
UNITS
V
V
V
-2.0
+2.0
%
-3.0
+3.0
%
VIN going low to high
2.4V ≤ VIN ≤ 5.5V, ILOAD = 100mA;
TA = 25C
2.4V ≤ VIN ≤ 5.5V, ILOAD = 0 - 1A,
TA = -40°C to +85°C
2.4V ≤ VIN ≤ 5.5V, ILOAD = 100mA
VSO=VS1=VS2=1
TYP
2.2
0.145
0.591
0.603
0.615
1
2.4V ≤ VIN ≤ 5.5V, ILOAD = 0-800mA,
TA = -40°C to +85°C
VSO=VS1=VS2=1
0.585
2
4/28/2009
nA
0.603
3
V
0.621
V
mV/μS
www.enpirion.com
Rev:B
EP5382Q/EP5362Q/EP5352Q
PARAMETER
Continuous Output Current
EP5352QI
Continuous Output Current
EP5362QI
Continuous Output Current
EP5382QI
Shut-Down Current
Quiescent Current
PFET OCP Threshold
VS0-VS1 Voltage
Threshold
VS0-VS2 Pin Input Current
SYMBOL
TYP
MAX
UNITS
EP5352Q
500
mA
IOUT
EP5362Q
600
mA
IOUT
EP5382Q
800
mA
ISD
Enable = Low
No switching
2.4V ≤ VIN ≤ 5.5V,
0.6V ≤ VOUT ≤ VIN – 0.6V
Pin = Low
Pin = High
ILIM
1.4
IEN
FOSC
RDS(ON)
RDS(ON)
Tss
0.75
800
μA
μA
2
A
0.0
1.4
IVSX
©Enpirion 2009 all rights reserved, E&OE
03132
MIN
IOUT
Enable Voltage Threshold
Enable Pin Input Current
Operating Frequency
PFET On Resistance
NFET On Resistance
Internal Inductor DCR
Soft-Start Operation
Time to 90% Vout
TEST CONDITIONS
0.4
VIN
1
Logic Low
Logic High
VIN = 3.6V
nA
0.0
1.4
Vout = 3.3V
3
4/28/2009
V
0.2
VIN
V
2
4
340
270
.110
μA
MHz
mΩ
mΩ
Ω
1
mS
www.enpirion.com
Rev:B
EP5382Q/EP5362Q/EP5352Q
VFB
VIN
2
15
VSENSE
GND
3
14
GND
4
VOUT
VOUT
VS0
ENABLE
19
20
VFB
16
VSENSE
15
NC
NC
14
3
GND
13
NC
NC
13
4
GND
5
12
NC
NC
12
5
VOUT
6
11
NC
NC
11
6
VOUT
8
7
NC
VOUT
NC
NC
10
NC
9
9
NC
NC
8
VOUT
10
7
VIN (Pin 1,2): Input voltage pin. Supplies power
to the IC. VIN can range from 2.4V to 5.5V.
1
VIN
2
VIN
VFB (Pin 16): Feed back pin for external divider
option. When using the external divider option
(VS0=VS1=VS2= high) connect this pin to the
center of the external divider. Set the divider
such that VFB = 0.603V.
Input GND: (Pin 3): Input power ground.
Connect this pin to the ground terminal of the
input capacitor.
Refer to
Layout
Recommendations for further details.
VS0,VS1,VS2 (Pin 17,18,19): Output voltage
select. VS0=pin19, VS1=pin18, VS2=pin17.
Selects one of seven preset output voltages or
choose external divider by connecting pins to
logic high or low. Logic low is defined as VLOW
≤ 0.4V. Logic high is defined as VHIGH ≥ 1.4V.
Any level between these two values is
indeterminate. (refer to section on output
voltage select for more detail).
Output GND: (Pin 4): Power ground. The
output filter capacitor should be connected to
this pin. Refer to Layout recommendations for
further detail.
VOUT (Pin 5,6,7): Regulated output voltage.
NC (Pin 8,9,10,11,12,13,14): These pins
should not be electrically connected to each
other or to any external signal, voltage, or
ground. One or more of these pins may be
connected internally.
ENABLE (Pin 20): Output enable. Enable =
logic high, disable = logic low. Logic low is
defined as VLOW ≤ 0.2V. Logic high is defined
as VHIGH ≥ 1.4V. Any level between these two
values is indeterminate.
VSENSE (Pin 15): Sense pin for output voltage
regulation.
Connect VSENSE to the output
voltage rail as close to the terminal of the
output filter capacitor as possible.
©Enpirion 2009 all rights reserved, E&OE
Thermal
Pad
Figure 3. Pin description, bottom view.
Figure 2. Pin description, top view.
03132
VS1
VS2
17
16
18
VS1
18
1
VS2
VS0
19
VIN
17
ENABLE
20
Pin Description
Thermal Pad. Thermal pad to remove heat
from package. Connect to surface ground pad
and PCB internal ground plane.
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Rev:B
EP5382Q/EP5362Q/EP5352Q
Functional Block Diagram
VIN
UVLO
Thermal Limit
Current Limit
ENABLE
Soft Start
P-Drive
(-)
Logic
VOUT
PWM
Comp
(+)
N-Drive
GND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Switch
Error
Amp
VFB
(+)
DAC
Voltage
Select
VREF
Package Boundry
VS0 VS1 VS2
Figure 4. Functional block diagram.
©Enpirion 2009 all rights reserved, E&OE
03132
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Rev:B
EP5382Q/EP5362Q/EP5352Q
Typical Performance Characteristics
Efficiency vs Output Current
Efficiency vs Output Current
Efficiency -%
95
100
90
95
85
90
85
Efficiency -%
80
V OUT = 3.3V
75
V OUT = 3.0V
70
V OUT = 2.7V
65
V OUT = 2.5V
80
V OUT = 3.3V
75
V OUT = 3.0V
70
V OUT = 2.7V
V OUT = 2.5V
65
V OUT = 1.8V
60
V OUT = 1.8V
60
55
VIN = 5.0V
55
50
50
150
250
350
450
V IN = 3.6V
50
550
50
150
Load Current (mA)
250
350
450
550
Load Current (mA)
Start up Waveform
Efficiency vs Output Current
100
95
V out
1V/Div
90
Efficiency -%
85
80
75
70
V OUT = 3.0V
V OUT = 2.7V
65
V OUT = 2.5V
60
Enable
2V/Div
V OUT = 1.8V
55
V OUT = 1.2V
VIN = 3.3V
50
50
150
250
350
450
VIN = 5.0V
VOUT = 3.3V
550
Load Current (mA)
Transient Response
Transient Response
Vout
50mV/Div
Vout
50mV/Div
ILoad
500mA/Div
ILoad
500mA/Div
VIN = 3.3V
20μs/Div
VOUT = 1.8V
Iload = 100mA to 800mA
VIN = 5.0V
20μs/Div
VOUT = 3.3V
Iload = 100mA to 800mA
Output Ripple
V out
10mV/Div
Output Ripple
V out
10mV/Div
VIN = 3.6V
200ns/Div
VOUT = 3.3V
Output Cap = 2 x 10 μF 0805
V IN = 3.6V
200ns/Div
V OUT = 3 .3V
Output Cap = 10 μF 0805
©Enpirion 2009 all rights reserved, E&OE
03132
200μs/Div
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Rev:B
EP5382Q/EP5362Q/EP5352Q
Detailed Description
Protection features include under-voltage lockout (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Functional Overview
The EP53x2Q family is a complete DCDC
converter solution requiring only two low cost
MLCC capacitors. MOSFET switches, PWM
controller, Gate-drive, compensation, and
inductor are integrated into the tiny 5mm x
4mm x 1.1mm package to provide the smallest
footprint possible while maintaining high
efficiency and high performance. The converter
uses voltage mode control to provide the
simplest implementation and high noise
immunity. The device operates at a 4 MHz
switching frequency. The high switching
frequency allows for a wide control loop
bandwidth
providing
excellent
transient
performance. The 4 MHz switching frequency
enables the use of very small components
making possible this unprecedented level of
integration.
Integrated Inductor
Enpirion has introduced the world’s first
product family featuring integrated inductors.
The EP53x2Q family utilizes a low loss, planar
construction inductor. The use of an internal
inductor localizes the noises associated with
the output loop currents. The inherent shielding
and compact construction of the integrated
inductor reduces the radiated noise that
couples into the traces of the circuit board.
Further, the package layout is optimized to
reduce the electrical path length for the AC
ripple currents that are a major source of
radiated emissions from DCDC converters.
The integrated inductor significantly reduces
parasitic effects that can harm loop stability,
and makes layout very simple.
Enpirion’s
proprietary
power
MOSFET
technology provides very low switching loss at
frequencies of 4 MHz and higher, allowing for
the use of very small internal components, and
very wide control loop bandwidth. Unique
magnetic design allows for integration of the
inductor into the very low profile 1.1mm
package. Integration of the inductor virtually
eliminates the design/layout issues normally
associated
with
switch-mode
DCDC
converters. All of this enables much easier
and faster integration into various applications
to meet demanding EMI requirements.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor. The soft start ramp rate is nominally
3.3mV/μSec.
Output voltage is chosen from seven preset
values via a three pin VID voltage select
scheme. An external divider option enables
the selection of any voltage in the 0.6 to VIN Vdropout. This reduces the number of
components that must be qualified and
reduces inventory problems. The VID pins can
be toggled on the fly to implement glitch free
dynamic voltage scaling.
©Enpirion 2009 all rights reserved, E&OE
03132
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense PMOSFET which is compared to a reference
current. When this level is exceeded the PFET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for a period of 1mS and then a normal soft start
is initiated. If the over current condition still
persists, this cycle will repeat in a “hiccup”
mode.
7
4/28/2009
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Rev:B
EP5382Q/EP5362Q/EP5352Q
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be less than 1 uA. The ENABLE pin must
not be left floating.
Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
Application Information
Output Voltage Select
Table 1. Voltage select settings.
To provide the highest degree of flexibility in
choosing output voltage, the EP53x2Q family
uses a 3 pin VID, or Voltage ID, output voltage
select arrangement. This allows the designer
to choose one of seven preset voltages, or to
use an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output voltage selected.
VS2
0
0
0
0
1
1
1
1
03132
VS0
0
1
0
1
0
1
0
1
VOUT
3.3
2.5
2.8
1.2
3.0
1.8
2.7
External
External Voltage Divider
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels. A logic “1” indicates a connection to VIN
or to a “high” logic voltage level. A logic “0”
indicates a connection to ground or to a “low”
logic voltage level. These pins can be either
hardwired to VIN or GND or alternatively can be
driven by standard logic levels. Logic low is
defined as VLOW ≤ 0.4V. Logic high is defined
as VHIGH ≥ 1.4V. Any level between these two
values is indeterminate. These pins must not
be left floating.
©Enpirion 2009 all rights reserved, E&OE
VS1
0
0
1
1
0
0
1
1
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to VIN or logic “high”.
The EP53x2Q uses a separate feedback pin,
VFB, when using the external divider. VSENSE
must be connected to VOUT as indicated in
Figure 5.
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Rev:B
VSense
ENABLE
VIN
Vin
VOUT
Vout
2.2uF
4.7uF
EP5382Q/EP5362Q/EP5352Q
formulation.
Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias, and with temperature, and are not
suitable for switch-mode DC-DC converter
input and output filter applications.
Ra
10μF
VFB
VS0
VS1
Rb
VS2
The output capacitance requirement is a
minimum of 10uF.
The control loop is
designed to be stable with up to 60uF of total
output
capacitance
without
requiring
modification of the control loop. Capacitance
above the 10uF minimum should be added if
the transient performance is not sufficient using
the 10uF. Enpirion recommends a low ESR
MLCC type capacitor be used. The output
capacitor must use a X5R or X7R or equivalent
dielectric formulation.
Y5V or equivalent
dielectric formulations lose capacitance with
frequency, bias, and temperature and are not
suitable for switch-mode DC-DC converter
input and output filter applications.
GND
Figure 5. External Divider.
The output voltage is selected by the following
formula:
VOUT = 0.603V (1 +
Ra
Rb
)
Ra must be chosen as 200KΩ to maintain loop
gain. Then Rb is given as:
Rb =
1.2 x105
Ω
VOUT − 0.603
Cin
Manufacturer
Part #
Murata
GRM21BR71A225KA01L
GRM31MR71A225KA01L
GRM21BR70J225KA01L
Dynamically Adjustable Output
Panasonic
The EP53x2Q are designed to allow for
dynamic switching between the predefined VID
voltage levels The inter-voltage slew rate is
optimized to prevent excess undershoot or
overshoot as the output voltage levels
transition. The slew rate is identical to the softstart slew rate of 3.3mV/uS.
Taiyo Yuden
Panasonic
Input and Output Capacitors
Taiyo Yuden
The input capacitance requirement is as
follows:
EP5352Q, EP5362Q = 2.2uF
EP5382Q = 4.7uF
Enpirion recommends that a low ESR MLCC
capacitor be used. The input capacitor must
use a X5R or X7R or equivalent dielectric
©Enpirion 2009 all rights reserved, E&OE
03132
9
4/28/2009
10V
6.3V
LMK107BJ225KA-T
LMK212BJ225KG-T
Value
4.7uF
WVDC
10V
Case Size
0805
1206
0805
1206
6.3V
10V
6.3V
Value
10uF
0805
1206
0805
0603
0805
10V
LMK212BJ475KG-T
LMK316BJ475KD-T
JMK212BJ475KD-T
Case Size
0805
1206
0805
10V
6.3V
ECJ-2FB1A475K
ECJ-3YB1A475K
ECJ-2FB0J475K
ECJ-3YB0J475K
Cout
Manufacturer
Part #
Murata
GRM219R60J106KE19D
GRM319R60J106KE01D
WVDC
10V
6.3V
ECJ-2FB1A225K
ECJ-3YB1A225K
ECJ-2YB0J225K
Cin
Manufacturer Part #
Murata
GRM219R61A475KE19D
GRM319R61A475KA01D
GRM219R60J475KE01D
GRM31MR60J475KA01L
Dynamic transitioning between internal VID
settings and the external divider is not allowed.
Value
2.2uF
0805
1206
0805
1206
0805
1206
0805
WVDC
6.3V
Case Size
0805
1206
Panasonic
ECJ-2FB0J106K
ECJ-3YB0J106K
6.3V
0805
1206
Taiyo Yuden
JMK212BJ106KD-T
JMK316BJ106KF-T
6.3V
0805
1206
www.enpirion.com
Rev:B
EP5382Q/EP5362Q/EP5352Q
LAYOUT CONSIDERATIONS*
*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success
Recommendation 1: Input and output filter capacitors should be placed as close to the EP53x2QI
package as possible to reduce EMI from input and output loop AC currents. This reduces the
physical area of the Input and Output AC current loops.
Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the
Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground
pad for the input and output filter capacitors should be isolated ground islands and should be
connected to system ground as indicated in recommendation 3 and recommendation 5.
Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect
ground terminals of the Input capacitor and the output capacitor to the system ground plane. This
provides a low inductance path for the high-frequency AC currents, thereby reducing ripple and
suppressing EMI (see Fig. 5, Fig. 6, and Fig. 7).
Recommendation 4: The large thermal pad underneath the component must be connected to the
system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill
size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for
heat dissipation from the converter.
Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be
the first layer immediately below the surface layer (PCB layer 2). This ground plane should be
continuous and un-interrupted below the converter and the input and output capacitors that carry
large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an
uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the
EN5312QI and its input and output capacitors. The vias that connect the input and output capacitor
grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as
well.
Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or
control lines underneath the converter package.
Figure 6 shows an example schematic for the EP53x2Q using the internal voltage select. In this
example, the device is set to a VOUT of 1.2V (VS2=0, VS1=1, VS0=1).
©Enpirion 2009 all rights reserved, E&OE
03132
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Rev:B
VS2
VFB
VSENSE
NC
NC
NC
NC
16
15
14
13
12
11
EP5382Q/EP5362Q/EP5352Q
17
9
NC
8
NC
7
VOUT
6
5
VOUT
4
GND
NC
VOUT
3
GND
AGND
20
2
ENABLE
1
VS0
19
VIN
18
VIN
VS1
10
VOUT
VIN
4.7uF/2.2uF
10μF
(see layout recommendation 3)
Figure 6. Example application, Vout=1.2V.
10
NC
9
NC
8
NC
VSENSE
NC
NC
NC
NC
15
14
13
12
11
VFB
Ra=200K
6
5
VOUT
Rb=60K
VOUT
VOUT
VIN
4
7
GND
20
3
ENABLE
2
19
VIN
VS0
GND
VS1
18
AGND
17
1
VS2
16
Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The
resistor values are chosen to give an output voltage of 2.6V.
VOUT
VIN
4.7uF
10μF
(see layout recommendation 3)
Figure 7. Schematic showing the use of external divider option, Vout = 2.6V.
Figure 8 shows two example board layouts. Note the placement of the input and output capacitors.
They are placed close to the device to minimize the physical area of the AC current loops. Note the
placement of the vias per recommendation 3.
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EP5382Q/EP5362Q/EP5352Q
Package
Outline
Thermal Vias to Ground Plane
CIN
COUT
Vias to Ground Plane
Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter
capacitor local grounds, and thermal pad, to PCB system ground.
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom Of Package
Enpirion has developed a break-through in package technology that utilizes the lead frame as part of
the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced
electrical lead resistance, and in overall foot print. However, it does require some special
considerations.
As part of the package assembly process, lead frame construction requires that for mechanical
support, some of the lead-frame metal be exposed at the point where wire-bond or internal passives
are attached. This results in several small pads being exposed on the bottom of the package.
Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to
the PC board. The PCB top layer under the EP53x2QI should be clear of any metal except for the
large thermal pad. The “grayed-out” area in Figure 9 represents the area that should be clear of any
metal (traces, vias, or planes), on the top layer of the PCB.
NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the
perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC
MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest
adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.
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Rev:B
EP5382Q/EP5362Q/EP5352Q
Thermal Pad.
Connect to
Ground plane
Figure 9. Exposed metal and mechanical dimensions of the package . Gray area represents bottom metal no-connect and
area that should be clear of any traces, planes, or vias, on the top layer of the PCB.
0.25
0.25
0.20
0.20
0.20
JEDEC minimum separation = 0.20
Figure 10. Exposed pad clearances; the Enpirion lead frame package complies with JEDEC requirements.
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Rev:B
EP5382Q/EP5362Q/EP5352Q
Figure 11. Recommended PCB Solder Mask Openings.
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Rev:B
EP5382Q/EP5362Q/EP5352Q
Figure 12. Package mechanical dimensions.
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Rev:B
EP5382Q/EP5362Q/EP5352Q
Contact Information
Enpirion, Inc.
685 US Route 202/206 Suite 305
Bridgewater, NJ 08807
Phone: 908-575-7550
Fax: 908-575-0775
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion.
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Rev:B