Cypress CY2309ZXI-1HT Low-cost 3.3v zero delay buffer Datasheet

CY2305
CY2309
Low-Cost 3.3V Zero Delay Buffer
Features
• 10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
• Zero input-output propagation delay
• 60 ps typical cycle-to-cycle jitter (high drive)
• Multiple low-skew outputs
— 85 ps typical output-to-output skew
— One input drives five outputs (CY2305)
— One input drives nine outputs, grouped as 4 + 4 + 1
(CY2309)
• Compatible with Pentium-based systems
• Test Mode to bypass phase-locked loop (PLL) (CY2309
only [see “Select Input Decoding” on page 2])
• Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil
SOIC package (CY2305)
• 3.3V operation
• Industrial temperature available
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
or TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs which lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 µA of current draw for commercial temperature devices and 25.0 µA for industrial temperature parts. The
CY2309 PLL shuts down in one additional case as shown in
the table below.
Multiple CY2305 and CY2309 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two/three different configurations, as shown in the ordering information (page 10). The
CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1s.
Block Diagram
Pin Configuration
PLL
MUX
REF
SOIC/TSSOP
Top View
CLKOUT
REF
CLKA1
1
16
CLKA1
2
15
CLKA2
VDD
3
CLKA2
14
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
CLKA3
CLKA4
CLKB1
S2
Select Input
Decoding
REF
CLK2
CLK1
GND
CLKB3
CLKB4
Cypress Semiconductor Corporation
Document #: 38-07140 Rev. *G
•
3901 North First Street
GND
CLKB4
CLKB3
S1
SOIC
Top View
CLKB2
S1
CLKOUT
CLKA4
CLKA3
VDD
•
1
8
2
7
3
6
4
5
CLKOUT
CLK4
VDD
CLK3
San Jose, CA 95134
•
408-943-2600
Revised August 4, 2005
CY2305
CY2309
Pin Description for CY2309
Pin
Signal
Description
1
REF[1]
Input reference frequency, 5V-tolerant input
2
CLKA1[2]
Buffered clock output, Bank A
3
CLKA2[2]
Buffered clock output, Bank A
4
VDD
3.3V supply
5
GND
Ground
6
CLKB1[2]
Buffered clock output, Bank B
7
[2]
CLKB2
Buffered clock output, Bank B
8
S2[3]
Select input, bit 2
9
S1[3]
Select input, bit 1
10
CLKB3[2]
Buffered clock output, Bank B
11
CLKB4[2]
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[2]
Buffered clock output, Bank A
15
CLKA4[2]
Buffered clock output, Bank A
16
CLKOUT[2]
Buffered output, internal feedback on this pin
Pin Description for CY2305
Pin
Signal
Description
1
REF[1]
Input reference frequency, 5V-tolerant input
2
CLK2[2]
Buffered clock output
3
CLK1[2]
Buffered clock output
4
GND
Ground
5
CLK3[2]
Buffered clock output
6
VDD
3.3V supply
7
CLK4[2]
Buffered clock output
8
CLKOUT[2]
Buffered clock output, internal feedback on this pin
Select Input Decoding for CY2309
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT[4]
Output Source
PLL Shutdown
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07140 Rev. *G
Page 2 of 14
CY2305
CY2309
REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
other outputs, for obtaining zero input-output delay. If input to
output delay adjustments are required, use the above graph to
calculate loading differences between the CLKOUT pin and
other outputs.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT
is not used, it must have a capacitive load, equal to that on
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled “CY2305 and CY2309 as PCI and SDRAM Buffers.”
Document #: 38-07140 Rev. *G
Page 3 of 14
CY2305
CY2309
Absolute Maximum Conditions
Storage Temperature ................................. –65°C to +150°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF......................................... –0.5V to 7V
Junction Temperature ................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter
Description
Min.
Max.
Unit
3.0
3.6
V
0
70
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, below 100 MHz
–
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
–
10
pF
CIN
Input Capacitance
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
–
7
pF
0.05
50
ms
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter
Description
VIL
Input LOW Voltage[5]
Voltage[5]
VIH
Input HIGH
IIL
Input LOW Current
IIH
VOL
Test Conditions
Min.
Max.
Unit
–
0.8
V
2.0
–
V
VIN = 0V
–
50.0
µA
Input HIGH Current
VIN = VDD
–
100.0
µA
Output LOW Voltage[6]
IOL = 8 mA (–1)
IOH = 12 mA (–1H)
–
0.4
V
VOH
Output HIGH Voltage[6]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
–
V
IDD (PD mode)
Power Down Supply Current
REF = 0 MHz
–
12.0
µA
IDD
Supply Current
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
–
32.0
mA
Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices[7]
Parameter
t1
Name
Test Conditions
Min.
Typ.
Max.
Unit
10
10
–
100
133.33
MHz
MHz
40.0
50.0
60.0
%
Measured between 0.8V and 2.0V
–
–
2.50
ns
Measured between 0.8V and 2.0V
–
–
2.50
ns
Output Frequency
30-pF load
10-pF load
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
[6]
t3
Rise Time
t4
Fall Time[6]
Skew[6]
t5
Output to Output
–
85
250
ps
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
–
0
±350
ps
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
CLKOUT Rising Edge[6]
Bypass Mode, CY2309 device only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT pins
of devices
–
–
700
ps
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67 MHz, loaded outputs
–
70
200
ps
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
tLOCK
PLL Lock
Time[6]
All outputs equally loaded
Notes:
5. REF input has a threshold voltage of VDD/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
7. All parameters specified with loaded outputs.
Document #: 38-07140 Rev. *G
Page 4 of 14
CY2305
CY2309
Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices[7]
Parameter
t1
Name
Description
Min.
Typ.
Max.
Unit
10
10
–
100
133.33
MHz
MHz
Output Frequency
30-pF load
10-pF load
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout < 50.0 MHz
45.0
50.0
55.0
%
t3
Rise Time[6]
Measured between 0.8V and 2.0V
–
–
1.50
ns
t4
Fall Time[6]
Measured between 0.8V and 2.0V
–
–
1.50
ns
[6]
t5
Output to Output Skew
–
85
250
ps
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
–
–
±350
ps
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
CLKOUT Rising Edge[6]
Bypass Mode, CY2309 device only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT pins
of devices
–
–
700
ps
t8
Output Slew Rate[6]
Measured between 0.8V and 2.0V using
Test Circuit #2
1
–
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67 MHz, loaded outputs
–
60
200
ps
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
tLOCK
PLL Lock
Time[6]
All outputs equally loaded
V/ns
Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
–40
85
°C
CL
Load Capacitance, below 100 MHz
–
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
–
10
pF
CIN
Input Capacitance
–
7
pF
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
Description
Test Conditions
Min.
Max.
Unit
–
0.8
V
VIL
Input LOW Voltage[5]
VIH
Input HIGH
Voltage[5]
2.0
–
V
IIL
Input LOW Current
VIN = 0V
–
50.0
µA
IIH
Input HIGH Current
VIN = VDD
–
100.0
µA
VOL
Output LOW Voltage[6]
IOL = 8 mA (–1)
IOH =12 mA (–1H)
–
0.4
V
VOH
Output HIGH Voltage[6]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
–
V
IDD (PD mode)
Power-down Supply Current
REF = 0 MHz
–
25.0
µA
IDD
Supply Current
Unloaded outputs at 66.67 MHz, SEL inputs at
VDD
–
35.0
mA
Document #: 38-07140 Rev. *G
Page 5 of 14
CY2305
CY2309
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices [7]
Parameter
t1
Name
Test Conditions
Min.
Typ.
Max.
Unit
10
10
–
100
133.33
MHz
MHz
40.0
50.0
60.0
%
Measured between 0.8V and 2.0V
–
–
2.50
ns
Measured between 0.8V and 2.0V
–
–
2.50
ns
Output Frequency
30-pF load
10-pF load
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
[6]
t3
Rise Time
t4
Fall Time[6]
[6]
t5
Output to Output Skew
All outputs equally loaded
–
85
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
–
–
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT
pins of devices
–
–
700
ps
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67 MHz, loaded
outputs
–
70
200
ps
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices[7]
Parameter
t1
Name
Description
Min.
Typ.
Max.
Unit
10
10
–
100
133.33
MHz
MHz
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
Output Frequency
30-pF load
10-pF load
Duty Cycle[6] = t2 ÷ t1
Duty
Cycle[6]
= t2 ÷ t1
Measured at 1.4V, Fout < 50.0 MHz
45.0
50.0
55.0
%
t3
Rise Time[6]
Measured between 0.8V and 2.0V
–
–
1.50
ns
t4
Fall Time[6]
Measured between 0.8V and 2.0V
–
–
1.50
ns
t5
Output to Output Skew[6]
All outputs equally loaded
–
85
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
–
–
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT
pins of devices
–
–
700
ps
t8
Output Slew Rate[6]
Measured between 0.8V and 2.0V
using Test Circuit #2
1
–
–
V/ns
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67 MHz, loaded
outputs
–
60
200
ps
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
Document #: 38-07140 Rev. *G
Page 6 of 14
CY2305
CY2309
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
3.3V
0V
t4
t3
Output-Output Skew
OUTPUT
1.4V
1.4V
OUTPUT
t5
Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
OUTPUT
t6
Device-Device Skew
CLKOUT, Device 1
VDD/2
VDD/2
CLKOUT, Device 2
t7
Document #: 38-07140 Rev. *G
Page 7 of 14
CY2305
CY2309
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1 and CY2309-1
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
58
56
56
54
52
33 MHz
50
66 MHz
48
100 MHz
46
Duty Cycle (% )
Duty Cycle (% )
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
54
66 MHz
50
100 MHz
48
133 MHz
46
44
44
42
42
40
33 MHz
52
40
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
VDD (V)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
60
60
58
58
3.5
3.6
56
54
-40C
52
0C
50
25C
48
70C
46
85C
Duty Cycle (%)
Duty Cycle (%)
3.4
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
56
54
-40C
52
0C
50
25C
48
70C
46
85C
44
44
42
42
40
40
20
40
60
80
100
120
140
20
40
60
Frequency (MHz)
80
100
120
140
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
140
120
120
100
33 MHz
80
66 MHz
60
100 MHz
IDD (mA)
100
IDD (mA)
3.3
VDD (V)
33 MHz
80
66 MHz
60
40
40
20
20
100 MHz
0
0
0
1
2
3
4
5
6
# of Loaded Outputs
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
Notes:
8. Duty Cycle is taken from typical chip measured at 1.4V.
9. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply
Voltage (V); f = frequency (Hz)).
Document #: 38-07140 Rev. *G
Page 8 of 14
CY2305
CY2309
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1H and CY2309-1H
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
58
56
56
54
52
33 MHz
50
66 MHz
48
100 MHz
46
54
Duty Cycle (% )
Duty Cycle (% )
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
33 MHz
52
66 MHz
50
100 MHz
48
133 MHz
46
44
44
42
42
40
40
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
3.3
VDD (V)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
60
60
58
58
3.6
56
54
-40C
52
0C
50
25C
48
70C
46
85C
Duty Cycle (%)
Duty Cycle (%)
3.5
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
56
54
-40C
52
0C
50
25C
48
70C
46
85C
44
44
42
42
40
40
20
40
60
80
100
120
140
20
40
60
80
Frequency (MHz)
100
120
140
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
160
160
140
140
120
120
100
33 MHz
80
66 MHz
60
100 MHz
IDD (mA)
IDD (mA)
3.4
VDD (V)
100
80
33 MHz
60
66 MHz
100 MHz
40
40
20
20
0
0
0
1
2
3
4
5
6
# of Loaded Outputs
Document #: 38-07140 Rev. *G
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
Page 9 of 14
CY2305
CY2309
Test Circuits
Test Circuit # 2
Test Circuit # 1
V DD
V DD
CLK
0.1 µ F
0.1 µ F
out
OUTPUTS
OUTPUTS
10 pF
C LOAD
GND
0.1 µ F
GND
1 kΩ
V DD
V DD
0.1 µ F
1 kΩ
GND
GND
For parameter t8 (output slew rate) on -1H devices
Ordering Information
Ordering Code
Package Type
Operating Range
CY2305SC-1
8-pin 150-mil SOIC
Commercial
CY2305SC-1T
8-pin 150-mil SOIC – Tape and Reel
Commercial
CY2305SZC-1
8-pin 150-mil SOIC – (Lead-free)
Commercial
CY2305SZC-1T
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
CY2305SXC-1
8-pin 150-mil SOIC – (Lead-free)
Commercial
CY2305SXC-1T
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
CY2305SI-1
8-pin 150-mil SOIC
Industrial
CY2305SI-1T
8-pin 150-mil SOIC – Tape and Reel
Industrial
CY2305SZI-1
8-pin 150-mil SOIC – (Lead-free)
Industrial
CY2305SZI-1T
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2305SXI-1
8-pin 150-mil SOIC – (Lead-free)
Industrial
CY2305SXI-1T
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2305SC-1H
8-pin 150-mil SOIC
Commercial
CY2305SC-1HT
8-pin 150-mil SOIC – Tape and Reel
Commercial
CY2305SZC-1H
8-pin 150-mil SOIC – (Lead-free)
Commercial
CY2305SZC-1HT
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
CY2305SXC-1H
8-pin 150-mil SOIC – (Lead-free)
Commercial
CY2305SXC-1HT
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
CY2305SI-1H
8-pin 150-mil SOIC
Industrial
CY2305SI-1HT
8-pin 150-mil SOIC – Tape and Reel
Industrial
CY2305SZI-1H
8-pin 150-mil SOIC – (Lead-free)
Industrial
CY2305SZI-1HT
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2305SXI-1H
8-pin 150-mil SOIC – (Lead-free)
Industrial
CY2305SXI-1HT
8-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2309SC-1
16-pin 150-mil SOIC
Commercial
CY2309SC-1T
16-pin 150-mil SOIC – Tape and Reel
Commercial
CY2309SZC-1
16-pin 150-mil SOIC – (Lead-free)
Commercial
CY2309SZC-1T
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
CY2309SXC-1
16-pin 150-mil SOIC – (Lead-free)
Commercial
CY2309SXC-1T
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
Document #: 38-07140 Rev. *G
Page 10 of 14
CY2305
CY2309
Ordering Information (continued)
Ordering Code
CY2309SI-1
Package Type
Operating Range
16-pin 150-mil SOIC
Industrial
CY2309SI-1
16-pin 150-mil SOIC
Industrial
CY2309SI-1T
16-pin 150-mil SOIC – Tape and Reel
Industrial
CY2309SZI-1
16-pin 150-mil SOIC – (Lead-free)
Industrial
CY2309SZI-1T
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2309SXI-1
16-pin 150-mil SOIC – (Lead-free)
Industrial
CY2309SXI-1T
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2309SC-1H
16-pin 150-mil SOIC
Commercial
CY2309SC-1HT
16-pin 150-mil SOIC – Tape and Reel
Commercial
CY2309SZC-1H
16-pin 150-mil SOIC – (Lead-free)
Commercial
CY2309SZC-1HT
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
CY2309SXC-1H
16-pin 150-mil SOIC – (Lead-free)
Commercial
CY2309SXC-1HT
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Commercial
CY2309SI-1H
16-pin 150-mil SOIC
Industrial
CY2309SI-1HT
16-pin 150-mil SOIC – Tape and Reel
Industrial
CY2309SZI-1H
16-pin 150-mil SOIC – (Lead-free)
Industrial
CY2309SZI-1HT
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2309SXI-1H
16-pin 150-mil SOIC – (Lead-free)
Industrial
CY2309SXI-1HT
16-pin 150-mil SOIC – Tape and Reel – (Lead-free)
Industrial
CY2309ZC-1H
16-pin 4.4-mm TSSOP
Commercial
CY2309ZC-1HT
16-pin 4.4-mm TSSOP – Tape and Reel
Commercial
CY2309ZXC-1H
16-pin 4.4-mm TSSOP – (Lead-free)
Commercial
CY2309ZXC-1HT
16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)
Commercial
CY2309ZZC-1H
16-pin 4.4-mm TSSOP – (Lead-free)
Commercial
CY2309ZZC-1HT
16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)
Commercial
CY2309ZI-1H
16-pin 4.4-mm TSSOP
Industrial
CY2309ZI-1HT
16-pin 4.4-mm TSSOP – Tape and Reel
Industrial
CY2309ZXI-1H
16-pin 4.4-mm TSSOP – (Lead-free)
Industrial
CY2309ZXI-1HT
16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)
Industrial
CY2309ZZI-1H
16-pin 4.4-mm TSSOP – (Lead-free)
Industrial
CY2309ZZI-1HT
16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)
Industrial
Document #: 38-07140 Rev. *G
Page 11 of 14
CY2305
CY2309
Package Drawing and Dimensions
8 Lead (150 Mil) SOIC - S08
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
16 Lead (150 Mil) SOIC
16-Lead (150-Mil) SOIC S16
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
9
SZ16.15 LEAD FREE PKG.
16
0.386[9.804]
0.393[9.982]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
51-85068-*B
Document #: 38-07140 Rev. *G
Page 12 of 14
CY2305
CY2309
Package Drawing and Dimensions (continued)
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05gms
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the
trademarks of their respective holders.
Document #: 38-07140 Rev. *G
Page 13 of 14
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2305
CY2309
Document History Page
Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer
Document Number: 38-07140
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
110249
10/19/01
SZV
Change from Spec number: 38-00530 to 38-07140
*A
111117
03/01/02
CKN
Added t6B row to the Switching Characteristics Table; also added the letter
“A” to the t6A row
Corrected the table title from CY2305SC-IH and CY2309SC-IH to
CY2305SI-IH and CY2309SI-IH
*B
117625
10/21/02
HWT
Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the
ordering information table.
Added the Tape and Reel option to all the existing packages:
CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT,
CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT,
CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT
*C
121828
12/14/02
RBI
Power-up requirements added to Operating Conditions information
*D
131503
12/12/03
RGL
Added Lead-free for all the devices in the ordering information table
*E
214083
See ECN
RGL
Added a Lead-free with the new coding for all SOIC devices in the ordering
information table
*F
291099
See ECN
RGL
Added TSSOP Lead-free devices
*G
390582
See ECN
RGL
Added typical values for jitter
Document #: 38-07140 Rev. *G
Page 14 of 14