EM EM6151 Low power windowed watchdog with reset, sleep mode function Datasheet

EM MICROELECTRONIC - MARIN SA
R
EM6151
Low Power Windowed Watchdog with Reset,
Sleep Mode Functions
Description
Features
The EM6151 offers a high level of integration by combining
voltage monitoring and software monitoring using a windowed
watchdog.
‰ Low quiescent current 35 μA
‰ -40°C to +125°C temperature range
‰ Windowed watchdog with an adjustable time windows,
guaranteeing a minimum time and a maximum time
between software clearing of the watchdog
‰ Time base accuracy ±8% (at 100ms)
‰ Voltage reference accuracy ±3%
‰ Sleep mode function (V55)
‰ Adjustable threshold voltage using external resistors
‰ Adjustable power on reset (POR) delay using one external
resistor
‰ Open-drain active-low RESET output
‰ Reset output guaranteed for regulated output voltage down
to 1.2 V
‰ System ENABLE output offers added security
‰ Qualified according to AEC-Q100
‰ Green SO-8 package (RoHS compliant)
A comparator monitors the voltage applied at the VIN input
comparing it with an internal voltage reference VREF. The
power-on reset function is initialized after VIN reaches VREF
and takes the reset output inactive after a delay TPOR
depending on external resistance ROSC. The reset output goes
active low when the VIN voltage is less than VREF. The RES
and EN outputs are guaranteed to be in a correct state for a
supply voltage as low as 1.2 V. The watchdog function
monitors software cycle time and execution.
If software clears the watchdog too quickly (incorrect cycle
time) or too slowly (incorrect execution) it will cause the
system to be reset. For enhanced security, the watchdog
must be serviced within an “open” time window. During the
remaining time, the watchdog time window is “closed” and a
reset will occur should a TCL pulse be received by the
watchdog during this “closed” time window. The ratio of the
open/closed window is either 33%/67% or 67%/33%.
Applications
The system ENABLE output prevents critical control functions
being activated until software has successfully cleared the
watchdog three times. Such a security could be used to
prevent motor controls being energized on repeated resets of
a faulty system.
‰
‰
‰
‰
‰
‰
When the microcontroller goes in stand-by mode or stops
working, no signal is received on the TCL input of the
EM6151 (version 55) and it goes into a stand-by mode in
order to save power (CAN-bus sleep detector).
Typical Operating Configuration
Selection Table
ROSC
VSS
R1
VIN
TCL
I/O
RES
RES
I/O
EN
Microprocessor
ROSC
100nF
Closed
Open
Window
Window
CAN-bus sleep
detector
Part Number
VREF
EM6151V30
1.17 V
67%
33%
No
EM6151V50
1.52 V
67%
33%
No
EM6151V53
1.52 V
33%
67%
No
EM6151V55
1.275 V
67%
33%
Yes
VDD
VDD
EM6151
Automotive systems
Industrial
Home security systems
Telecom / Networking
Computers
Set top boxes
Please refer to Fig. 4 for more information about the
open/closed window of the watchdog.
R2
GND
Fig. 1
Copyright © 2005, EM Microelectronic-Marin SA
rev. B / 06.06
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EM6151
Ordering Information
Part Number
EM6151V30SO8A+
EM6151V30SO8B+
EM6151V50SO8A+
EM6151V50SO8B+
EM6151V53SO8A+
EM6151V53SO8B+
EM6151V55SO8A+
EM6151V55SO8B+
Version
VREF
Package
V30
1.17 V
SO-8
V50
1.52 V
SO-8
V53
1.52 V
SO-8
V55
1.275 V
SO-8
Package
Marking
Delivery Form
Stick, 97 pcs
Tape & Reel, 2500 pcs
Stick, 97 pcs
Tape & Reel, 2500 pcs
Stick, 97 pcs
Tape & Reel, 2500 pcs
Stick, 97 pcs
Tape & Reel, 2500 pcs
6151030
6151050
6151053
6151055
Note: the “+” symbol at the end of the part number means that this product is RoHS compliant (green). For version V30, please
contact EM Microelectronic.
Pin Assignment and Description
SO8
Name
Function
1
EN
2
RES
3
TCL
Push-pull active low enable output
Open drain active low reset output.
RES must be pulled up to VDD even
if unused
Watchdog timer clear input signal
4
VSS
GND terminal
5
NC
No connect
6
VDD
Supply voltage
7
ROSC
ROSC input for RC oscillator tuning
8
VIN
SO8
EN
1
8
VIN
RES
2
7
ROSC
TCL
3
6
VDD
VSS
4
5
NC
EM6151
Voltage comparator input
Block Diagram EM6151
Voltage
Reference
VREF
VIN
ROSC
Enable
Logic
EN
Reset
Control
RES
Comparator
+
Current
Controlled
Oscillator
Timer
Open drain
output RES
TCL
Fig. 2
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EM6151
Absolute Maximum Ratings
Parameter
Max. voltage at VDD
Max. voltage at any signal pin
Min. voltage at any signal pin
Storage temperature
ESD
According to MIL-STD-883C
method 3015.7
Operating Conditions
Symbol
Conditions
VDDMAX
VMAX
VMIN
TSTO
VSS + 7.0V
VDD + 0.3V
VSS – 0.3V
-65 to +150 °C
VSmax
Parameter
Operating junction
temperature
Supply voltage
Symbol
Min.
Max.
Units
Tj
-40
+125
°C
VDD
1.2
5.5
V
VDD
1.2
VIN
ROSC
0
10
RES and EN guaranteed
(note 1)
Comparator input voltage
RC-oscillator programming
2000V
V
VDD
1000
Table 1
V
kΩ
Table 2
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability or
cause malfunction.
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, it is advised that normal
precautions be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only occur
when all terminal voltages are kept within the voltage range.
At any time, all inputs must be tied to a defined logic voltage
level.
Electrical Characteristics
VDD = 5.0V, Tj = -40 to +125°C, unless otherwise specified
Parameter
Supply current
Supply current in standby mode and sleep
mode for V55
RES and EN
Output Low Voltage
Symbol
IDD
IDD
VOL
EN
Output High Voltage
VOH
TCL Input Low Level
TCL Input High Level
Leakage current
VIL
VIH
ILI
Comparator reference (note 2)
VREF
Comparator hysteresis (note 2)
VIN input resistance
VHY
RVIN
Test Conditions
ROSC = 100kΩ VIN and TCL =
VDD, O/PS 1MΩ to VDD
ROSC = don’t care, TCL = VDD, VIN
=0V
VDD = 4.5 V, IOL = 8 mA
VDD = 2.0 V, IOL = 4 mA
VDD = 1.2 V, IOL = 0.5 mA
VDD = 4.5 V, IOH= -1 mA
VDD = 2.0 V, IOH= -100 μA
VDD = 1.2 V, IOH= -20 μA
VSS ≤ VTCL ≤ VDD
Version V30 (replaces V6130)
Version V50 (replaces V6150)
Version V53
Version V55 (replaces V6155)
Min.
3.5
1.8
0.9
VSS
2.5
1.135
1.475
1.475
1.235
Typ.
Max.
Units
35
60
μA
25
50
μA
0.25
0.2
0.04
4.1
1.9
1.05
0.45
0.4
0.2
V
V
V
V
V
V
V
V
μA
V
V
V
V
mV
MΩ
0.5
VDD
0.05
1.170
1.520
1.520
1.275
2
100
1.205
1.565
1.565
1.315
Table 3
Note 1:
Note 2:
RES must be pulled up externally to VDD even if it is unused. ( RES and EN are used as inputs by EM test)
the comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference voltage
plus the comparator hysteresis (see Fig. 5).
Copyright © 2005, EM Microelectronic-Marin SA
rev. B / 06.06
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EM6151
Timing Characteristics
VDD = 5.0 V, Tj = -40 to +125 °C, unless otherwise specified
Parameter
Propagation delay TCL to Output Pins
VIN sensitivity
Watchdog Reset Pulse Period
Version V30
Power-on Reset delay
Closed Window Time
Open Window Time
Watchdog Time
Watchdog Reset Pulse Width if no TCL
Version V50
Power-on Reset delay
Closed Window Time
Open Window Time
Watchdog Time
Watchdog Reset Pulse Width if no TCL
Version V53
Power-on Reset delay
Closed Window Time
Open Window Time
Watchdog Time
Watchdog Reset Pulse Width if no TCL
Version V55
Power-on Reset delay
Closed Window Time
Open Window Time
Watchdog Time
Watchdog Reset Pulse Width if no TCL
Watchdog Reset Pulse Width in Sleep Mode
Watchdog Reset Pulse Period in Sleep Mode
Symbol
TDIDO
TSEN
TWDRP
Test Conditions
Min.
VINhigh=1.1xVREF, VINlow=0.9xVREF
TCL inactive
TPOR
TCW
TOW
TWD
TWDR
ROSC= 116.9 kΩ ±1%
TPOR
TCW
TOW
TWD
TWDR
ROSC= 121.6 kΩ ±1%
TPOR
TCW
TOW
TWD
TWDR
ROSC = 23.2 kΩ ±1%
TPOR
TCW
TOW
TWD
TWDR
TWDRS
TWDRPS
ROSC = 107.5 kΩ ±1%
ROSC off; RINT=1MΩ
TCL inactive
Typ.
Max.
250
500
1
5
20
TCW + TOW+ TWDR
Units
ns
μs
ms
91.6
74
37
92.5
2.25
100
80
40
100
2.5
108.3
85.76
42.88
107.2
2.75
ms
91.6
74
37
92.5
2.25
100
80
40
100
2.5
108.3
85.76
42.88
107.2
2.75
ms
4.57
9.24
18.48
18.48
0.56
5.0
10
20
20
0.625
5.44
10.77
21.54
21.54
0.69
ms
91.6
74
37
92.5
2.25
2.8
750
100
80
40
100
2.5
3.2
1100
108.3
85.76
42.88
107.2
2.75
3.6
1450
ms
Table 4
For different values of TWD and ROSC, see figures 9 to 12.
Timing Waveforms
Watchdog Timeout Period
Version V50:
Version V53:
For ROSC=121.6 kOhm
TWD
TWD
TCW (closed window)
Watchdog
timer reset
For ROSC=23.2 kOhm
TOW (open)
80
TCW (closed)
120
Watchdog
timer reset
Time [ms]
TOW (open)
10
30
Time [ms]
( V30, V50 and V55 have similar ratios for T CW and TOW )
Fig. 4
Copyright © 2005, EM Microelectronic-Marin SA
rev. B / 06.06
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EM6151
Voltage Monitoring
VIN
Conditions:
VDD > 3V
No timeout
VHY
VREF
TSEN
TSEN
TSEN
TSEN
TPOR
TPOR
RES
Fig. 5
Timer Reaction
Conditions: VIN > VREF after power-up sequence
TTCL
TCW
TCW
TCW + TOW TCW + TOW
TOW
TCW
TCW + TOW
TTCL
TCL
RES
EN
TWDR
1
2
3
3 correct TCL services
EN goes active low
Timeout
- Watchdog timer reset
Fig. 6
Combined Voltage and Timer Reaction
VIN
Condition:
VDD > 3V
VREF
TPOR
TCL
TOW
TTCL
TCW
TCW+TOW
RES
EN
1
2
3
TCL
too early
3 correct TCL services
EN goes active low
- Watchdog timer reset
Fig. 7
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EM6151
Functional Description
VIN Monitoring
Watchdog Timeout Period Description
The power-on reset and the power-down reset are
generated as a response to the external voltage level
applied on the VIN input. The threshold voltage at which
reset is asserted or released (VRESET) is determined by the
external voltage divider between VDD and VSS, as shown on
Fig. 8. A part of VDD is compared to the internal voltage
reference. To determine the values of the divider, the
leakage current at VIN must be taken into account as well as
the current consumption of the divider itself. Low resistor
values will need more current, but high resistor values will
make the reset threshold less accurate at high temperature,
due to a possible leakage current at the VIN input. The sum
of the two resistors (R1 + R2) should stay below 500 kΩ. The
formula is:
The watchdog timeout period is divided into two periods, a
closed window period (TCW) and an open window period
(TOW), see Fig. 4. If no pulse is applied on the TCL input
during the open window period TOW, the RES output goes
low for a time TWDR. When a pulse is applied on the TCL
input, the cycle is restarted with a close window period.
For example if TWD = TPOR = 100ms, TCW = 80 ms, TOW =
40ms and TWDR = 2.5ms.
When VIN recovers after a drop below VREF, the pad RES is
set low for the time TPOR during which any TCL activation is
disabled.
Timer Clearing and RES Action
VRESET = VREF x (1 + R1/R2).
The watchdog circuit monitors the activity of the processor.
If the user’s software does not send a pulse to the TCL
input within the programmed open window timeout period a
short watchdog RES pulse is generated which is equal to
TWDR (see Fig. 6).
With the open window constraint, new security is added to
conventional watchdogs by monitoring both software cycle
time and execution. Should software clear the watchdog too
quickly (incorrect cycle time) or too slowly (incorrect
execution) it will cause the system to be reset. If software is
stuck in a loop which includes the routine to clear the
watchdog then a conventional watchdog would not make a
system reset even though the software is malfunctioning;
the circuit would make a system reset because the
watchdog would be cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves of
period (TCW + TOW + TWDR). The watchdog will remain in this
state until the next TCL falling edge appears during an open
window, or until a fresh power-up sequence. The system
enable output, EN , can be used to prevent critical control
functions being activated in the event of the system going
into this failure mode (see section “Enable- EN Output”).
The RES output must be pulled up to VDD even if the output
is not used by the system (see Fig 8).
Example: choosing R1 = 200 kΩ and R2 = 100 kΩ gives
VRESET =4.56 V (typical) for version V50 and V53.
At power-up the reset output ( RES ) is held low (see Fig. 5).
When VIN becomes greater than VREF, the RES output is
held low for an additional power-on-reset (POR) delay TPOR
(defined with the external resistor connected at ROSC pin).
The TPOR delay prevents repeated toggling of RES even if
VDD voltage drops out and recovers. The TPOR delay allows
the microprocessor’s crystal oscillator time to start and
stabilize and ensures correct recognition of the reset signal
to the microprocessor.
The RES output goes active low generating the powerdown reset whenever VIN falls below VREF. The sensitivity or
reaction time of the internal comparator to the voltage level
on VIN is typically 3 μs.
Timer Programming
The on-chip oscillator allows the user to adjust the power-on
reset (POR) delay TPOR and the watchdog time TWD by
changing the resistor value of the external resistor ROSC
connected between the pin ROSC and VSS (see Fig. 8). The
closed and open window times (TCW and TOW) as well as the
watchdog reset pulse width (TWDR), which are TTCL
dependent, will vary accordingly. The watchdog time TWD
can be obtained with figures 9 to 12 or with the Excel
application EM6151ResCalc.xls available on EM website.
TPOR is equal to TWD with the minimum and maximum
tolerances increased by 1% (For Version 53, TPOR is one
fourth of TWD).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated
by the sequence of events shown in Fig. 6. On power-up,
when the voltage at VIN reaches VREF, the power-on-reset,
POR, delay is initialized and holds RES active for the time
of the POR delay. A TCL pulse will have no effect until this
power-on-reset delay is completed. When the risk exists that
TCL temporarily floats, e.g. during TPOR, a pull-up to VDD is
required on that pin. After the POR delay has elapsed, RES
goes inactive and the watchdog timer starts acting. If no
TCL pulse occurs, RES goes active low for a short time
TWDR after each closed and open window period. A TCL
pulse coming during the open window clears the watchdog
timer. When the TCL pulse occurs too early (during the
closed window), RES goes active and a new timeout
sequence starts. A voltage drop below the VREF level for
longer than typically 3μs overrides the timer and
immediately forces RES active and EN inactive. Any further
TCL pulse has no effect until the next power-up sequence
has completed.
Note that the current consumption increases as the
frequency increases.
CAN-Bus Sleep Mode Detector (version 55)
When the microcontroller goes into a standby mode, it
implies that it does not send any pulses on the TCL input of
the EM6151. After three reset pulse periods (TCW + TOW +
TWDR) on the RES output, the circuit switches on an internal
resistor of 1 MΩ, and it will have a reset pulse of typically 3
ms every 1 second on the RES output. When a TCL edge
(rising or falling) appears on the TCL input or the power
supply goes down and up, the circuit switches to the ROSC.
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EM6151
Enable - EN Output
The system enable output, EN , is inactive always when
RES is active and remains inactive after a RES pulse until
the watchdog is serviced correctly 3 consecutive times (i.e.
the TCL pulse must come in the open window). After three
consecutive services of the watchdog with TCL during the
open window, the EN goes active low.
could be energized each time reset goes inactive (time
allowed for the system to restart) and in this way the
electrical motors driven by the system could function out of
control. The circuit prevents the above failure mode by using
the EN output to disable the motor controls until software
has successfully cleared the watchdog three times (i.e. the
system has correctly re-started after a reset condition).
A malfunctioning system would be repeatedly reset by the
watchdog. In a conventional system critical motor controls
Typical Application
Regulated Voltage (5V)
VDD
EM6151
ROSC
100kΩ
VSS
R1
Address decoder
VIN
TCL
Microprocessor
RES
RES
EN
R2
EN
Motor
controls
GND
Fig. 8
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EM6151
V30 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125°C
1.44
1.38
Max
Rosc Coefficient [kOhm/ms]
1.32
1.26
1.20
Typ
1.14
1.08
Min
1.02
0.96
10
100
1000
Twd [ms]
Fig. 9
V50 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125°C
1.44
1.38
Max
Rosc Coefficient [kOhm/ms]
1.32
1.26
1.20
Typ
1.14
1.08
Min
1.02
0.96
10
100
1000
Twd [ms]
Fig. 10
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EM6151
V53 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125°C
1.46
1.40
Max
Rosc Coefficient [kOhm/ms]
1.34
1.28
1.22
Typ
1.16
1.10
Min
1.04
0.98
10
100
1000
Twd [ms]
Fig. 11
V55 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125°C
1.34
1.28
Max
Rosc Coefficient [kOhm/ms]
1.22
1.16
1.10
Typ
1.04
0.98
Min
0.92
0.86
10
100
1000
Twd [ms]
Fig. 12
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EM6151
Package Information
Dimensions of 8-pin SOIC Package
E
D
A1
A
C
0 - 8°
L
B
e
4
3
2
1
5
6
7
8
H
Dimensions in mm
Min Nom Max
A 1.35 1.63 1.75
A1 0.10 0.15 0.25
B 0.33 0.41 0.51
C 0.19 0.20 0.25
D 4.80 4.94 5.00
E 3.80 3.94 4.00
e
1.27
H 5.80 5.99 6.20
L 0.40 0.64 1.27
Fig. 13
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SUBJECT TO CHANGE WITHOUT NOTICE
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