ATMEL AT17LV128-10JI Fpga configuration e2prom Datasheet

AT17 Series
Features
• E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed
To Store Configuration Programs For Programmable Gate Arrays
• Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
• Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs,
XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
• Cascadable To Support Additional Configurations or Future Higher-density Arrays
(17C128 and 17C256 only)
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available In the Space-efficient Plastic DIP or Surface-mount
PLCC and SOIC Packages
• In-System Programmable Via 2-Wire Bus
• Emulation of 24CXX Serial EPROMs
• Available in 3.3V ± 10% LV Version
Description
FPGA
Configuration
E2PROM
65K, 128K and 256K
The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration
EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin
DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The AT17 Series
organization supplies enough memory to configure one or multiple smaller FPGAs.
Using a special feature of the AT17 Series, the user can select the polarity of the reset
function by programming a special EEPROM bit.
The AT17 Series can be programmed with industry standard programmers.
AT17C65
AT17C128
AT17C256
Pin Configurations
20-pin PLCC
20-Pin SOIC
8-Pin DIP
0391E-A–5/97
1
Controlling The AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial
EEPROM are simple and self-explanatory.
• The DATA output of the AT17 Series drives DIN of the
FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the AT17 Series.
• The CEO output of any AT17C/LV128/256 drives the CE
input of the next AT17C/LV128/256 in a cascade chain of
PROMs.
• SER_EN must be connected to VCC.
There are, however, two different ways to use the inputs
CE and OE, as shown in the AC Characteristics waveforms.
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
Block Diagram
2
AT17 Series
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
does not see the external reset signal and will not reset its
internal address counters and, consequently, will remain
out of sync with the FPGA for the remainder of the configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the AT17
Series, while its OE input is driven by the inversion of the
input to the FPGA RESET input pin. This connection works
under all normal circumstances, even when the user aborts
a configuration before D/P has gone High. A High level on
the RESET/OE input to the AT17C/LVxxx – during FPGA
reset – clears the Configurator's internal address pointer,
so that the reconfiguration starts at the beginning. The
AT17 Series does not require an inverter since the RESET
polarity is programmable.
AT17 Series
Pin Configurations
PLCC/
SOIC
DIP
Pin
Pin
Name
I/O
Description
2
1
DATA
I/O
Three-state DATA output for reading. Input/Output pin for programming.
4
2
CLK
I
Clock input. Used to increment the internal address and bit counter for reading
and programming.
RESET/Output Enable input (when SER_EN is High). A Low level on both the
CE and RESET/OE inputs enables the data output driver. A High level on
RESET/OE resets both the addresss and bit counters. A logic polarity of this
input is programmable as either RESET/OE or RESET/OE. This document
describes the pin as RESET/OE.
6
3
RESET/OE
8
4
CE
10
5
GND
14
6
CEO
O
Chip Enable Out output. This signal is asserted Low on the clock cycle following
the last bit read from the memory. It will stay Low as long as CE and OE are
both Low. It will then follow CE until OE goes High. Thereafter CEO will stay
High until the entire PROM is read again and senses the status of RESET
polarity.
A2
I
Device selection input, A2. This is used to enable (or select) the device during
programming and when SER_EN is Low (see Programming Guide for more
details).
I
17
7
SER_EN
20
8
VCC
I
Chip Enable input. Used for device selection. A Low level on both CE and OE
enables the data output driver. A High level on CE disables both the address
and bit counters and forces te device into a low power mode. Note this pin will
not enable/disable the device in 2-wire Serial mode (ie; when SER_EN is Low).
Ground Pin
Serial enable is normally high during FPGA loading operations. Bringing
SER_EN low, enables the 2-wire serial interface for programming.
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature.........................-55°C to +125 °C
Storage Temperature............................-65 °C to +150°C
Voltage on Any Pin
with Respect to Ground.................... -0.1V to VCC + 0.5V
Supply Voltage (Vcc) .............................. -0.5 V to +7.0V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.)... 260°C
ESD (RZAP = 1.5K, CZAP = 100pF) ........................2000V
3
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
Cascading Serial Configuration
EEPROMs
(AT17C/LV128 and AT17C/LV256)
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory (17C/
LV128 and 17C/LV256 only).
After the last bit from the first Configurator is read, the next
clock signal to the Configurator asserts its CEO output Low
and disables its DATA line. The second Configurator recognizes the Low level on its CE input and enables its DATA
output.
Figure 1. Condition 1 Connection
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator Active.
If the address counters are not to be reset upon completion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Programming Guide.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the 2wire interface. The programming is done at V CC supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel's Configuration Memories Application Note for further information. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.0V nominal.
AT17C/LVXXX Reset Polarity
The AT17C/LVXXX lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVXXX enters a low-power standby mode
whenever CE is asserted High. In this mode, the Configurator consumes less than 1.0 mA of current. The output
remains in a high impedance state regardless of the state
of the OE input.
Operating Conditions
Symbol
VCC
4
Description
AT17CXXX
AT17LVXXX
Min/Max
Min/Max
Units
Commercial
Supply voltage relative to GND
-0°C to +70°C
4.75/5.25
3.0/3.6
V
Industrial
Supply voltage relative to GND
-40°C to +85C°
4.5/5.5
3.0/3.6
V
Military
Supply voltage relative to GND
-55°C to +125C
4.5/5.5
3.0/3.6
V
AT17 Series
AT17 Series
DC Characteristics
VCC = 5V ± 5% Commercial / 5V ± 10% Ind./Mil.
Symbol
Description
Min
Max
Units
VIH
High-level input voltage
2.0
VCC
V
VIL
Low-level input voltage
0
0.8
V
VOH
High-level output voltage (IOH = -4 mA)
VOL
Low-level output voltage (IOL = +4 mA)
VOH
High-level output voltage (IOH = -4 mA)
VOL
Low-level output voltage (IOL = +4 mA)
VOH
High-level output voltage (IOH = -4 mA)
VOL
Low-level output voltage (IOL = +4 mA)
0.4
V
ICCA
Supply current, active mode
10
mA
IL
Input or output leakage current (VIN = VCC or GND)
10
µA
Commercial
75
µA
Industrial/Military
150
µA
Commercial
1
mA
Industrial/Military
2
mA
3.7
V
Commercial
0.32
3.6
V
Industrial
0.37
3.5
V
V
Military
-10
Supply current, standby mode AT17C256
ICCS
V
Supply current, standby mode AT17C128/65
DC Characteristics
VCC = 3.3V ± 10%
Symbol
Description
Min
Max
Units
VIH
High-level input voltage
2.0
VCC
V
VIL
Low-level input voltage
0
0.8
V
VOH
High-level output voltage (IOH = -2.5 mA)
VOL
Low-level output voltage (IOL = +3 mA)
VOH
High-level output voltage (IOH = -2 mA)
VOL
Low-level output voltage (IOL = +3 mA)
VOH
High-level output voltage (IOH = -2 mA)
VOL
Low-level output voltage (IOL = +2.5 mA)
ICCA
Supply current, active mode
IL
Input or output leakage current (VIN = VCC or GND)
ICCS
Supply current, standby mode
2.4
V
Commercial
0.4
2.4
V
V
Industrial
0.4
2.4
V
V
Military
0.4
V
5
mA
10
µA
Commercial
50
µA
Industrial/Military
100
µA
-10
5
AC Characteristics
AC Characteristics When Cascading
6
AT17 Series
AT17 Series
AC Characteristics for AT17C256
VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
TCE(2)
TCAC
(2)
Min
Max
Industrial/Military
Min
Max
Units
25
25
ns
CE to Data Delay
45
45
ns
CLK to Data Delay
50
55
ns
TOH(2)
Data Hold From CE, OE, or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
20
20
ns
THC
CLK High Time
20
20
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
35
40
ns
THCE
CE Hold Time to CLk (to guarantee proper counting)
0
0
ns
THOE
OE High Time (guarantees counter is reset)
20
20
ns
FMAX
MAX Input Clock Frequency
12.5
12.5
MHz
0
0
50
ns
50
ns
AC Characteristics for AT17C256 When Cascading
VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Symbol
Description
TCDF(3)
CLK to Data Float Delay
TOCK(2)
TOCE(2)
TOOE(2)
Notes:
Min
Max
Industrial/Military
Min
Max
Units
50
50
ns
CLK to CEO Delay
35
40
ns
CE to CEO Delay
35
35
ns
RESET/OE to CEO Delay
30
35
ns
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
7
AC Characteristics for AT17C65/128
VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
TCE(2)
TCAC
(2)
Min
Max
Industrial/Military
Min
Max
Units
110
150
ns
CE to Data Delay
50
50
ns
CLK to Data Delay
50
55
ns
TOH(2)
Data Hold From CE, OE, or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
30
35
ns
THC
CLK High Time
30
35
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
45
50
ns
THCE
CE Hold Time to CLk (to guarantee proper counting)
0
5
ns
OE High Time (guarantees counter is reset)
50
60
ns
THOE
FMAX
(4)
0
0
50
MAX Input Clock Frequency
ns
50
10
10
ns
MHz
AC Characteristics for AT17C65/128 When Cascading
VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Symbol
Description
TCDF(3)
CLK to Data Float Delay
TOCK(2)
TOCE(2)
TOE(2)
Notes:
Industrial/Military
Max
Units
50
50
ns
CLK to CEO Delay
65
75
ns
CE to CEO Delay
55
60
ns
RESET/OE to CEO Delay
55
55
ns
Min
Max
Min
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
4. During cascade FMAX = 8 MHz.
8
AT17 Series
AT17 Series
AC Characteristics
VCC = 3.3V ± 10%
Commercial
Symbol
Description
Max
Units
40
45
ns
CE to Data Delay
60
60
ns
CLK to Data Delay
75
80
ns
(2)
OE to Data Delay
TCE(2)
TOE
TCAC
(2)
TOH(2)
TDF
Data Hold From CE, OE, or CLK
(3)
Min
Max
Industrial/Military
0
CE or OE to Data Float Delay
Min
0
55
ns
55
ns
TLC
CLK Low Time
25
25
ns
THC
CLK High Time
25
25
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
35
60
ns
THCE
CE Hold Time to CLk (to guarantee proper counting)
0
0
ns
OE High Time (guarantees counter is reset)
25
25
ns
MAX Input Clock Frequency
10
8
THOE
FMAX
(4)
Notes:
10
MHz
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV afrom steady state active levels.
4. During cascade FMAX = 8 MHz.
AC Characteristics When Cascading
VCC = 3.3V ± 10%
Commercial
Symbol
Description
TCDF(3)
CLK to Data Float Delay
TOCK(2)
TOCE(2)
TOOE
(2)
Industrial/Military
Max
Units
60
60
ns
CLK to CEO Delay
55
60
ns
CE to CEO Delay
55
60
ns
RESET/OE to CEO Delay
40
45
ns
Min
Max
Min
9
Ordering Information - 5V Devices
Memory
Size (K)
64K
128K
256K
Ordering Code
Package
Operation Range
AT17C65-10PC
AT17C65-10JC
AT17C65-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17C65-10PI
AT17C65-10JI
AT17C65-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
AT17C128-10PC
AT17C128-10JC
AT17C128-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17C128-10PI
AT17C128-10JI
AT17C128-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
AT17C256-10PC
AT17C256-10JC
AT17C256-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17C256-10PI
AT17C256-10JI
AT17C256-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
Ordering Information - 3.3V Devices
Memory
Size (K)
64K
128K
256K
Ordering Code
Package
Operation Range
AT17LV65-10PC
AT17LV65-10JC
AT17LV65-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17LV65-10PI
AT17LV65-10JI
AT17LV65-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
AT17LV128-10PC
AT17LV128-10JC
AT17LV128-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17LV128-10PI
AT17LV128-10JI
AT17LV128-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
AT17LV256-10PC
AT17LV256-10JC
AT17LV256-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17LV256-10PI
AT17LV256-10JI
AT17LV256-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
Package Type
10
8P3
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20J
20-Lead, Plastic J-Leaded Chip Carrier (PLCC)
20S
20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
AT17 Series
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