FINAL
Am79C30A/32A
Digital Subscriber Controller™ (DSC™) Circuit
DISTINCTIVE CHARACTERISTICS
■ Combines CCITT I.430 S/T-Interface Transceiver,
D-Channel LAPD Processor, Audio
■ Certified protocol software support available
■ CMOS technology, TTL compatible
■ D-channel processing capability
■ Processor (DSC device only), and IOM-2
Interface in a single chip
■ Special operating modes allow realization of
CCITT I.430 power-compliant terminal
equipment
— Flag generation/detection
— CRC generation/checking
— Zero insertion/deletion
— Four 2-byte address detectors
■ S- or T-Interface Transceiver
— Level 1 Physical Layer Controller
— 32-byte receive and 16-byte transmit FIFOs
— Supports point-to-point, short and extended
passive bus configurations
— Provides multiframe support
BLOCK DIAGRAM
SBP/IOM-2 Interface
AINA
AREF
AINB
EAR1
EAR2
LS1
LS2
CAP2
Main Audio
Processor (MAP)
SBIN
SCLK BCL/CH2STRB*
SBIOUT
SFS
HSW
S/T Line
Interface Unit
(LIU)
Peripheral Port
(PP)
(Am79C30A
Only)
Bd Be Bf
LOUT1
LOUT2
LIN1
LIN2
S/T Interface
Audio Interface
CAP1
D
Channel
B1
Ba
XTAL1
XTAL2
B-channel Multiplexer
(MUX)
B2
D-Channel Data
Link Controller
(DLC)
Oscillator
(OSC)
Bb
Bc
MCLK
D
Channel
CS
WR
RD
Microprocessor Interface
(MUX)
D7 D6 D5 D4 D3 D2 D1 D0 INT A2
Microprocessor Interface
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
RESET
A1 A0
09893H-1
Publication# 09893 Rev: H Amendment/0
Issue Date: December 1998
DISTINCTIVE CHARACTERISTICS (continued)
■ Audio processing capability (DSC circuit only)
— Programmable sidetone level
— Registers for implementation of software-based
speaker phone algorithms
— Programmable DTMF, single tone, progress
tone, and ringer tone generation
— Dual audio inputs
— Programmable on-chip microphone amplifier
— Earpiece and loudspeaker drivers
— Codec/filter with A/µ selection
— Programmable gain and equalization filters
■ Pin and software compatible with the
Am79C32A ISDN Data Controller (IDC™) Circuit.
The Am79C32A is used in data-only
applications.
GENERAL DESCRIPTION
The Am79C30A Digital Subscriber Controller (DSC)
Circuit and Am79C32A ISDN Data Controller (IDC) Circuit, shown in the Block Diagram, allow the realization
of highly-integrated Terminal Equipment for the ISDN.
The Am79C30A/32A is fully compatible with the
CCITT-I-series recommendations for the S and T reference points, ensuring that the user of the device may
design TEs which conform to the international standards.
The Am79C30A/32A provides a 192-Kbit/s full duplex
digital path over four wires between the TE located on
the subscriber's premises and the NT or PABX linecard. All physical layer functions and procedures are
implemented in accordance with CCITT Recommendation I.430, including framing, synchronization, maintenance, and multiple ter minal contention. Both
point-to-point and point-to-multipoint configurations are
supported.
The Am79C30A/32A processes the ISDN basic rate bit
stream, which consists of B1 (64 Kbit/s), B2 (64 Kbit/s),
and D (16 Kbit/s) channels. The B channels are routed
to and from different sections of the Am79C30A/32A
2
under software control. The D channel is partially processed by the DSC/IDC circuit and is passed to the microprocessor for further processing.
The Main Audio Processor (MAP) uses Digital Signal
Processing (DSP) to implement a high performance
codec/filter function. The MAP interface supports a
loudspeaker, an earpiece, and two separate audio inputs. Programmable on-chip gain is provided to simplify use of low output level microphones. The user may
alter frequency response and gain of the MAP receive
and transmit paths. Tone generators are included to implement ringing, call progress, and DTMF signals.
A Peripheral Port (PP) is provided to allow the B channels to be routed off-chip for processing by other peripherals. This por t is configurable as either an
industry-standard IOM-2 port, or as a serial bus port
(SBP).
The TE design process is simplified by the availability
of certified protocol software packages, which provide
complete system solutions through OSI Layer 3.
Am79C30A/32A Data Sheet
CONNECTION DIAGRAMS
Top View
AVSS
AINB
AINA
EAR2
EAR1
LS2
LS1
AREF
LIN1
LIN2
HSW
6
5
4
3
2
1
44
43
42
41
40
44-Pin PLCC
CAP1
7
39
LOUT1
CAP2
8
38
LOUT2
AVCC
9
37
AVSS
DV CC
10
36
DV SS
RESET
11
35
INT
CS
12
34
XTAL1
Am79C30A
26
27
28
D1
D0
SBIN
SBOUT
25
29
D2
17
24
A1
D3
SCLK
23
30
BCL/CH2STRB
16
22
A2
D4
SFS
21
31
D5
15
20
DV SS
D6
MCLK
19
XTAL2
32
D7
33
14
18
13
A0
RD
WR
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
LS2
LS1
AREF
LIN1
LIN2
HSW
6
5
4
3
2
1
44
43
42
41
40
44-Pin PLCC
RSRVD
7
39
LOUT1
RSRVD
8
38
LOUT2
AVCC
9
37
AVSS
DV CC
10
36
DV SS
RESET
11
35
INT
CS
12
34
XTAL1
RD
13
33
XTAL2
Am79C32A
24
25
26
27
28
D3
D2
D1
D0
SBIN
SBOUT
23
29
BCL/CH2STRB
17
22
A1
D4
SCLK
21
30
D5
16
20
A2
D6
SFS
19
MCLK
31
D7
32
15
18
14
A0
WR
DV SS
Note:
1. Pin 1 is marked for orientation purposes.
2. RSRVD = Reserved pin; should not be connected externally to any signal or supply.
Am79C30A/32A Data Sheet
3
CONNECTION DIAGRAMS (continued)
Top View
AVSS
AINB
AINA
EAR2
EAR1
LS2
LS1
AREF
LIN1
LIN2
HSW
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP
CAP1
1
33
LOUT1
CAP2
2
32
LOUT2
AVCC
3
31
AVSS
DV CC
4
30
DVSS
RESET
5
29
INT
CS
6
28
XTAL1
Am79C30A
20
21
22
D1
D0
SBIN
SBOUT
19
23
D2
11
18
A1
D3
SCLK
17
24
BCL/CH2STRB
10
16
A2
D4
SFS
15
25
D5
9
14
DV SS
D6
MCLK
13
XTAL2
26
D7
27
8
12
7
A0
RD
WR
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
LS2
LS1
RSRVD
LIN1
LIN2
HSW
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP
RSRVD
1
33
LOUT1
RSRVD
2
32
LOUT2
AVCC
3
31
AVSS
DV CC
4
30
DVSS
RESET
5
29
INT
CS
6
28
XTAL1
RD
7
27
XTAL2
WR
Am79C32A
18
19
20
21
22
D3
D2
D1
D0
SBIN
SBOUT
17
23
BCL/CH2STRB
11
16
A1
D4
SCLK
15
24
D5
10
14
A2
D6
SFS
13
9
D7
MCLK
25
12
26
A0
8
DV SS
Note:
Pin 1 is marked for orientation purposes.
4
Am79C30A/32A Data Sheet
ORDERING INFORMATION
Standard Products
AMD ® standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
AM79C30A/32A
J
C
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
V = 44-Pin Thin Plastic Quad Flat Pack (PQT044)
SPEED OPTION
Not Applicable
DEVICE NAME/DESCRIPTION
Am79C30A/32A
Digital Subscriber Controller (DSC) device
ISDN Data Controller (IDC) device
Valid Combinations
Valid Combinations
AM79C30A
JC, VC
AM79C32A
JC, VC
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Reference Appendix C, Figures 1 & 2, for specific mechanical dimensions of the two packages.
Am79C30A/32A Data Sheet
5
PIN DESCRIPTION*
EAR1, EAR2
Earpiece Interface (Differential Outputs)
Line Interface Unit (LIU)
EAR1 and EAR2 are the outputs from the receive path
of the codec/filter. These differential outputs can directly drive a minimum load of 130 ohms.
HSW
Hook-Switch (Input)
The HSW signal indicates if the hook-switch is on or off
hook. This signal may be generated with a mechanical
switch wired to ground with a pull-up resistor to VCC.
Any change in the HSW state causes an interrupt.
LIN1, LIN2
Subscriber Line Input (Differential Inputs)
LS1, LS2
Loudspeaker Interface (Differential Outputs)
LS1 and LS2 are push-pull outputs which can directly
drive a minimum load of 40 ohms.
Microprocessor Interface (MPI)
The LIN1 and LIN2 inputs interface to the subscriber (S
reference point) via an isolation transformer. LIN2 is the
positive input; LIN1 is the negative input. These pins
are not TTL compatible.
A2–A0
Address Line (Inputs)
LOUT1, LOUT2
Subscriber Line Output (Differential Outputs)
CS
Chip Select (Input)
The LOUT1 and LOUT2 line driver output signals interface to the subscriber line at the S reference point via
an isolation transformer and resistors. LOUT2 is the
positive S-interface driver (sources current during a
High mark), and LOUT1 is the negative S-interface
dr iver ( sou rce s cur ren t d ur ing Low ma r k). Fo r
multi-point applications, all TEs must maintain the
same polarity on the S Interface. These pins are not
TTL compatible.
CS must be Low to read or write to the Am79C30A/
32A. Data transfer occurs over the bidirectional data
lines (D7–D0).
Main Audio Processor (MAP)
All MAP pins are analog, and therefore are not TTL
compatible.
AINA, AINB
Analog (Inputs)
These analog inputs allow for two separate analog (audio) inputs to the transmit path of the codec/filter.Input
signals on either of these pins must be referenced to
AREF.
AREF
Analog Reference (Output)
This is a nominal 2.25-V reference voltage output for biasing the analog inputs. When the MAP is disabled,
this pin is high impedance.
CAP1, CAP2
Capacitor/Resistor (CAP1, Input; CAP2, Output)
An external resistor and capacitor are connected in series between these pins. These components are
needed for the integrator in the Analog-to-Digital Converter (ADC).
A2, A1, and A0 signals select source and destination
registers for read and write operations on the data bus.
D7–D0
Data Bus (Bidirectional with High-Impedance State)
The eight bidirectional data bus lines are used to exchange information with the microprocessor. D0 is the
least significant bit (LSB) and D7 is the most significant
bit (MSB). A High on the data bus line corresponds to
a logic 1, and Low corresponds to a logic 0. These lines
act as inputs when both WR and CS are active and as
outputs when both RD and CS are active. When CS is
inactive or both RD and WR are inactive, the D7–D0
pins are in a high-impedance state.
INT
Interrupt (Output)
An active Low output on the INT pin informs the external microprocessor that the Am79C30A/32A needs interrupt service. INT is updated once every 125 µs. The
INT pin remains active until the Interrupt Register (IR)
is read or the Am79C30A/32A is reset.
RESET
Reset (Input)
Reset is an active High signal which causes the
Am79C30A/32A to immediately terminate its present
activity and initialize to the reset condition. When reset
returns Low, the Am79C30A/32A enters the Idle mode.
The MCLK output remains active while RESET is held
High.
Note:
* All signal levels are TTL compatible unless otherwise stated.
6
Am79C30A/32A Data Sheet
RD
Read (Input)
The active Low read signal is conditioned by CS and indicates that internal information is to be transferred
onto the data bus. A number of internal registers are
user accessible. The contents of the accessed register
are transferred onto the data bus after the High to Low
transition of the RD input.
WR
Write (Input)
The active Low write signal is conditioned by CS and
indicates that external information on the data bus is to
be transferred to an internal register. The contents of
the data bus are loaded on the Low to High transition of
the WR input.
Peripheral Port is programmed to IOM-2 mode, SBOUT
functions as the data output except in the special case
of IOM-2 Slave mode when it becomes an input during
part or all of the IOM-2 frame.
SCLK
Serial Data Clock (Input/Output)
When the PP is programmed to SBP mode, SCLK outputs a 192-kHz data clock, which may be inverted
under software control. When the PP is programmed to
IOM-2 Master mode, SCLK outputs a 1.536-MHz 2X
data clock. In IOM-2 Slave mode, SCLK functions as
the clock input. The SCLK pin defaults to a high-impedance state upon reset, but becomes active after any
MUX connection is made or if the PP is programmed to
IOM-2 Master mode.
SFS
Serial Frame Sync (Input/Output)
Oscillator (OSC)
MCLK
Master Clock (Output)
The MCLK output is available for use as the system
clock for the microprocessor. MCLK is derived from the
12.288-MHz crystal via a programmable divider in the
Am79C30A/32A which provides the following MCLK
output frequencies: 12.288, 6.144, 4.096, 3.072, 1.536,
0.768, and 0.384 MHz.
XTAL1, XTAL2
External Crystal (Output, Input)
XTAL1 and XTAL2 are connected to an external parallel
resonant crystal for the on-chip oscillator. XTAL2 can
also be connected to an external source instead of a
crystal, in which case XTAL1 should be left disconnected. The frequency must be 12.288 MHz, ± 80 ppm.
Peripheral Port (PP)
SBIN
Serial Data (Input/Output)
In SBP mode, SFS outputs an 8-kHz frame synchronization signal. SFS is an output in IOM-2 Master mode,
and an input in IOM-2 Slave mode. As an output, SFS
is active for 8-bit periods. The SFS pin defaults to a
high-impedance state upon reset, but becomes active
after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. For SBP mode, the
active signal state is Low during Idle and 8 kHz in Active Data Only and Active Voice and Data modes.
BCL/CH2STRB
Bit Clock/SBP Channel 2 Strobe
(Output, Three-state)
In SBP mode, this pin provides a strobe during the 8-bit
times of the second 64-kbit/s data channel. In IOM-2
Master mode, this pin provides a 768-kHz bit clock to
aid in the connection of non-IOM-2 devices to the port.
In IOM-2 Slave mode, this pin is high-impedance.
Power Supply Pins
When the Peripheral Port is programmed to SBP mode,
SBIN operates as an input for serial data. When the Peripheral Port is programmed to IOM-2 mode, SBIN
functions as the data input except in the special case of
IOM-2 Slave mode, when it becomes an open-drain
output during part or all of the IOM-2 frame, or when
deactivated.
SBOUT
Serial Data (Input/Output)
When the Peripheral Port is programmed to SBP mode,
SBOUT operates as an output for serial data. When the
PLCC/TQFP Packages
AVCC
+5-V analog power supply, ±5%
AVSS
Analog ground
DVSS
Digital ground
DVCC
+5-V digital power supply, ±5%
Note:
For best performance, decoupling capacitors should be installed between VCC and VSS as close to the chip as possible.
Do not use separate supplies for analog and digital power
and ground connections.
Am79C30A/32A Data Sheet
7
OPERATIONAL DESCRIPTION
Overview of Power Modes
The minimization of power consumption is a key factor
in the design of Terminal Equipment for the ISDN, and
the DSC/IDC circuit employs two basic approaches to
power management:
1. The power consumption of the DSC/IDC circuit itself is managed by using four basic power modes
which allow unused functional blocks to be disabled. The INIT register may be programmed to select Active Voice and Data, Active Data Only, Idle, or
Power-Down mode, depending upon which DSC/
IDC device resources are required at the time.
2. The power consumption of the controlling micro-processor system may be controlled by driving the processor clock with the DSC/IDC circuit MCLK output.
A wide range of MCLK operating frequencies may be
selected, and a special Clock Speed-Up function is
provided which increases the speed of MCLK upon
the occurrence of a key event, without processor intervention. Control of MCLK frequency and Clock
Speed-up is accomplished by programming the INIT
and INIT2 registers, as described later.
Active Voice and Data Mode
In Active Voice and Data mode all functional blocks of
the DSC/IDC circuit are available. Device registers may
be accessed through the MPI, the LIU and DLC are
available, the OSC is running, the Peripheral Port is
available, MUX connections may be made, the Secondary Tone Ringer may be activated, and the MAP is
operational (DSC circuit only).
Active Data Only Mode
Active Data Only mode is similar to Active Voice and
Data mode, except that the MAP (DSC circuit only) is
disabled to reduce system power consumption. This increases the amount of power available for the Secondary Tone Ringer or microprocessor system during the
phases of call setup and teardown, or during a
data-only telephone call.
Idle Mode
Power-Down Mode
Power-Down mode consumes the least power of all the
DSC/IDC power options, and differs from Idle mode in
that all clocks, including the XTAL oscillator, are
stopped. Most functional blocks are disabled, except
for those required to recognize key external events that
will force the DSC/IDC circuit to return to Idle mode.
The Power-Down mode is not available unless the
Power-Down Enable bit is set in the INIT2 register; see
the INIT2 register description for further details.
Entering the Power-Down Mode
The Power-Down mode is entered by appropriate programming of the INIT and INIT2 registers. Selection of
the Power-Down mode causes the DSC/IDCcircuit to
begin an internal countdown of at least 250 MCLK cycles after which the MCLK and XTAL1 outputs are both
stopped and held High, and the XTAL2input will be disregarded. The purpose of this countdown cycle is to
allow the microprocessor time for housekeeping operations before its clock is stopped. If an interrupt causes
the DSC INT pin to go Low during the countdown, the
Power-Down mode bits in the INIT register will be reset
and the countdown will be canceled.
If the LIU is enabled and in any state other than F3 at
the end of the countdown, MCLK is stopped but the oscillator continues to run. This allows the LIU to identify
the incoming signal and either (1) generate an interrupt
and force the DSC/IDC circuit to Idle mode when activation is complete, or (2) move to the F3 state and stop
the oscillator once the line goes idle.
Exiting the Power-Down Mode
Idle mode is the RESET default mode of DSC/IDCcircuit operation, and represents an operational state in
which power consumption is reduced, yet the microprocessor system is operational to program DSC/IDC circuit registers or perform other required background
tasks. Idle mode may also be entered by appropriate
programming of the INIT register.
In Idle mode, the MCLK output is available to drive the
microprocessor system, the MPI is available for programming of DSC/IDC registers, and the LIU is available to initiate or respond to S/T interface activity. The
HSW hookswitch interrupt is also available in Idle mode.
8
Idle mode reduces DSC/IDC circuit power consumption by disabling the MUX, DLC, and MAP functional
blocks. The Peripheral Port is also disabled, except that
an IOM-2 activation request interrupt is possible, and
the SFS and SCLK outputs may still be activated. The
SFS and SCLK outputs are high impedance upon RESET, but become active after any MUX connection is
programmed. The DLC read-only registers are cleared
when the DSC/IDC circuit enters the Idle mode.
The DSC/IDC circuit will exit the Power-Down mode
and enter the Idle mode if any of the following events
occur:
•
The DSC/IDC circuit receives a hardware reset via
the RESET pin.
•
The CS and WR pins are both pulled Low at the
same time, as would occur during a normal write
operation from the microprocessor to the DSC circuit. No data will be transferred by this operation.
•
The HSW hookswitch pin changes state, and the
hookswitch interrupt is enabled.
Am79C30A/32A Data Sheet
•
The LIU receiver is enabled, detects an incoming
signal on the S/T Interface, and achieves activation
as indicated by a transition to state F7. Both the INT
pin and the F7 transition interrupt must be enabled
for Power-Down mode to be exited. If the LIU is enabled, it may restart the oscillator so that it can identify the activity on the interface. If the activity is
determined to be noise, the LIU will stop the oscillator and continue to monitor the line without an interrupt or returning to Idle mode.
•
The IOM-2 Interface is enabled as a clock master
and the SBIN input pin goes Low. This indicates that
a slave device wants to activate the IOM-2 Interface
and communicate with the DSC circuit. Both the INT
pin and the IOM-2 timing request interrupts must be
enabled for Power-Down mode to be exited.
•
The IOM-2 Interface is enabled as a clock slave and
the SCLK input pin goes High. This indicates that
the master device is activating the IOM-2 Interface
and the DSC circuit must wake up in order to monitor the data. Both the INT pin and the IOM-2 timing
request interrupts must be enabled for Power-Down
mode to be exited.
If the DSC/IDC circuit is awakened by any condition
other than RESET, the MCLK output will be restored to
its previously programmed frequency, and will not generate any shortened or spurious output cycles. If the
DSC/IDC circuit is revived by RESET, MCLK will default
to its normal 6.144-MHz rate. The DSC/IDC circuit provides a minimum of two MCLK cycles prior to activating
the interrupt pin when exiting Power-Down mode.
There are two events that will trigger the clock
speed-up function:
1. The DLC receive FIFO threshold has been reached;
or,
2. a second packet begins to be received while data
from a prior packet is still in the receive FIFO.
The second packet case requires provision of an interrupt; see the DLC register section for further information. The clock speed-up function allows the user to
program a very slow MCLK frequency using INIT2
when D-channel activity is minimal. If a burst of activity
is seen on the D channel and it exceeds the programmed threshold of the receive FIFO or threatens to
overrun the receive FIFO status buffers, MCLK will instantly toggle back to the higher frequency programmed in the INIT register. This eliminates the
latency incurred if an interrupt has to be serviced to
change the clock speed, and allows the overall system
power to be reduced during typical voice connections.
Note that automatic clock speed-up will not function unless at least one of the associated interrupts are enabled so the processor can be informed that the clock
speed has been altered.
Global Register Functions
INIT Register (INIT) default = 00H
Address = Indirect 21 Hex, Read/Write
Table 1.
INIT Register
Bit
MCLK Frequency Control
7
The MCLK frequency selection bits in the INIT register
are unchanged from Revision D. However, additional
MCLK frequencies are available by programming bits in
the INIT2 register. No shortened or spurious clock
pulses that might disrupt the external microprocessor
will result when the MCLK frequency is changed.
In order to reduce the probability of errant software disrupting system operation, the INIT2 register requires
two consecutive writes before the value will be entered
into the register. Note that there will be no MCLK countdown as is the case for entering Power-Down mode if
INIT2 is programmed to cause MCLK to STOP, and
there will be no shortened or spurious MCLK pulses.
MCLK Clock Speed-up Function
A programmable automatic MCLK speed-up option is
provided that will force a hardware reset of INIT2 bits
3-0, which will cause the MCLK frequency to be restored to the value programmed in the INIT register.
6
5
4 3
1
0 Function
X X
X X X X 0
0 Idle mode
X X
X X X X 0
1 Active Voice and Data mode
X X
X X X X 1
0 Active Data Only mode
X X
X X X X 1
1 Power-Down mode
X X
X X X 0 X X INT output enabled
X X
X X X 1 X X INT output disabled
X X
0
0
0 X X X MCLK frequency = 6.144 MHz
X X
0
0
1 X X X MCLK frequency = 12.288 MHz
X X
0
1
0 X X X MCLK frequency = 3,072 MHz
X X
0
1
1 X X X MCLK frequency = 6.144 MHz
X X
1
0
0 X X X MCLK frequency = 4.096 MHz
X X
1
0
1 X X X MCLK frequency = 6.144 MHz
X X
1
1
0 X X X MCLK frequency = 6.144 MHz
X X
1
1
1 X X X MCLK frequency = 6.144 MHz
X 0
X X X X X X DLC receiver abort disabled
X 1
X X X X X X DLC receiver abort enabled
0 X
X X X X X X DLC transmitter abort disabled
1 X
X X X X X X DLC transmitter abort enabled
Am79C30A/32A Data Sheet
2
9
RESET Operation
INIT2 Register (INIT2) default = 00H
Address = Indirect 20 Hex, Read/Write
A special write procedure must be followed in order to
modify the contents of the INIT2 Register, since the
INIT2 Register includes control bits which could result
in the stopping of the microprocessor clock. This procedure greatly reduces the probability of errant software
disabling the system, and is described as follows:
1. Write the INIT2 address to the Command Register.
2. Write to the Data Register (INIT2 is not yet updated).
3. Write the INIT2 address to the Command Register.
4. Write to the Data Register (INIT2 is updated).
The writes must take place without any intervening indirect accesses to the DSC/IDC circuit.
Table 2.
INIT2 Register
Bit
7
6
5
4
3
2
1
0 Function
0 0
X X X X X X Reserved, must be written to 0;
READs are undefined
0 0
0 X X X X X Power-Down disabled; writing
11 to the INIT Register will put
the DSC/IDC circuit into Idle
mode
0 0
1 X X X X X Power-Down enabled; writing
11 to the INIT Register will put
the DSC/IDC circuit into
Power-Down mode
0 0
X 0 X X X X Multiframe Interrupt filter
disabled
0 0
X 1 X X X X Multiframe Interrupt filter
enabled (see LIU section for
detailed description)
0 0
X X X 0 X X Clock speed-up option disabled
0 0
X X X 1 X X Clock speed-up option enabled;
if set, this register bit will be
cleared when the DLC FIFO
receive threshold or second
packet received interrupt is
triggered
0 0
X X X 0
0
0 MCLK frequency determined by
INIT Register
0 0
X X X 0
0
1 MCLK frequency is 1.536 MHz
0 0
X X X 0
1
0 MCLK frequency is 768 kHz
0 0
X X X 0
1
1 MCLK frequency is 384 kHz
0 0
X X X 1
0
0 MCLK stopped in High state
0 0
X X X 1
0
1 Reserved
0 0
X X X 1
1
0 Reserved
0 0
X X X 1
1
1 Reserved
10
The Am79C30A/32A can be reset by driving the
RESET pin High. When power is first supplied to the
DSC/IDC circuit, a reset must be performed. This initializes the DSC/IDC circuit to its default condition as
defined in Table 3.
Table 3.
Reset Pin Conditions
Pin Name
State Following RESET
D7–D0
High Impedance
MCLK
6.144 MHz
INT
Logical 1
SBOUT
High Impedance
SFS
High Impedance
SCLK
High Impedance
LS1, LS2
High Impedance
EAR1
High Impedance
EAR2
High Impedance
AREF
High Impedance
LOUT1
High Impedance
LOUT2
High Impedance
Receive and Transmit Abort Commands
The microprocessor has the option via INIT Register
bits 6 and 7 to abort the receive and transmit D-channel
packets. When the microprocessor sets one of these
bits, the Am79C30A/32A aborts the respective operation. The frame abort sequence is defined in greater
detail later. (See the Data Link Controller section on
page 36.)
Interrupt Handling
The Am79C30A/32A generates either no interrupt or
only one interrupt every 125 µs. Once asserted, INT remains active until the microprocessor responds by interrogating the Am79C30A/32A’s Interrupt Register (IR)
(see Table 4). Reading the IR in response to an activated INT pin deactivates the INT pin and clears the IR.
If an event causing an interrupt occurs while the IR is
being read by the microprocessor, the effect of the
event is held until the microprocessor has completed its
read cycle. A reset clears all conditions causing interrupts.
Bits 0, 1, and 4 of the IR, if set, advise the microprocessor that the respective buffer is ready for reading or
writing. If bit 0 is set due to an empty buffer, the D-channel Transmit buffer must be serviced within 375 µs. If bit
1 is set and the D-channel Receive buffer is full, the
buffer must be serviced within 425 µs. This is to prevent
erroneous data transfers causing transmitter underrun
and receiver overrun errors. If bit 4 is set then the Bb or
Am79C30A/32A Data Sheet
Bc buffers must be accessed within 122.4 µs. This is to
prevent erroneous data transfers. Only one interrupt is
used to signal accessibility for both B channels of the S
Interface. Since the data transfer must occur synchronously to the S Interface, any data access to either Bb
or Bc or both must be made within the122.4 µs limit.
Note that even though only a single interrupt is issued,
either or both S-Interface B channels must be serviced.
IR bits 2, 3, 5, 6, and 7, if set, indicate that a bit has
been set in the associated status or error register. All of
the interrupts generated by the Am79C30A/32A can be
individually disabled. In the case of IR bit 7, the interrupt can also be masked by setting PPIER bit 7 to 0.
DMR1, DMR2, DMR3, LMR2, MCR4, and MF control
the mask conditions that affect the INT pin. The INT pin
is activated only by interrupts that are not disabled. The
Interrupt Register reflects the status of enabled interrupts. The INT pin can be disabled by setting INIT Register bit 2 to a logical 1.
The Am79C30A/32A has facilities that allow the microprocessor to read the status registers (status update is
inhibited during status read) or the IR at any time during functional operation.
Am79C30A/32A Data Sheet
11
Table 4.
Bit
Interrupt Generated/Action Required
Interrupt Mask
0
D-channel transmit threshold interrupt/load D-channel Transmit buffer
DMR1 bit 0
1
D-channel receive threshold interrupt/read D-channel Receive buffer
DMR1 bit 1
2
3
D-channel status interrupt/read DSR1
Source
Cause
DSR1 bit 0
Valid Address (VA) or End of Address (EOA)
DMR3 bit 0
DSR1 bit 1
When a closing flag is received or a receive error occurs
DMR1 bit 3
DSR1 bit 6
When a closing flag is transmitted DMR3 bit 1
DMR3 bit 1
D-channel error interrupt/read DER and DSR2 bit 2
Source
Cause
DER bit 0
Current received packet has been aborted
DMR2 bit 0
DER bit 1
Non-integer number of bytes received
DMR2 bit 1
DER bit 2
Collision abort detected
DMR2 bit 2
DER bit 3
FCS error
DMR2 bit 3
DER bit 4
Overflow error
DMR2 bit 4
DER bit 5
Underflow error
DMR2 bit 5
DER bit 6
Overrun error
DMR2 bit 6
DER bit 7
Underrun error
DMR2 bit 7
DSR2 bit 2
Receive packet lost
DMR3 bit 6
4
Bb or Bc byte available or buffer empty interrupt/read or write Bb or Bc buffers
5
LIU status interrupt/read LSR
6
7
12
Format of the Interrupt Register (IR), Read Only
MCR4 bit 3
Source
Cause
LSR bit 3
Change of state to F3
LMR2 bit 3
LSR bit 4
Change of state from/to F7
LMR2 bit 6
LSR bit 5
Change of state from/to F8
LMR2 bit 4
LSR bit 7
HSW change of state
LMR2 bit 5
D-channel status interrupt/read DSR2
Source
Cause
DSR2 bit 0
Last byte of received packet
DMR3 bit 2
DSR2 bit 1
Receive byte available
DMR3 bit 3
DSR2 bit 3
Last byte transmitted
DMR3 bit 4
DSR2 bit 4
Transmit buffer available
DMR3 bit 5
DSR2 bit 7
Start of second packet
EFCR bit 1
Multiframe or PP interrupt/read MFSB and PPSR
Source
Cause
MFSB bit 5
S-data available
MF bit 1
MFSB bit 6
Q-bit buffer empty
MF bit 2
MFSB bit 7
Multiframe change of state (in/out of sync)
MF bit 3
PPSR bit 0
Monitor receive, data available
PPIER bit 0
PPSR bit 1
Monitor transmit, buffer available
PPIER bit 1
PPSR bit 2
Monitor EOM received
PPIER bit 2
PPSR bit 3
Monitor abort received
PPIER bit 3
PPSR bit 4
C/I channel 0, data change
PPIER bit 4
PPSR bit 5
C/I channel 1, data change
PPIER bit 5
PPSR bit 6
IOM-2 timing request
PPIER bit 6
Am79C30A/32A Data Sheet
FUNCTIONAL DESCRIPTION
Microprocessor Interface (MPI)
Direct Registers
The Am79C30A/32A can be connected to any general
purpose 8-bit microprocessor via the MPI. The MCLK
from the Am79C30A/32A can be used as the clock for
the microprocessor. The MPI is an interrupt-driven interface containing all the circuitry necessary for access
to the internal programmable registers, status registers, coefficient RAM, and transmit/receive buffers.
MPI External Interface
External connections to the MPI are shown in Table 5.
Table 5.
MPI External Interface
Name
Direction
Function
D7–D0
Bidirectional
Data Bus
A2–A0
Inputs
Address Line
RD
Input
Read Enable
WR
Input
Write Enable
CS
Input
Chip Select
RESET
Input
Initialization
INT
Output
Interrupt
Table 6.
Access to the Direct Registers of the Am79C30A/32A
is controlled by the state of the CS, RD, WR, A2, A1,
and A0 input pins, as defined below by Table 6.
Indirect Registers
To read from or write to any of the Indirect Registers, an
indirect address command is first written to the Command Register (CR). One or more data bytes may then
be transferred to or from the selected register through
the Data Register (DR).
Registers within certain groups can be accessed
quickly by using internal circuitry which automatically
increments the indirect value. In Table 7, the bytes
transferred numbers are the number of bytes which are
read or written to the DR after the CR has been loaded.
Whenever the CR is loaded, any previous commands
are automatically terminated.
Direct Register Access Guide
CS
RD
WR
A2
A1
A0
Register(s) Accessed
Mode
0
1
0
0
0
0
Command Register (CR)
W
0
0
1
0
0
0
Interrupt Register (IR)
R
0
1
0
0
0
1
Data Register (DR)
W
0
0
1
0
0
1
Data Register (DR)
R
0
0
1
0
1
0
D-channel Status Register 1 (DSR1)
R
0
0
1
0
1
1
D-channel Error Register (DER) (2-byte FIFO)
R
0
1
0
1
0
0
D-channel Transmit buffer (DCTB) (8- or 16-byte FIFO)
W
0
0
1
1
0
0
D-channel Receive buffer (DCRB) (8- or 32-byte FIFO)
R
0
1
0
1
0
1
Bb-channel Transmit buffer (BBTB)
W
0
0
1
1
0
1
Bb-channel Receive buffer (BBRB)
R
0
1
0
1
1
0
Bc-channel Transmit buffer (BCTB)
W
0
0
1
1
1
0
Bc-channel Receive buffer (BCRB)
R
0
0
1
1
1
1
D-channel Status Register 2 (DSR2)
R
1
X
X
X
X
X
No access (X = logical 0 or 1)
—
Note:
The RD and WR signals must never both be Low under normal operating conditions.
Am79C30A/32A Data Sheet
13
Table 7.
Operation
Block
Register
Indirect Register Access Guide
Register
Number
Indirect Name
Mode Address
INIT
Initialization Register
1
INIT
R/W
INIT
Initialization Register 2
2
INIT2
LIU
LIU Status Register
1
LSR
LIU
LIU Priority Register
2
LIU
LIU Mode Register 1
3
Byte Sequence
21H
One byte transferred
R/W
20H
One byte transferred
R
A1H
One byte transferred
LPR
R/W
A2H
One byte transferred
LMR1
R/W
A3H
One byte transferred
One byte transferred
14
LIU
LIU Mode Register 2
4
LMR2
R/W
A4H
LIU
—
5
Perform 2–4
–
A5H
One byte transferred
LIU
Multiframe Register
6
MF
R/W
A6H
One byte transferred
LIU
Multiframe S-bit/Status Register
7
MFSB
R
A7H
One byte transferred
LIU
Multiframe Q-bit buffer
8
MFQB
W
A8H
One byte transferred
MUX
MUX Control Register 1
1
MCR1
R/W
41H
One byte transferred
MUX
MUX Control Register 2
2
MCR2
R/W
42H
One byte transferred
MUX
MUX Control Register 3
3
MCR3
R/W
43H
One byte transferred
MUX
MUX Control Register 4
4
MCR4
R/W
44H
One byte transferred
MUX
—
5
Perform 1–4
—
45H
MCR1, 2, 3, 4
MAP
X filter Coefficient Register
1
X Coeff.
R/W
61H
h0 LSB, h0 MSB...h7 MSB
MAP
R filter Coefficient Register
2
R Coeff.
R/W
62H
h0 LSB, h0 MSB...h7 MSB
MAP
GX Gain Coefficient Register
3
GX Coeff.
R/W
63H
LSB, MSB
MAP
GR Gain Coefficient Register
4
GR Coeff.
R/W
64H
LSB, MSB
MAP
GER Gain Coefficient Register
5
GER Coeff.
R/W
65H
LSB, MSB
MAP
Sidetone Gain Coefficient Register
6
STG Coeff.
R/W
66H
LSB, MSB
MAP
Frequency Tone Generator Register
1, 2
7
FTGR1, FTGR2
R/W
67H
FTGR1, 2
MAP
Amplitude Tone Generator Register
1, 2
8
ATGR1,ATGR2
R/W
68H
ATGR1, 2
MAP
MAP Mode Register 1
9
MMR1
R/W
69H
One byte transferred
MAP
MAP Mode Register 2
10
MMR2
R/W
6AH
One byte transferred
MAP
—
11
Perform 1–10
—
6BH
46 bytes loaded 1–10
MAP
MAP Mode Register 3
12
MMR3
R/W
6CH
One byte transferred
MAP
Secondary Tone Ringer Amplitude
13
STRA
R/W
6DH
One byte transferred
MAP
Secondary Tone Ringer Frequency
14
STRF
R/W
6EH
One byte transferred
MAP
Transmit Peak Register
15
PEAKX
R
70H
One byte transferred
MAP
Receive Peak Register
16
PEAKR
R
71H
One byte transferred
MAP
—
17
Perform 15–16
R
72H
One byte transferred
DLC
First Received Byte Address
Registers 1, 2, 3
1
FRAR 1, 2, 3
R/W
81H
FRAR1, 2
DLC
Second Received Byte Address
Registers 1, 2, 3
2
SRAR1, 2, 3
R/W
82H
SRAR1, 2
DLC
Transmit Address Register
3
TAR
R/W
83H
LSB, MSB
DLC
D-channel Receive Byte Limit
Register
4
DRLR
R/W
84H
LSB, MSB
DLC
D-channel Transmit Byte Count
Register
5
DTCR
R/W
85H
LSB, MSB
Am79C30A/32A Data Sheet
Table 7.
Indirect Register Access Guide (Continued)
Operation
Block
Register
Register
Number
Indirect Name
D-channel Mode Register 1
6
DMR1
R/W
DLC
D-channel Mode Register 2
7
DMR2
R/W
87H
One byte transferred
DLC
—
8
Perform 1–7
—
88H
4 bytes loaded 1–7
DLC
D-channel Receive Byte Count
Register
9
DRCR
R
89H
LSB, MSB
DLC
Random Number Generator
Register
10
RNGR1 (LSB)
R/W
8AH
One byte transferred
DLC
Random Number Generator
Register
11
RNGR2 (MSB)
R/W
8BH
One byte transferred
DLC
First Received Byte Address
Register 4
12
FRAR4
R/W
8CH
One byte transferred
DLC
Second Received Byte Address
Register 4
13
SRAR4
R/W
8DH
One byte transferred
DLC
D-channel Mode Register 3
14
DMR3
R/W
8EH
One byte transferred
DLC
D-channel Mode Register 4
15
DMR4
R/W
8FH
One byte transferred
DLC
—
16
Perform 12–15
—
90H
FRAR4, SRAR4, DMR3,
DMR4
DLC
Address Status Register
17
ASR
R
91H
One byte transferred
DLC
Extended FIFO Control Register
18
EFCR
R/W
92H
One byte transferred
DLC
Mode Address
86H
Byte Sequence
One byte transferred
PP
Peripheral Port Control Register 1
1
PPCR1
R/W
C0H
One byte transferred
PP
Peripheral Port Status Register
2
PPSR
R
C1H
One byte transferred
PP
Peripheral Port Interrupt Enable
Register
3
PPIER
R/W
C2H
One byte transferred
PP
Monitor Transmit Data Register
4
MTDR
W
C3H
One byte transferred
PP
Monitor Receive Data Register
5
MRDR
R
C3H
One byte transferred
PP
C/I Transmit Data Register 0
6
CITDR0
W
C4H
One byte transferred
PP
C/I Receive Data Register 0
7
CIRDR0
R
C4H
One byte transferred
PP
C/I Transmit Data Register 1
8
CITDR1
W
C5H
One byte transferred
PP
C/I Receive Data Register 1
9
CIRDR1
R
C5H
One byte transferred
PP
Peripheral Port Control Register 2
10
PPCR2
R/W
C8H
One byte transferred
PP
Peripheral Port Control Register 3
11
PPCR3
R/W
C9H
One byte transferred
Line Interface Unit (LIU)
The LIU connects to the four-wire S Interface through a
pair of isolation transformers, one for the transmit and
one for the receive direction, as shown in Figure 1.
The receiver section of the LIU consists of a differential
receiver, circuitry for bit timing recovery, circuitry for detecting High and Low marks, and a frame recovery circuit for frame synchronization. The receiver converts
the received pseudo-ternary coded signals to binary
before delivering them to the other blocks of the
Am79C30A/32A. It also performs collision detection (Eand D-bit comparison) per the CCITT recommenda-
tions so several TEs can be connected to the same S
Interface.
The transmitter consists of a binary to pseudo-ternary
encoder and a differential line driver which meets the
CCITT recommendations for the S Interface.
The Am79C30A/32A can establish multiframe synchronization, receive S bits, and transmit Q bits synchronized to the received frame.
External Interface
The LIU can be connected to both point-to-point and
point-to-multipoint configurations at the CCITT S reference point. The point-to-point configuration consists of
one TE connected to the NT or PABX linecard. The
Am79C30A/32A Data Sheet
15
point-to-multipoint configuration can have multiple TEs
connected to one NT.
Line Code
Pseudo-ternary coding is used for both transmitting
and receiving over the S Interface. In this type of coding, a binary 1 is represented by a space (zero voltage),
and a binary 0 is represented by a High mark or a Low
mark. Two consecutive binary 0s are represented by alternate marks to reduce DC offset on the line. A mark
followed, either immediately or separated by spaces,
by a mark of the same polarity, is defined as a code violation. Code violations are used to identify the boundaries of the frame.
Note:
The DSC defines “Any Signal” as any frame with at least
three marks above receive threshold.
Frame Structures
In both transmit and receive directions, the bits are
grouped into frames of 48 bits each. The frame structure is identical for both point-to-point and point-to-multipoint configurations. Each frame transmitted at 4 kHz
consists of several groups of bits.
Multiframing
If multiframing is enabled, the Am79C30A/32A recognizes and establishes multiframe synchronization
based on the monitoring of the FA (Q-bit control) and M
(M-bit control) bits. The Am79C30A/32A also receives
and compiles S bits, and transmits Q bits synchronized
to the received frame.
Establishment of Multiframe Synchronization
When the enable multiframe synchronization bit (bit 0
of the Multiframe Register) is set and the LIU is in either
state F6 or F7, the LIU monitors the FA (Q-bit control)
and M (M-bit control) bits. When three consecutive multiframes with the M bits and FA bits set as defined in
Table 8 are received, the multiframe synchronized bit
(bit 7 of the Multiframe Register) and multiframe
change of state bit (bit 7 of the Multiframe S bit/Status
buffer) are set. Note that S-bit data is received, compiled, and transferred to the user after attaining synchronization at the start of the next multiframe.
S-Bit Reception
The default operation of the DSC/IDC circuit is that the
LIU will receive and pass multiframe data to the user in
5-bit increments four times per multiframe, regardless
of the value of the data. After multiframe synchronization has been requested and established the microprocessor can read the Multiframe S bit/Status buffer
(MFSB) once the S-bit available bit (MFSB bit 5) is set.
The S-data available bit is set to a logical 1 when the
Am79C30A/32A has received five S bits (one S bit per
S-interface frame) synchronized to the setting of the
FA -bit to a logical 1 and transferred them into the
MFSB. Once the S-bit available bit is set, the MFSB
must be accessed within 1.25 ms or succeeding S data
will be lost.
Subsequent to the original definition of the DSC/IDC
circuit, the CCITT has defined a structure for the 20
multiframe bits, which specifies five 4-bit channels. Furthermore, the idle code for these channels has been
defined as 0000. An enhanced mode of multiframe reception has been included, which may be enabled by
setting INIT2 bit 4 to a 1. This enhanced mode reduces
processor overhead by generating an interrupt only
upon the reception of a non-zero S-channel word.
INIT2 bit 4 will be automatically cleared by hardware
when the five received data bits in the MFSB are not all
0s, as long as MF bit 1 (interrupt enable) is set. This allows subsequent valid all-zero words to be received.
Furthermore, when the first five S bits of the multiframe
are loaded into the MFSB, bit 4 of the MF register will
be set, which allows identification of the position of received words within the multiframe.
S
Line Drivers
Frame
Recovery
To
MUX
and
DLC
Decoder
Binary
to
Pseudo-ternary
Coder
Slicer
Timing
Recovery
Balanced
Receiver
09893H-2
Figure 1.
16
LIU Block Diagram
Am79C30A/32A Data Sheet
Table 8.
Multiframing Structures
Frame Number
NT-to-TE Q Control Bit FA
NT-to-TE M Bit (M)
NT-to-TE S Bit (S)
TE-to-NT FA Bit (Q Bit)
1
1
1
SC11
Q1
2
0
0
SC21
0
3
0
0
SC31
0
4
0
0
SC41
0
5
0
0
SC51
0
6
1
0
SC12
Q2
7
0
0
SC22
0
8
0
0
SC32
0
9
0
0
SC42
0
10
0
0
SC52
0
11
1
0
SC13
Q3
12
0
0
SC23
0
13
0
0
SC33
0
14
0
0
SC43
0
15
0
0
SC53
0
16
1
0
SC14
Q4
17
0
0
SC24
0
18
0
0
SC34
0
19
0
0
SC44
0
20
0
0
SC54
0
1
1
1
SC11
Q1
2
0
0
SC21
0
etc.
Transmission of Q bits
Loss of Multiframe Synchronization
The microprocessor can load the Multiframe Q-bit
buffer (MFQB) once the Q-bit buffer empty bit (bit 6 of
the Multiframe S bit/Status buffer) is set. The Q-bit
buffer empty bit is set to a logical 1 at reset or when
data that has been written to the Multiframe Q-bit buffer
is transferred to the LIU. The Q-bit buffer empty bit is
cleared to a logical 0 when the Multiframe S-bit/Status
buffer is read. After multiframing has been requested
and established, the Am79C30A/32A transfers the data
written into the Q-bit Register to the LIU, synchronized
to the multiframe, irrespective of the receipt of valid
Q-control bits. If the microprocessor does not reload
the Q-bit Register for retransmissions, the Q-bit pattern
is repeated in the next multiframe.
The Am79C30A/32A continuously monitors the FA
(Q-bit control) and the M bits to ensure multiframe synchronization. Once multiframe synchronization is established, multiframe synchronization is lost if three
consecutive invalid multiframes are received, or the LIU
is no longer in state F6 or F7, or multiframing is disabled. When loss of multiframe synchronization occurs,
bit 7 of the Multiframe Register is set to a logical 0, and
bit 7 of the Multiframe S bit/Status buffer is set to a
logical 1. The Am79C30A/32A also terminates the reception of S bits and transmission of Q bits until multiframing synchronization is re-established.
If multiframing is enabled but multiframe synchronization is not established, the LIU transmits the value
loaded in MFQB bit 4 in all Q bits. The default value of
MFQB bit 4 is a logical 0 which satisfies the CCITT recommendations. When synchronization is achieved, the
contents of MFQB bits 3 to 0 are transmitted according
to Table 8.
HSW
The hookswitch circuitry on the DSC circuit provides the
attached microprocessor with a way of converting an
external mechanical hookswitch into a software status
condition capable of generating an interrupt. Debounce
and glitch rejection are provided internal to the DSC circuit. The logic rejects glitches less than 162 ns and provides debounce of 16 ms. HSW status reporting is
disabled after RESET. It is enabled by any of the following: taking the device out of Idle mode, a write to a MUX
Control Register (MCR3–MCR1), or unmasking the
HSW interrupt.
Am79C30A/32A Data Sheet
17
LIU Registers
The LIU contains the registers shown in Table 9.
Table 9.
LIU Registers
as 1, F4 as 2, and so on, where bit 0 is the LSB. The
LIU interrupts the microprocessor via bit 4 of the LSR
when activation has been achieved (that is, when the
LIU moves to state F7 upon receipt of INFO 4). During
reset the LSR is 0.
LIU Status Register
1
LSR
LIU Priority Register
1
LPR
LIU Mode Registers
2
LMR1, LMR2
Multiframe Register
1
MF
Even thou gh th e L IU Status R eg iste r ( LSR ) is
read-only, no default value upon power-up is given due
to the uncertain state of bit 6 (Hookswitch State). Following RESET, the LIU State is F2 and the HSW bit reflects the HSW pin, producing a power-up value of
either 00H or 40H.
Multiframe S-bit/Status
Register
1
MFSB
LIU D-Channel Priority Register (LPR), Read/Write
Multiframe Q-bit buffer
1
MFQB
The LPR contains the priority level for D-channel access. Its default value after reset is 0.
Registers
No./Registers Mnemonic
3
Change of state to F3
If LMR2 bit 3 = 1
4
Change of state from/to F7
If LMR2 bit 6 = 1
The D-channel access procedure of the Am79C30A/
32A uses the priority level programmed in the LPR. The
priority mechanism defined by the CCITT I-series recommendations is fully implemented if the LPR is programmed via the microprocessor to conform to the
priority class of the Layer-2 frame to be transmitted.The
LPR has 16 possible programmable priority levels. The
priority levels are numbered 0–15. Priority Level 0 corresponds to counting eight 1s in the echo channel, priority Level 1 corresponds to counting ten 1s in the echo
channel, priority Level 2 corresponds to counting
twelve 1s, etc. The DSC circuit automatically handles
transitions between the programmed priority level n
and the associated odd value n + 1. The priority is
incremented following a successfully transmitted
packet, and decremented when the higher count has
been satisfied.
5
Change of state from/to F8
If LMR2 bit 4 = 1
The LPR format is shown in Table 11.
6
HSW state
7
HSW change of state
LIU Status Register (LSR), Read Only
Address = Indirect A1H
The LSR format is shown in Table 10.
Table 10.
LIU Status Register
Bit
Logical 1
0-2
Binary values 000 through 110
represent the LIU activation
circuitry’s current state (F2
through F8, respectively) bit 2 is
MSB
Generates
Interrupt
No
No
If LMR2 bit 5 = 1
When the microprocessor reads the LSR, bits 3, 4, 5,
and 7 are cleared. The other bits retain the current status of the LIU. bits 0 to 2 are defined such that state F2
(see CCITT I.430 state matrix tables) is coded as 0, F3
18
Table 11.
Bits
LIU Priority Register
Description
3, 2, 1, 0
D-channel access priority level bit 0 is LSB
7, 6, 5, 4
Reserved, reads logical 0
Am79C30A/32A Data Sheet
LIU Mode Register (LMR1), Read/Write
Address = Indirect A3H
LMR1 is defined in Table 12.
Table 12.
Bit
LIU Mode Register 1
Logical 1
Logical 0 (default value)
0
Enable B1 transmit
Disable B1 transmit
1
Enable B2 transmit
Disable B2 transmit
2
Disable F transmit
Enable F transmit
3
Disable FA transmit
Enable FA transmit
4
Activation request
No activation request
5
Go from F8 to F3
No transition
6
Enable receiver/transmitter
Disable receiver/transmitter
7
Reserved; must be set to logical 0
Reserved; must be set to logical 0
Notes:
The F and FA bits in LMR1 (bits 2 and 3) should be enabled during the activation procedure so the Am79C30A/32A can respond
with INFO 3.
LMR1 bit 4 is used to transfer the signals PH-AR and Expiry of Timer from the microprocessor to the LIU (see CCITT I.430 state
diagram—activation request). PH-AR is defined as bit 4 being a logical 1 and Expiry of Timer is defined as the transition of bit 4
from a logical 1 to a logical 0. This bit must not be set until the LIU, as reflected in the LSR, is in state F3, F6, or F7 and the
receiver has been enabled for a minimum of 250 µs.
LMR1 bit 6 is primarily used to disable the receiver when the terminal does not require access to the S Interface signals. This bit
is cleared by reset and must be written to logical 1 in order to receive activation from the S Interface, or to request activation.
LIU Mode Register 2 (LMR2), Read/Write
Address = Indirect A4H
LMR2 is used to select the operations found in Table 13.
Table 13.
Bit
LIU Mode Register 2
Logical 1
Logical 0 (Default Value)
0
D-channel loopback at Am79C30A/32A enable
D-channel loopback at Am79C30A/32A disable
1
D-channel loopback at LIU enable
D-channel loopback at LIU disable
2
D-channel back-off disable
D-channel back-off enable
3
F3 change of state interrupt enable
F3 change of state interrupt disable
4
F8 change of state interrupt enable
F8 change of state interrupt disable
5
HSW interrupt enable
HSW interrupt disable
6
F7 change of state interrupt enable
F7 change of state interrupt disable
7
Reserved; must be set to logical 0
Reserved; must be set to logical 0
Am79C30A/32A Data Sheet
19
The three D-channel loopback controls defined in
LMR2 bits 0, 1, and 2 are explained below:
Bit 0, D-channel loopback at Am79C30A/32A enable:
Am79C30A
D
S
D
Bit 1, D-channel loopback at LIU enable:
Am79C30A
NT/PABX
D
S
D
NT/PABX
MPI
D
D
This local loopback is provided for local testing. Data on
the incoming D channel is ignored. The data from the
microprocessor is processed by the DLC and then
looped back to the microprocessor.
E
Bit 2, D-channel back-off disable:
This remote loopback is provided for maintenance purposes from the NT’s perspective. The NT transmits
D-channel bits to the Am79C30A/32A where they are
internally looped (with the Data Link Controller) and
transmitted back to the NT. The incoming D-channel
data can be accessed by the microprocessor; however,
the microprocessor cannot send data on the outgoing
D channel.
Any difference between the transmitted D-channel bits
a n d t h e r e c e i ve d E - c h a n n e l b i t s t o / f r o m t h e
Am79C30A/32A (normally detected as an error which
halts the transmission) is ignored, thereby allowing the
transmission to continue.
Am79C30A
D
S
E
D
E
This loopback is provided for maintenance purposes
from the TE’s perspective. The Am79C30A/32A transmits D-channel bits to the NT where they are looped
and transmitted back to the Am79C30A/32A in the E
channel. The operation is normal except differences
between the D and E channels do not halt the transmission.
Multiframe Register (MF), Read/Write
Address = Indirect A6H
Table 14.
Bit
Logical 0 (Default Value)
0
Enable Multiframe sync
Disable Multiframe sync
1
Enable S-data available interrupt
Disable interrupt
2
Enable Q-bit buffer empty interrupt
Disable interrupt
3
Enable Multiframe change of state interrupt
Disable interrupt
4
First subframe
Not first subframe
Not used, reads logical 0
Not used, reads logical 0
Multiframe synchronized (read only)
Multiframe not synchronized (read only)
7
20
Multiframe Register
Logical 1
5, 6
NT/PABX
Am79C30A/32A Data Sheet
Multiframe S-bit/Status Buffer (MFSB), Read Only
Address = Indirect A7H
The logical channels available at the MUX are shown in
Figure 2, They are:
1. From/to the LIU channels B1 and B2
Table 15.
Multiframe S-Bit/Status Buffer
2. From/to the MAP channel Ba
Description
Generates Interrupt
3. From/to the MPI channels Bb and Bc
0
S1
No
4. From/to the PP channels Bd, Be, and Bf
1
S2
No
2
S3
No
3
S4
No
4
S5
No
For any specific application, the MUX can be programmed by the microprocessor to route any three
B- ch an n el p or ts to a ny o the r thr ee B- ch a nn e l
ports.Programmable bidirectional bit reversal is provided for both of the MPI data channels Bb and Bc.
5
S-data available
If MF bit 1 = 1
6
Q-bit buffer empty
If MF bit 2 = 1
7
Multiframe change of state If MF bit 3 = 1
Bit
The MFSB reset default value is 40H.
Multiframe Q-bit Buffer (MFQB), Write Only
Address = Indirect A8H
Table 16.
Bit
Multiframe Q-Bit Buffer
Description
0
Q1 (default = 1)
1
Q2 (default = 1)
2
Q3 (default = 1)
3
Q4 (default = 1)
4
Q-bit value when multiframing enabled but
synchronization not achieved (default = 0)
5, 6, 7
MUX Control Registers 1, 2, and 3
(MCR1, MCR2, and MCR3), Read/Write
Addresses = Indirect 41H, 42H, 43H
The MUX can support three bidirectional paths. The
contents of the MUX Control Registers MCR1, MCR2,
and MCR3 direct the flow of data between the eight
MUX logical B channels (see Figure 2). These three
MCRs are programmed to connect any two B-channel
ports together by writing the appropriate channel code
into an MCR. These MCRs have the same format,
where bits 7–4 indicate port 1 and bits 3–0 indicate port
2. In each of these three MCR registers, the channel
codes found in Table 18 are used for both ports 1 and 2.
Table 18.
Not used
MCR Register Channel Codes
Code
Channel
0000
No connection (default value)
0001
B1 (LIU)
0010
B2 (LIU)
Multiplexer (MUX)
0011
Ba (MAP)
The MUX contains the registers found in Table 17.
0100
Bb (MPI)
0101
Bc (MPI)
0110
Bd (PP channel 1)
Mnemonic
0111
Be (PP channel 2)
MCR1, MCR2, MCR3,
MCR4
1000
Bf (PP channel 3)
Table 17.
Register
MUX Control
Registers
MUX Registers
No./Registers
4
The Multiplexer is used to selectively route 64-Kbit/s
full-duplex B channels between the LIU (Line Interface
Unit), MAP (Main Audio Processor), MPI (Microprocessor Interface), and the PP (Peripheral Port).
For example, to connect B1(LIU) with Bb (MPI) and B2 (LIU)
with Ba (MAP), the contents of the MCRs would be:
Port 1
Port 2
Register 7 6 5 4 3 2 1 0 Channel Connection
MCR1
0 0 0 1 0 1 0 0 B1 (LIU)
Bb (MPI)
MCR2
0 0 1 0 0 0 1 1 B2 (LIU)
Ba (MAP)
MCR3
0 0 0 0 0 0 0 0 No connect
Am79C30A/32A Data Sheet
No connect
21
Peripheral Port
Bd
Be
Bf
Bb
B1
MPI
B-channel
MUX
LIU
Bc
B2
Ba MAP
09893H-3
Figure 2.
MUX Logical Channels
Therefore, in this example, MCR1 provides a data link
from the S Interface and MCR2 sets up a voice connection across the S Interface.
To loopback a channel, the same channel code is used
for port 1 and port 2. For example, to loopback B1, B2,
and Ba, the MCRs would be:
Port 1
Port 2
Register 7 6 5 4 3 2 1 0 Channel Connection
MCR1
0 0 0 1 0 0 0 1 B1 (LIU) Loopback
MCR2
0 0 1 0 0 0 1 0 B2 (LIU) Loopback
MCR3
0 0 1 1 0 0 1 1 Ba (MAP) Loopback
MCR3 has higher priority than MCR2. MCR2 has
higher priority than MCR1.
MCR will overwrite the data from the connecting port in
the lower priority MCR, for example:
Port 1
Register 7 6 5 4 3 2 1 0 Channel Connection
MCR1
0 0 0 0 0 0 0 0 No connect
MCR2
0 0 0 1 0 1 0 0 B1 (LIU)
Bb (MPI)
MCR3
0 1 0 0 0 0 1 1 Bb (MPI)
Ba (MAP)
The final data transfers are:
B1 (LIU) receives Bb (MPI),
Ba (MAP) receives Bb (MPI),
Bb (MPI) receives Ba (MAP).
Therefore, the data transfer from B1 (LIU) to Bb (MPI)
is lost in the arrangement proposed in MCR2.
If multiple connections are made to the same port, the
data from the connecting ports in the highest priority
22
Port 2
Am79C30A/32A Data Sheet
MUX Control Register 4 (MCR4), Read/Write
Address = Indirect 44H
The MUX Control Register 4 (MCR4) can prevent interrupt generation by masking the output of IR bit 4. MCR4 has
the format shown in Table 19.
Table 19.
MUX Control Register 4
Bit
Logical 1
Logical 0 (Default Value)
0–2
Reserved, must be set to logical 0
Reserved, must be set to logical 0
3
Enable Bb- or Bc-channel byte available interrupt (IR Bit 4) Disable interrupt
4
Reverse bit order of Bb (LSB transmitted/received first)
No Bb bit reversal (MSB transmitted/received first)
5
Reverse bit order of Bc (LSB transmitted/received first)
No Bc bit reversal (MSB transmitted/received first)
6
Reserved, must be set to logical 0
Reserved, must be set to logical 0
7
Reserved, must be set to logical 0
Reserved, must be set to logical 0
Am79C30A/32A Data Sheet
23
Main Audio Processor (MAP)
Audio Inputs
(Am79C30A only)
The audio input port consists of two inputs (AINA and
AINB) which are selectable, one at a time, by register
programming. Signals applied to these inputs must be
AC-coupled.
Overview
The MAP, as illustrated in Figure 3, implements audio-band analog-to-digital (ADC) and digital-to-analog
(DAC) conversions together with a wide variety of audio
support functions. Analog interfaces are provided for a
handset earpiece, a handset mouthpiece, a microphone, and a loudspeaker. A programmable analog
preamplifier is included in front of the A/D converter.
The codec and filter functions are implemented using
digital signal processing (DSP) techniques to provide
operational stability and programmable features. There
is one programmable digital gain stage in the transmit
path and two in the receive path to allow precise signal
level control. Sidetone attenuation is programmable,
and programmable equalization filters are present in
both the receive and transmit paths in order to modify
the frequency response of either or both paths. Tone
generation capability is included to allow generation of
ringing signals, DTMF tones, and call progress signals.
MAP operation is described in detail in the following
sections.
Earpiece and Loudspeaker Drivers
The earpiece and loudspeaker drivers each consist of
amplifiers with differential, low-impedance outputs. The
MAP receive path signal may be routed to either of
these outputs, or to both outputs simultaneously. Alternatively, the MAP receive path may be routed to the
EAR outputs while the Secondary Tone Ringer (STR)
is routed to the LS outputs. The EAR drivers can drive
loads Š130 ohms between the EAR1 and EAR2 pins,
while the LS drivers can drive loads Š40 ohms between
the LS1 and LS2 pins. The maximum capacitive-loading between EAR1 and EAR2 or between LS1 and LS2
is 100 pF. The EAR outputs are high-impedance when
the MAP is disabled. The LS outputs are high impedance when both the MAP and the Secondary Tone
Ringer are disabled.
CAP1
CAP2
AINA
AINB
PEAKX
GA*
ADC
X*
Decimators, BPF
GX*
COMP*
Digital
Loopback 1
AREF
Transmitter
Receiver
Analog
Sidetone
Gain*
(A)
DTMF
GEN.
Sidetone
Gain*
Digital
Loopback 2
EAR1
EAR2
DAC
Interpolators, LPF
R*
GER*
+
GR*
LS1
STR*
LS2
Ba channel
from
EXP*
MUX
PEAKR
(C)
Notes:
GX
GER
GR
STG
GA
ASTG
Ba channel
to
MUX
Minimum
Default
Maximum
Step
0 dB**
–10 dB**
–12 dB**
–18 dB**
0 dB
–27 dB**
0 dB
0 dB
0 dB
–18 dB
0 dB
8
12 dB
18 dB
0 dB
0 dB
24 dB
–6 dB
0.5 dB
0.5 dB
0.5 dB
0.5 dB
6.0 dB
1.5 dB
Tone*
Ringer
Tone*
Gen.
(B)
*Programmable
**These registers can also be programmed for infinite attenuation to break the signal path if desired.
09893H-4
Figure 3.
24
Main Audio Processor Block Diagram
Am79C30A/32A Data Sheet
Programmable Analog Preamplifier
Receiver
A programmable analog preamplifier GA is included in
front of the A/D converter and is adjustable in 6-dB increments from 0 dB to +24 dB. The existing GX gain
stage in the transmit path may be used for finer adjustment of transmit gain. This preamplifier eliminates the
need for an external operational amplifier when interfacing electret-type handsets to the DSC circuit.
The receiver performs a series of operations described
as follows:
Analog Sidetone
Analog sidetone takes the analog input to the transmitter ADC and sums it into the single-ended input of the
EAR output buffer. The summing point is after the output selection switch. The analog sidetone path has programmable attenuation between –6 and –27 dB, plus
infinity (off). Default is infinity. Programming is via four
bits in the Extended FIFO Control Register, EFCR.6–3.
The programming values are given in Table 20.
Table 20.
Analog Sidetone
0000 =∞
0100 = –22.5 dB
0001 = –27.0 dB
0101 = –21.0 dB
0010 = –25.5 dB
0110 = –19.5 dB
0011 = –24.0 dB
0111 = –18.0 dB
1. An expander converts the input A- or µ-law data to
digital linear data. The most significant bit is transferred from the MUX first. The default value is µ-law.
2. The GR filter is a programmable gain filter that allows the user to program a gain of –12 to 0 dB in
0.5-dB steps. The default value of GR is 0 dB.
3. The GER and Sidetone Gain (STG) are programmable constant multipliers which allow the user to
program a gain of –10 to +18 dB in 0.5-dB steps
(default value 0 dB) and –18 to 0 dB in 0.5-dB steps
(default value –18 dB) respectively. The GER provides volume control (for the hearing impaired) and
should be programmed to 0 dB for normal operation. The sidetone gain path provides feedback from
the transmitter.
4. The R filter is provided to correct for speaker attenuation distortion and is a user-programmable filter
similar to the X filter in the transmitter.
5. A series of interpolators increases the sampling
frequency.
1000 = –16.5 dB
1100 = –10.5 dB
6. A DAC converts the digital signal to the analog
audio output signal.
1001 = –15.0 dB
1101 = –9.0 dB
PEAK Hold Registers
1010 = –13.5 dB
1110 = –7.5 dB
1011 = –12.0 dB
1111 = –6.0 dB
Logic in the form of two microprocessor accessible
peak hold registers will be provided to allow for support
of a software based speaker phone solution. These
registers, one in the transmit path (PEAKX) and one in
the receive path (PEAKR), will provide the compressed
maximum (peak) absolute value of the data in the path
since the register was last read. With appropriate software, this can be used to implement a hands-free function. Refer to the MAP block diagram for the location of
these registers in the processing path.
Signal Processing
Transmitter
The transmitter performs a series of operations as described below.
1. An ADC converts the incoming analog signal at a
sampling rate of 512 kHz.
2. The Band Pass filter and a series of decimators reject DC and 50- to 60-Hz line frequencies while reducing the sampling rate to 8 kHz.
3. The X filter is an 8-tap user-programmable filter for
tuning the microphone. The default is flat with unity
gain.
4. The GX filter is a programmable gain filter that allows the user to program a gain of 0 to +12 dB in
0.5-dB steps. The default value is 0 dB.
5. The µ-law or A-law digital compression algorithm
converts the linear output of the GX filter to µ- or
A-law code. The default algorithm is µ-law code.
The MSB (sign bit) is transferred first to (or from) the
MUX.
The following assumptions are made:
1. The GX and GR blocks are used as gain/attenuators, without modification to their range or resolution.
2. The data is presented in compressed A-law format,
without the alternate bit inversion. The sign bit is not
presented.
3. The data extraction point for the transmit path is
after the X filter.
4. The data extraction point for the receive path is immediately following the expander.
5. The compressed data from the transmit and receive
paths is presented using the same compression
algorithm.
Am79C30A/32A Data Sheet
25
6. The peak registers are double-buffered and can be
read asynchronously to the operation of the DSP
register. They are cleared on read.
The DTMF generator may be used to generate single
frequency outputs. To obtain a single frequency out of
the DTMF generator, load a zero code into one of the
two frequency registers.
7. The peak registers default to “don't care” values
when the part is reset. An initial read operation is required to clear the register before using it for the first
time.
Tone Generation
The PEAKX register is at indirect address 70H, while
the PEAKR register is at indirect address 71H. Both
may be accessed via back-to-back read data register
operations by loading the command register with 72H.
Tone Ringer
Tone Generators
The MAP contains three tone generators which can be
enabled via MAP Mode Register 2, bits 2, 3, and 4.
Only one of the three tone generator bits in the register
can be set at a time. If more than one bit is set, all three
bits are considered set to zero and tone generation is
disabled. The tone generators are:
DTMF Generator
This generator provides tone injection at a sampling
rate of 32 kHz into the transmit and sidetone paths (Figure 3, Block A). The DTMF frequencies generated are
guaranteed to ±1.2% deviation.
Table 21.
FTGR 2 or 1
This generator provides tone aler t signals output
through the receive path to the loudspeaker or earpiece (Figure 3, Block C).
To program the DTMF tone generators, two frequency
values and two amplitude values must be written to the
two 8-b it Frequ ency Ton e Gen era to r Re gisters
(FTGR1, FTGR2) and the two 8-bit Amplitude Tone
Generator Registers (ATGR1, ATGR2), respectively.
The Tone Generator and the Tone Ringer use the frequency programmed in FTGR1. The Tone Generator
uses the amplitude programmed in ATGR1 while the
Tone Ringer uses the amplitude programmed in ATGR2.
Common frequency values are listed in Table 22.
The FTGR codes to obtain DTMF dialing output frequencies are listed in Table 21.
DTMF Codes
9BH
ABH
BFH
D3H
FREQ
1209
1336
1477
1633
5AH
697
1
2
3
A
63H
770
4
5
6
B
6EH
852
7
8
9
C
79H
941
*
0
#
D
HEX REG VALUE
FTGR 1 or 2
26
This generator provides call progress tones to the receive path, where it is added to the incoming speech
(Figure 3, Block B).
Am79C30A/32A Data Sheet
The output frequency of the DTMF tone generator approximately equals:
64000
DTMF Frequency in Hz = ---------------------------------------------------integer ( 8192 ⁄ i ) + 1
where i is the decimal equivalent of value programmed
into the FTGR register. This allows the DTMF generator to supply common dual tone call progress signals
such as Busy or Dial tones.
Table 22.
The ATGR registers allow the user to program a gain of
–18 dB to 0 dB in 2-dB steps. Example ATGR codes to
obtain amplitude gains are listed in Table 23. 0 dB implies a level of +3 dBm0. The gain values are rounded
off to the nearest 1 dB.
Table 23.
Amplitude Gain Coefficients
Gain (dB)
Hex Code
–18
37
–16
32
–14
31
Tone Ringer and Tone Generator
Frequency Coefficients
Frequency (Hz)
Hex Code
–12
27
2666
AB
–10
22
2000
81
–8
21
1600
67
–6
20
1333
56
–4
12
1142
4A
–2
11
1000
41
0
10
889
39
800
34
727
2F
667
2B
615
28
Secondary Tone Ringer
571
25
533
23
500
21
471
1F
444
1D
421
1B
400
1A
381
19
364
18
348
17
333
16
320
15
A Secondary Tone Ringer is included, which is able to
ring the phone using the LS outputs while a voice conversation is in progress on the EAR outputs. The STR
is louder than the Tone Generator, and may be used
with or without enabling the MAP in order to provide
flexible control of system power consumption. The STR
is not available if the INIT register is programmed to
Idle or Power-Down mode. The amplitude and frequency of the STR square-wave output waveform is
programmable via the STRA and STRF registers, respectively. If both the LS outputs from the MAP receive
path and the STR are simultaneously enabled, priority
is given to the STR connection. The STR is available for
both the DSC and IDC circuits. A legal value must be
programmed in the STRF register before the STR is
enabled.
Note:
See the amendment to Table 23 following page 100.
Note:
These coefficients do not apply to the DTMF generator.
Am79C30A/32A Data Sheet
27
Programmable Gain Coefficients
The GER, GR, GX, and Sidetone gain coefficients are each 16 bits in length. Two consecutive register locations
correspond to one gain coefficient. The LSB is transferred first to (or from) the microprocessor. Sample coefficients
for the GER filter are listed in Table 24. The gain values are rounded off to the nearest 0.1 dB.
Table 24.
GER Gain Coefficients
Hex Code
Hex Code
Gain (dB)
MSB
LSB
Gain (dB)
MSB
LSB
–10
AA
AA
4.0
31
DD
–9.5
9B
BB
4.5
44
1F
–9.0
79
AC
5.0
43
1F
–8.5
09
9A
5.5
33
1F
–8.0
41
99
6.0
40
DD
–7.5
31
99
6.5
11
DD
–7.0
9C
DE
7.0
44
0F
–6.5
9D
EF
7.5
41
1F
–6.0
74
9C
8.0
31
1F
–5.5
54
9D
8.5
55
20
–5.0
6A
AE
9.0
10
DD
–4.5
AB
CD
9.5
42
11
–4.0
AB
DF
10.0
41
0F
–3.5
74
29
10.5
11
1F
–3.0
64
AB
11.0
60
0B
–2.5
6A
FF
11.5
00
DD
–2.0
2A
BD
12.0
42
10
–1.5
BE
EF
12.5
40
0F
–1.0
5C
CE
13.0
11
0F
–0.5
75
CD
13.4
22
10
0.0
00
99
14.0
72
00
0.5
55
4C
14.5
42
00
1.0
43
DD
15.0
21
10
1.5
33
DD
15.5
10
0F
2.0
52
EF
15.9
22
00
2.5
77
1B
16.6
11
10
3.0
55
42
16.9
00
0B
3.5
41
DD
17.5
21
00
18.0
00
0F
Note:
The coefficient 0008 provides an attenuation of infinity when GER gain is enabled.
28
Am79C30A/32A Data Sheet
Example coefficients for the GR, GX, and STG filters
are listed in Tables 25, 26, and 27. The gain values are
rounded off to the nearest 0.1 dB.
Table 25.
GX Gain Coefficients
Hex Code
Table 26.
GR Gain Coefficients
Hex Code
Gain (dB)
MSB
LSB
–11.5
91
C5
–11.0
91
B6
–10.5
92
12
Gain (dB)
MSB
LSB
–10.0
91
A4
0.0
08
08
–9.5
92
22
0.5
4C
B2
–9.0
92
32
1.0
3D
AC
–8.5
92
FB
1.5
2A
E5
–8.0
92
AA
2.0
25
33
–7.5
93
27
2.5
22
22
–7.0
93
B3
3.0
21
22
–6.5
94
B3
3.5
1F
D3
–6.0
9F
91
4.0
12
A2
–5.5
9C
EA
4.5
12
1B
–5.0
9B
F9
5.0
11
3B
–4.5
9A
AC
5.5
0B
C3
–4.0
9A
4A
6.0
10
F2
–3.5
A2
22
6.5
03
BA
–3.0
A2
A2
7.0
02
CA
–2.5
A6
8D
7.5
02
1D
–2.0
AA
A3
8.0
01
5A
–1.5
B2
42
8.5
01
22
–1.0
BB
52
9.0
01
12
–0.5
CB
B2
9.5
00
EC
0.0
08
08
10.0
00
32
10.5
00
21
11.0
00
13
11.5
00
11
12.0
00
0E
Am79C30A/32A Data Sheet
29
Table 27.
STG Gain Coefficients
Hex Code
Gain (dB)
MSB
LSB
–18.0
8B
7C
–17.5
8B
44
–17.0
8B
35
–16.5
8B
2A
–16.0
8B
24
–15.5
8B
22
–15.0
91
23
–14.5
91
2E
–14.0
91
2A
–13.5
91
32
–13.0
91
3B
–12.5
91
4B
–12.0
91
F9
–11.5
91
C5
–11.0
91
B6
–10.5
92
12
–10.0
91
A4
–9.5
92
22
–9.0
92
32
–8.5
92
FB
–8.0
92
AA
–7.5
93
27
–7.0
93
B3
–6.5
94
B3
–6.0
9F
91
–5.5
9C
EA
–5.0
9B
F9
–4.5
9A
AC
–4.0
9A
4A
–3.5
A2
22
–3.0
A2
A2
–2.5
A6
8D
–2.0
AA
A3
–1.5
B2
42
–1.0
BB
52
–0.5
CB
B2
0.0
08
08
Note:
The coefficient 9008 provides an attenuation of infinity when
GR, GX, and/or STG are enabled.
30
Overflow/Underflow Precautions When Using
Programmable Gains
Care must be taken so that at any point in the signal
processing path, the combination of gains and filters
and/or tones does not result in a signal that is larger
than full scale. Full scale is defined as the digital representation of the maximum analog signal that is allowed
into the transmitter or out of the receiver with all filters
and gain stages at their default (0 dB) settings (e.g., in
A-Law, the transmitter full scale is ±1.25 VP and the receiver full scale is ±2.5 VP). Likewise, it is desirable that
the peak signal be kept as close to full scale as possible
at any point in the signal processing path in order to
minimize digital truncation effects in the A/D, D/A, and
MAP DSP.
Consider the following example: STG is programmed
for infinite attenuation, GR is programmed to –6 dB
while GER is programmed to +12 dB, and the R filter is
programmed to exhibit a net gain of –6 dB. Assume the
analog full scale out of the receiver is ± 2.5 VP, and a
full scale PCM code is possible from the MUX. After
GR, the equivalent analog signal will be 2.5 / 2 = ±1.25
VP. However, after GER the signal will be 1.25 × 4, or +
5 VP. Even though the R filter will have a net gain of –6
dB, the signal will be clipped after GER and distorted
for PCM codes between full scale and 6 dB below full
scale due to the intermediate result at the output of
GER.
Be very careful when programming the tone ringers/generators. For example, if one of the DTMF tones
is programmed to 0 dB, a tone is generated that is
equivalent to a ± full scale signal in the transmit path.
This means no headroom is left for the other DTMF
tone. Therefore, the DTMF generator should never be
programmed to exceed full scale if signal quality is to
be maintained. In the receive path, similar caution
should be exercised in order to prevent the combination
of Tone Generator, Sidetone, GR, and GER from clipping the signal.
Extended Programming Ranges
Some applications of the DSC will require greater flexibility in the programming of the MAP’s internal gain
and attenuation blocks. For example, applications such
as software-based hands-free utilizing the PEAKX and
PEAKR registers may need attenuation as well as gain
within the MAP transmit path. The preceding gain tables do not specifically detail this capability, but due to
the DSP implementation of these gain and filter blocks,
the DSC is capable of performance beyond these recommended ranges. (GA and ASTG are not implemented in DSP and are limited to their stated range and
step size.) Table 28 lists guaranteed ranges, while
Table 29 shows the limits by design.
Am79C30A/32A Data Sheet
Table 28.
Recommended Ranges
Recommended and guaranteed
where each hj Coefficient Register pair has the following format:
0 to +12 dB plus infinite in 0.5 dB steps
Byte
7
654
3
210
GER
–10 to +18 dB plus infinite in 0.5 dB steps
LSB
S1
M1
S0
M0
GR
–12 to 0 dB plus infinite in 0.5 dB steps
MSB
S3
M3
S2
M2
STG
–18 to 0 dB plus infinite in 0.5 dB steps
GX
Table 29.
Design Ranges
and Ai = –1 Si 2 –Mi , (i=0,1,2,3).
The X and R filter coefficients are programmed using a
16-byte transfer with the format shown in Table 30.
Limits by design
GX
–84.3 to 14.0 dB plus infinite in 0.1 dB steps
over most of the range
GER
–24.1 to 24.1 dB plus infinite in 0.1 dB steps
over most of the range
–84.3 to 14.0 dB plus infinite in 0.1 dB steps
over most of the range
0
h0 LSB
GR
1
h0 MSB
STG
–84.3 to 14.0 dB plus infinite in 0.1 dB steps
over most of the range
2
h1 LSB
4
h2 LSB
5
h2 MSB
6
h3 LSB
7
h3 MSB
8
h4 LSB
Table 30.
X/R Filter Format
Byte
As an example, in a hands-free application using an
electret requiring 24 dB of gain in the transmit path for
optimum performance. The typical implementation
would use 18 dB of GA and 6 dB of GX gain. The user
would then have a programmable range of +6 dB to –66
dB utilizing GX. Selection of these gain points is of
course, application specific, and will depend on the performance requirements of the system.
Listings of the optimized programming values for various levels are included in Appendix A. Values listed in
the recommended tables are still correct and will perform as stated. There is no need to convert to the extended values unless greater resolution is required.
Value
9
h4 MSB
10
h5 LSB
11
h5 MSB
12
h6 LSB
13
h6 MSB
14
h7 LSB
15
h7 MSB
Programmable Filter Coefficients and Equations
The frequency domain transfer function equation for
the X and R filters is:
hf = h0 + h1 z
h5z
–5
–1
+ h2 z
+ h6 z
–6
–2
+ h3z
+ h7 z
–3
+ h4 z
–4
+
–7
Note:
AmMAP™ software, which calculates X and R filter coefficients, is available from Advanced Micro Devices. Contact
your local AMD Sales Office for more information.
Test Facilities
Three capabilities are provided for MAP operation verification.
MAP Analog Loopback
where:
z = cos (wT) + i V sin(wT)
i = (–1) 1/2
w = frequency of input signal in Hz · 2pi
T = sample period in seconds (0.125 ms)
hj (j = 0,1,...7) = user-defined coefficients.
Each hj coefficient is defined by the following equation:
hj = A3 { 1 + A2 [ 1 + A ( 1 + A0 ) ] }
Signals sent in on AINA or AINB may be sent back out
to EAR1/EAR2 or LS1/LS2 by looping the MAP path in
the MUX. The MUX should be set up for Ba-to-Ba loopback by writing 33H to MCR1, MCR2, or MCR3. No
other MUX connections overriding Ba-to-Ba should be
programmed. This test allows the MAP analog and digital to be tested using a local signal source.
MAP Digital Loopback 1
This loopback mode connects the interpolator output to
the decimator input in place of the ADC output. This
mode allows verification from the S Interface or micro-
Am79C30A/32A Data Sheet
31
processor that the MAP digital circuitry is functional.
Note that the digital patterns received after loopback
will not be identical to the transmitted patterns. The
D-D gain is approximately 2.5 dB.
MAP Digital Loopback 2
This loopback mode connects the analog D/A output
path to the analog A/D input path, internal to the DSC
circuit. The EAR and LS outputs and both AIN inputs
will be disabled. This mode allows verification from the
S Interface or microprocessor that the MAP analog and
digital circuitry are functional. The digital patterns received after loopback will not be identical to the transmitted patterns.
Following reset, the MAP registers FTGR, MMR1,
MMR2, MMR3, STRA, and STRF all default to 00 hex.
All other MAP registers are not affected by reset and
must be programmed by the microprocessor before
being enabled. When the registers are disabled, or
after reset, the MAP will have the response shown in
Table 32.
Table 32.
Default Values
Filter
Default Response
X filter
Disabled (0 dB, Flat)
R filter
Disabled (0 dB, Flat)
The bits in the MAP mode Register define the enable/disable options for the various MAP configurations
as follows.
GX filter
Disabled (0 dB, Gain)
GR filter
Disabled (0 dB, Gain)
GER filter
Disabled (0 dB, Gain)
MAP Registers
Sidetone gain
Disabled (–18 dB, Gain)
The MAP contains the programmable registers found in
Table 31.
Table 31.
Map Registers
MAP Register
Bytes
Mnemonic
X-filter Coefficient Register
16
X
R-filter Coefficient Register
16
R
GX-Gain Coefficient Register
2
GX
GR-Gain Coefficient Register
2
GR
GER-Gain Coefficient Register
2
GER
Sidetone-Gain Coefficient Register
2
STGR
Frequency Tone Generator Register
2
FTGR
Amplitude Tone Generator Register
2
ATGR
MAP mode Registers (3)
1
MMR
Secondary Tone Ringer Amplitude
Reg
1
STRA
Secondary Tone Ringer Frequency
Reg
1
STRF
Transmit Peak Register
1
PEAKX
Receive Peak Register
1
PEAKR
Note:
It is necessary to complete any transfers to the multi-byte
MAP registers. For instance, a total of 16 bytes must be transferred to update the X filter.
32
Am79C30A/32A Data Sheet
MAP Mode Register 1 — (MMR1) — Read/Write
Address = Indirect 69H
Table 33.
Bit
Map Mode Register 1
Logical 1
Logical 0 (Default Value)
0
A-Law
µ-Law
1
GX coefficient loaded from register
GX bypassed; gain = 0 dB
2
GR coefficient loaded from register
GR bypassed; gain = 0 dB
3
GER coefficient loaded from register
GER bypassed; gain = 0 dB
4
X coefficient loaded from register
X bypassed; response = flat
5
R coefficient loaded from register
R bypassed; response = flat
6
Sidetone gain coefficient loaded from register
STG gain = –18 dB*
7
Digital loopback #1 at MAP enabled
Digital loopback #1 at MAP disabled
Note:
*To remove the sidetone path completely, it is necessary to enable the STG function by setting MMR1 bit 6 to 1, and program the
STGR coefficient to 9008 (hex).34
MAP Mode Register 2 — (MMR2) — Read/Write
Address = Indirect 6AH
Table 34.
Bit
Logical 1
Map Mode Register 2
Logical 0 (Default Mode)
0
AINB selected
AINA selected
1
LS1/LS2 selected
EAR1/EAR2 selected
2
DTMF enabled
DTMF disabled
3
Tone generator enabled
Tone generator disabled
4
Tone ringer enabled
Tone ringer disabled
5
High pass filter disabled
High pass filter enabled
6
ADC auto-zero function disabled
ADC auto-zero function enabled
7
Reserved, must be Logical 0
Reserved, must be Logical 0
Note:
For most applications, MMR2 bits 5 and 6 should always be written to logical 0. This enables the 50–60 Hz rejection filter and the
internal offset cancellation circuits to operate normally. They can both be disabled when system or test conditions require the
transmission of DC or low frequency signals.
Am79C30A/32A Data Sheet
33
Map Mode Register 3 — (MMR3) — Read/Write
Address Indirect 6CH
Table 35.
Map Mode Register 3
Bit
7
6
5
4
3
2
1
0
0
X
X
X
X
X
X
X Bit 7 Reserved, must be written to 0
Function
0
0
0
0
X
X
X
X 0-dB pre-amplifier gain, 1.250-V maximum peak input voltage
0
0
0
1
X
X
X
X +6-dB pre-amplifier gain, 0.625-V maximum peak input voltage
0
0
1
0
X
X
X
X +12-dB pre-amplifier gain, 0.312-V maximum peak input voltage
0
0
1
1
X
X
X
X +18-dB pre-amplifier gain, 0.156-V maximum peak input voltage
0
1
0
0
X
X
X
X +24-dB pre-amplifier gain, 0.078-V maximum peak input voltage
0
1
0
1
X
X
X
X Reserved; undefined
0
1
1
0
X
X
X
X Reserved; undefined
0
1
1
1
X
X
X
X Reserved; undefined
0
X
X
X
1
X
X
X MUTE ON, AINA and AINB inputs disabled
0
X
X
X
0
X
X
X MUTE OFF, AINA or AINB enabled
0
X
X
X
X
1
X
X Digital Loopback 2 enabled; D/A output looped to A/D input; EAR, LS, and AIN pin disabled
0
X
X
X
X
0
X
X Digital Loopback 2 disabled
0
X
X
X
X
X
1
X EAR and LS simultaneously enabled
0
X
X
X
X
X
0
X EAR or LS enabled by MMR2 bit 1
0
X
X
X
X
X
X
1
Secondary Tone Ringer enabled
0
X
X
X
X
X
X
0
Secondary Tone Ringer disabled
Secondary Tone Ringer Amplitude Register — (STRA) — Read/Write
Address = Indirect 6DH
Table 36.
Secondary Tone Ringer Amplitude
Bit
34
Peak-to-Peak
Output Voltage
Relative Output
Approximate Power
into 50 ohms
0.22 V
–27 dB
0.25 mW
0.31 V
–24 dB
0.5 mW
0
0.44 V
–21 dB
1.0 mW
0
0.62 V
–18 dB
2.0 mW
0
0
0.88 V
–15 dB
4.0 mW
0
0
0
1.25 V
–12 dB
8.0 mW
0
0
0
1.77 V
–9 dB
16.0 mW
0
0
0
0
2.50 V
–6 dB
31.25 mW
0
0
0
0
0
3.53 V
–3 dB
62.5 mW
1
0
0
0
0
5.00 V
0 dB
125.0 mW
X
0
0
0
0
Bits 0–3 Reserved;
must be written to 0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Silent
0
0
0
1
0
0
0
0
Reserved
0
0
1
0
0
0
0
0
Reserved
0
0
1
1
0
0
0
0
Reserved
0
1
0
0
0
0
0
0
Reserved
0
1
0
1
0
0
0
0
Reserved
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
X
X
X
Am79C30A/32A Data Sheet
Secondary Tone Ringer Frequency Register (STRF), Read/Write; Address = Indirect 6EH
STRF is a Read/Write register controlling the frequency of the secondary tone ringer. Hex codes 7F and 00 are reserved and should not be used. The coefficients are defined in Table 37.
Table 37.
Counter
Value
3F
1F
0F
87
43
A1
D0
E8
F4
7A
3D
1E
8F
C7
63
B1
58
2C
16
0B
05
02
01
80
40
20
10
88
C4
E2
71
38
1C
8E
47
23
91
48
A4
D2
E9
74
3A
1D
0E
07
03
81
C0
60
30
98
4C
26
93
49
Frequency
(Hz)
Reserved
Reserved
12000.0
9600.0
8000.0
6857.1
6000.0
5333.3
4800.0
4363.6
4000.0
3692.3
3428.6
3200.0
3000.0
2823.5
2666.7
2526.3
2400.0
2285.7
2181.8
2087.0
2000.0
1920.0
1846.2
1777.8
1714.3
1655.2
1600.0
1548.4
1500.0
1454.6
1411.8
1371.4
1333.3
1297.3
1263.2
1230.8
1200.0
1170.7
1142.9
1116.3
1090.9
1066.7
1043.5
1021.3
1000.0
979.6
960.0
941.2
923.1
905.7
888.9
872.7
857.1
842.1
Counter
Value
3B
9D
4E
27
13
09
04
82
41
A0
50
A8
D4
6A
B5
DA
6D
B6
5B
AD
D6
6B
35
9A
4D
A6
D3
69
34
1A
0D
86
C3
E1
F0
F8
7C
BE
DF
6F
B7
DB
ED
F6
7B
BD
5E
AF
D7
EB
75
BA
5D
2E
17
8B
Frequencies for Secondary Tone Ringer
Frequency
(Hz)
727.3
716.4
705.9
695.7
685.7
676.1
666.7
657.5
648.7
640.0
631.6
623.4
615.4
607.6
600.0
592.6
585.4
578.3
571.4
564.7
558.1
551.7
545.5
539.3
533.3
527.5
521.7
516.1
510.6
505.3
500.0
494.9
489.8
484.9
480.0
475.3
470.6
466.0
461.5
457.1
452.8
448.6
444.4
440.4
436.4
432.4
428.6
424.8
421.1
417.4
413.8
410.3
406.8
403.4
400.0
396.7
Counter
Value
D8
6C
36
1B
8D
C6
E3
F1
78
3C
9E
CF
E7
73
39
9C
CE
67
33
19
8C
46
A3
D1
68
B4
5A
2D
96
4B
25
12
89
44
A2
51
28
94
4A
A5
52
A9
54
2A
95
CA
E5
72
B9
DC
EE
77
BB
DD
6E
37
Am79C30A/32A Data Sheet
Frequency
(Hz)
369.2
366.4
363.6
360.9
358.2
355.6
352.9
350.4
347.8
345.3
342.9
340.4
338.0
335.7
333.3
331.0
328.8
326.5
324.3
322.2
320.0
317.9
315.8
313.7
311.7
308.7
307.7
305.7
303.8
301.9
300.0
298.1
296.3
294.5
292.7
290.9
289.2
287.4
285.7
284.0
282.4
280.7
279.1
277.5
275.9
274.3
272.7
271.2
269.7
268.2
266.7
265.2
263.7
262.3
260.9
259.5
Counter
Value
F7
FB
FD
7E
BF
5F
2F
97
CB
65
32
99
CC
66
B3
59
AC
56
2B
15
8A
C5
62
31
18
0C
06
83
C1
E0
70
B8
5C
AE
57
AB
55
AA
D5
EA
F5
FA
7D
3E
9F
4F
A7
53
29
14
0A
85
42
21
90
C8
Frequency
(Hz)
247.4
246.2
244.9
243.7
242.4
241.2
240.0
238.8
237.6
236.5
235.3
234.2
233.0
231.9
230.8
229.7
228.6
227.5
226.4
225.4
224.3
223.3
222.2
221.2
220.2
219.2
218.2
217.2
216.2
215.3
214.3
213.3
212.4
211.5
210.5
209.6
208.7
207.8
206.9
206.0
205.1
204.3
203.4
202.5
201.7
200.8
200.0
199.2
198.4
197.5
196.7
195.9
195.1
194.3
193.6
192.8
35
Table 37.
Counter
Value
24
92
C9
64
B2
D9
EC
76
Frequency
(Hz)
827.6
813.6
800.0
786.9
774.2
761.9
150.0
738.5
Frequencies for Secondary Tone Ringer (Continued)
Counter
Value
45
22
11
0-8
84
C2
61
B0
Frequency
(Hz)
393.4
390.2
387.1
384.0
381.0
378.0
375.0
372.1
Data Link Controller (DLC)
Overview
A 16-Kbit/s D-channel is time-multiplexed within the
frame structure of the S Interface. The data carried by
the D channel is encoded using the Link Access Protocol D-channel (LAPD) format shown in Figure 4. The D
channel can be used to carry either end-to-end signaling or low-speed packet data. Further information concerning LAPD protocol can be found in the CCITT
recommendations. The LIU controls the multiplexing
and demultiplexing of the D-channel data between the
S Interface and the DLC.
The DLC performs processing of Level-1 and partial
Level-2 LAPD protocol, including flag detection and
generation, zero deletion and insertion, Frame Check
Sequence (FCS) processing for error detection, and
some addressing capability. High level protocol processing is done by the external microprocessor. The
microprocessor may process the address field in the
LAPD frame depending on the programmed state of
the DLC. The status of the DLC is held in the status registers and relevant interrupts are generated under user
program control. In addition to transmit and receive
data FIFOs, the DLC contains a 16-bit pseudo-random
number generator (RNG) used in the CCITT D-channel
address allocation procedure.
D-channel Processing
Random Number Generator (RNG)
The RNG is accessible by the microprocessor and operates in the following manner.
On the Low-to-High transition of the reset signal, the
RNG is cleared, then started. The RNG stops when the
LSB or MSB of the 16-bit counter is read by the microprocessor, or when the MSB is loaded by the microprocessor. Writing to the MSB of the counter loads this
byte but does not start the RNG. The RNG starts when
the LSB of the counter is loaded by the microprocessor.
Frame Abort
The DLC aborts an incoming D-channel frame when
seven contiguous logical 1s are received. When this
occurs, an End-of-Receive-Packet interrupt is issued to
the processor. DER bit 0 is set to a logical 1 when the
36
Counter
Value
9B
CD
E6
F3
79
BC
DE
EF
Frequency
(Hz)
258.1
256.7
255.3
254.0
252.6
251.3
250.0
248.7
Counter
Value
E4
F2
F9
FC
FE
FF
Frequency
(Hz)
192.0
191.2
190.5
189.7
189.0
188.2
last byte of the aborted packet is read from the D-channel Receive buffer. The Receive-Abort interrupt can be
masked by setting DMR2 bit 0 to a logical 0. With the
exception of the Packet-Reception-in-Progress bit, no
other bits associated with packet reception are updated
after a receive packet abort. The receive frame can be
aborted at any time by setting INIT bit 6 to logical 1.
Similarly, the transmit frame can be aborted by setting
INIT bit 7 to a logical 1. When the transmit frame is
aborted, seven consecutive 1s are transmitted on the S
Interface followed by a logical 0, and DSR1 bit 7 is set
to a logical 1. Seven consecutive 1s followed by a 0 will
continue to be transmitted as long as INIT bit 7 is set to
1. DSR1 bit 7 will be set after each sequence of seven
consecutive 1s followed by 0.
Level-2 Frame Structure
The D-channel Level-2 frame structure conforms to
one of the formats shown in Figure 4. All frames start
and end with the flag sequence consisting of one 0 followed by six 1s followed by one 0. A packet consists of
a Level-2 frame minus the flag bytes. The LSB is transmitted first for all bytes except the FCS.
The flag preceding a packet is defined as the opening
flag. Therefore, the byte following an opening flag, by
definition, cannot be an abort or another flag. A closing
flag is defined as a flag that terminates a packet. This
flag can be followed by another flag(s), interframe fill
consisting of all 1s or flags, or the address field of the
next packet. In the latter case, the closing flag of one
packet is the opening flag of the next packet. The DLC
receiver can recognize interframe fill consisting of logical 1s or flags. The DLC transmitter follows the closing
flag with interframe fill consisting of all 1s (mark Idle) if
DMR4 bit 4 is set to a logical 0, or all 0s (flag Idle) if
DMR4 bit 4 is set to a logical 1. CCITT I-series D-channel access protocol specifies use of mark Idle.
When a collision is detected (mismatch of a D and E
bit), a complete frame must be retransmitted. For transfer across the S Interface, the S-Interface frame structure is impressed upon the D-channel frame structure
(LAPD).
Zero Insertion/Deletion
When transmitting, the DLC examines the frame content between the opening and closing flags. To ensure
Am79C30A/32A Data Sheet
In the case of the LAPD operating environments, the
address is a 2-byte address where the first byte is analogous to the Service Access Point Identifier (SAPI) and
the second byte is analogous to the Terminal Endpoint
Identifier (TEI) as defined by the CCITT recommendations.
that a flag sequence is not repeated within the flag
boundaries of the frame, a logical 0 bit is automatically
inserted after each sequence of five contiguous logical
1s. When receiving, the DLC examines the frame content between the opening and closing flags and automatically discards the first logical 0 which directly
follows five contiguous logical 1s.
The DLC is able to recognize D-channel addresses of
all of the three types outlined above. Note that only the
first two bytes of a more than 2-byte address can be
checked by the DLC. There are four First Received
Byte Address Registers (FRARs) which hold the values
used to match against the first byte of the incoming address. Similarly, there are four Second Received Byte
Address Registers (SRARs) which hold the values
used to match against the second byte of the incoming
address.
D-Channel Address Recognition
The address field, shown in Figure 4, allows for three
types of addresses:
1. 1-byte address signified by the LSB of the first address byte being set to a logical 1
2. 2-byte address signified by the LSB of the first address byte being set to a logical 0, and the LSB of
the second address byte being set to a logical 1
FRAR4 defaults to FE hex; SRAR4 defaults to FF hex.
This default is analogous to the broadcast address defined by the CCITT recommendations. The type of address recognition which is enabled is shown in Table 38
3. More than 2-byte address signified by the LSB of
both the first and second address bytes being set to
a logical 0
1
2
3
4
5
EA =0 C/R
6
7
8
OCTET 2
SAPI
EA =1
OCTET 3
TEI
FLAG
ADDRESS
CONTROL
FCS
FLAG
01111110
16 bits
8 bits
16 bits
01111110
1
2,3
4
5,6
7
OCTET
Minimum Packet
FLAG
ADDRESS
CONTROL
INFORMATION
FCS
FLAG
01111110
16 bits
8 bits
N bits
16 bits
01111110
1
2,3
4
5…
N–1
N
OCTET
General
09893H-4
Notes:
EA = Address Field Extension bit
SAPI = Service Access Point Identifier
FCS = Frame Check Sequence
C/R = Command/Response Field bit
TEI = Terminal Endpoint Identifier
Figure 4.
Level-2 Frame Structure Formats
Am79C30A/32A Data Sheet
37
Table 38.
DMR4
Bit 7
0
1
X
X
Bit 5
1
1
0
X
.Address Recognition
DMR1
Bits
7
6
5
4
X
X
X
1
Type of address recognition
X
1
X
X
FRAR3
1
X
X
X
FRAR4
X
X
X
1
SRAR1
X
X
1
X
SRAR2
X
1
X
X
SRAR3
1
X
X
X
SRAR4
X
X
X
1
FRAR1:SRAR1
X
X
1
X
FRAR2:SRAR2
X
1
X
X
FRAR3:SRAR3
1
X
X
X
FRAR4:SRAR4
0
0
0
0
FRAR1
Second received byte-only address
2-byte address
Address recognition disabled
If DMR4 bit 6 is set to a logical 0, bit 1 of the FRARs is
ignored when matching the first incoming address byte.
If DMR4 bit 6 is set to a logical 1, all bits of the FRARs
are used when matching the first incoming address
byte. FRAR bit 1 is analogous to the C/R bit defined by
the CCITT recommendations. The address recognition
mechanism for the four FRAR/SRAR addresses can be
individually enabled/disabled via DMR1 bits 4–7.
First Received Byte-Only Address Recognition
If DMR4 bit 5 is set to a logical 1 and DMR4 bit 7 is set
to a logical 0, only the first byte of the incoming address
is compared with the values stored in the enabled
FRARs. An interrupt is generated if there is an address
match and the Valid Address interrupt is enabled. If the
address matches, the packet will be received.
Second Received Byte-Only Address Recognition
If DMR4 bits 5 and 7 are set to a logical 1, the DLC
compares only the value in the second byte of the incoming address with values stored in the enabled
SRARs. An interrupt is generated if there is an address
match and the Valid Address interrupt is enabled. If the
address matches, the packet will be received.
2-Byte Address Recognition
If DMR4 bit 5 is set to a logical 0, the first byte of the
incoming address is compared with the values stored in
the enabled FRARs, and the second byte of the incoming address is compared with the value stored in the
corresponding SRAR. An interrupt is generated if a
match is found for both incoming address bytes with a
FRAR/SRAR pair and the Valid Address interrupt is enabled. If the address matches, the packet will be received.
Disabling Address Recognition
If DMR1 bits 4, 5, 6, and 7 are all set to logical 0, all address recognition is disabled and all addresses are rec38
First received byte-only address
ognized and received. In this case, the Am79C30A/32A
receives the first two bytes following the opening flag
(the incoming address), and then issues an End of Address interrupt if the End of Address interrupt is enabled.
DLC Operation
DLC Transmit and Receive FIFOs
The DLC Transmit and Receive FIFOs may be configured to the Normal or Extended mode of operation.Normal mode is fully backwards compatible with the
Revision D or prior DSC circuit, and is activated upon
RESET or if EFCR bit 0 is programmed to logical 0. In
Normal mode the Transmit and Receive FIFOs are
each 8 bytes in length.
The Extended mode of FIFO operation may be activated
by programming EFCR bit 0 to a logical 1, increasing the
depth of the Transmit and Receive FIFOs to 16 bytes
and 32 bytes, respectively. The setting of EFCR bit 0 to
logical 1 also alters the available programmable FIFO
threshold values set by DMR4 bits 2 and 3.
Receiving D-Channel Packets
The receiver controls the flow of D-channel data to the
D-channel Receive buffer and the termination of a receive packet. Up to two packets can be contained in the
D-channel Receive buffer.
After receiving an opening flag (a bit sequence of
01111110) and one byte of data which is not an abort
or flag on the D channel, the DLC sets the Packet-Reception-in-Progress status bit (bit 2) in D-channel Status Register 1 (DSR1). The DLC then receives the first
two bytes (the two address bytes). If address recognition is enabled, the Am79C30A/32A issues a Valid Address interrupt if a match between the programmed
values and the received address is detected. If no
match is detected and address recognition is enabled,
the DLC ignores the packet. If address recognition is
Am79C30A/32A Data Sheet
disabled, the Am79C30A/32A receives the first two
bytes, issues an End of Address interrupt, and receives
the packet. Both a Valid Address and an End of Address interrupt set Interrupt Register bit 2 to a logical 1
and bit 0 of the D-channel Status Register 1 (DSR1) to
a logical 1. The Valid Address/End of Address interrupt
can be disabled via DMR3 bit 0. There is an internal
3-byte delay which holds the first of the D-channel address bytes until the interrupt has been issued. Note
that the incoming address bytes cannot be read however, until the D-channel Receive Byte Available or
D-channel Receive Threshold interrupt is set.
After the address is received, the DLC continues to receive D-channel bytes into the D-channel Receive
buffer FIFO. The DLC issues an interrupt when data is
available in the D-channel Receive buffer. This interrupt
can be disabled by setting DMR3 bit 3 to a logical 0.
The DLC also issues an interrupt when the receive
threshold set in DMR4 is reached. This interrupt can be
disabled by programming a logical 0 into DMR1 bit 1.
By polling, the microprocessor can then read the
D-channel bytes. The 3-byte delay incurred during address recognition is maintained. Therefore, the DLC receives the Frame Check Sequence (FCS) before
issuing an interrupt to signal the last byte of the packet
has been received and appropriate status bits have
been updated. If DMR3 bit 7 is set, the two FCS bytes
at the end of the packet are transferred into the D-channel Receive buffer along with the data.
The DLC issues an interrupt when the last byte of the
packet is read from the DCRB. This interrupt can be
disabled by setting DMR3 bit 2 to a logical 0.
After the FCS is received, the DLC receiver detects the
closing flag (a bit sequence of 01111110) and then terminates the packet by issuing an End Of Receive
Packet interrupt (bit 1 of DSR1) and returns to looking
for opening flags. The DLC also terminates the packet
when an abort, an overflow, or overrun error condition
is detected. The End Of Receive Packet interrupt can
be disabled by setting DMR1 bit 3 to a logical 0.
The D-channel Receive Byte Count Register (DRCR)
is a 16-bit wide, two-word deep FIFO that is used to
record the number of bytes in the incoming D-channel
packets. Each count is terminated by an end-of-packet
condition. Thus, the DRCR informs the microprocessor
of the number of bytes, including the address bytes,
which have been received. The counter is updated
when the last byte of a packet is placed in the D-channel Receive buffer. When the FCS bytes are included in
the data transferred to the D-channel Receive buffer,
the FCS bytes are included in the byte count; if the FCS
bytes are not included in the transfer, they are not included in the byte count. The opening flag and closing
flag are not included in the byte count.
The D-channel Error and Address Status Registers are
also double buffered. Reading the last byte of a packet
causes the DER byte to propagate to the output of the
FIFO and updates the D-channel Status and Interrupt
Registers accordingly. Reading the MSB of the DRCR
causes the next count and associated ASR byte to
propagate to the output of the FIFOs and updates the
D-channel Status and Interrupt Registers accordingly.
For this reason it is important to read ASR, DER, and
DSR1 prior to reading the DRCR.
When a receive error occurs, an End-of-Packet interrupt is generated and the packet is terminated. When
the last byte of the associated packet is read from the
D-channel Receive buffer, the appropriate DER bits are
set and an error interrupt is generated. All error interrupts can be individually masked by setting the corresponding bits in DMR2 to a logical 0.
There is one 16-bit D-channel Receive Byte Limit Register (DRLR). The received byte count is compared with
the DRLR. When the byte count of the currently received D-channel packet exceeds the limit value, a receiver overflow is detected, the packet is terminated,
and an End-of-Packet interrupt is issued. D-channel
Error Register (DER) bit 4 is set to a logical 1 and an
overflow interrupt issued when the last byte of the associated packet is read from the D-channel Receive
buffer. The Overflow Error interrupt can be masked by
setting DMR2 bit 4 to a logical 0.
The minimum packet length is 5 bytes for a 2-byte address packet (not including flags). If the packet length
is less than the above, an interrupt is issued and DER
bit 5 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive
buffer. The error interrupt can be masked by setting
DMR2 bit 5 to a logical 0.
If packet reception is in progress and the D-channel
Receive buffer is full, the microprocessor has a maximum of 425 µs to respond to the D-channel Receive
Data Available interrupt. If the microprocessor fails to
do so, then an overrun error occurs when the data byte
is overwritten. When this happens, the packet is terminated. DER bit 6 is set to a logical 1 when the last byte
of the associated packet is read from the D-channel
Receive buffer. The Overrun Error interrupt can be
masked by setting DMR2 bit 6 to logical 0.
Error indication is given if two packets have been received and not serviced by the user and a third packet
is received via DSR2 bit 2. When this error occurs, the
third packet is terminated (not received).
Error indication is given for a receiver abort (the reception of seven contiguous 1s) by DER bit 0.
If the number of bits received between two flags is not
an integer multiple of eight (if the received packet does
not contain an integral number of bytes), DER bit 1 is
Am79C30A/32A Data Sheet
39
set and an interrupt is generated when the last byte of
the associated packet is read from the D-channel Receive buffer.
nel Transmit buffer empties to the threshold specified in
the D-channel FIFO mode register. This interrupt can
be disabled by setting DMR1 bit 0 to a logical 0.
The incoming bit stream (including FCS) is run through
the FCS generation and compare block. Upon receipt
of the closing flag, the result is checked and must be
(MSB first) 0001110100001111. Any other pattern indicates an FCS error, and DER bit 3 is set to a logical 1
when the last byte of the associated packet is read from
the D-channel Receive buffer.
If the D-channel Transmit buffer is empty, the microprocessor has up to 375 ms to respond to the D-channel
transmit buffer interrupt. If the microprocessor fails to
load the data bytes in this time frame, an underrun interrupt is generated in DER bit 7, and packet transmission
is terminated with a transmitted abort. The Underrun interrupt can be masked by setting DMR2 bit 7 to a logical
0. Transmission is also terminated when a collision is detected or LIU loss of synchronization occurs.
The DLC receiver does not assume the packet to be
byte-aligned. The architecture supports shared flags between packets, interframe fill consisting of logical 1s
(Mark idle), and interframe fill consisting of flags (Flag
idle). Mark idle is defined as at least 15 or more contiguous 1s. Flag idle is defined as more than two consecutive flag characters, not including a closing flag. DSR2 bit
5 is set to a logical 1 while Mark idle is being detected.
DSR2 bit 6 is set to a logical 1 while Flag idle is being detected. The receiver D-channel packet can be aborted at
any time during reception by setting INIT bit 6.
Transmitting D-Channel Packets
The DLC Transmitter is activated when the MSB (second byte) of the 16-bit D-channel Transmit Byte Count
Register (DTCR) is loaded by the microprocessor.
Next, the LIU starts counting the number of consecutive 1s on the E-channel until the number of 1s defined
by the LIU priority mechanism is detected. After the sequence of 1s, the DLC transmitter will begin packet
transmission.
Address bytes for a transmit packet can be handled in
two ways: they can be loaded into the transmit buffer or
loaded into the Transmit Address Register (TAR).
There is one 16-bit TAR which can be loaded by the microprocessor. The bytes loaded into the TAR are transmitted LSB first followed by MSB. For LAPD operation,
the LSB contains the SAPI, and the MSB contains TEI.
This 16-bit address (loaded LSB first) is transmitted
within the address field of the D-channel packet if enabled by setting DMR1 bit 2 to a logical 1. If the TAR is
enabled, the DTCR should be loaded with the number
of bytes to be transmitted excluding the address, flags,
and FCS. If the TAR is disabled, the DTCR should be
loaded with the number of bytes to be transmitted excluding the flags and FCS, and the microprocessor
must load the address to be transmitted as the first two
bytes of the D-channel packet data.
The DLC issues an interrupt when a position is
avail-able in the D-channel Transmit buffer. This interrupt can be disabled by setting DMR3 bit 5 to a logical
0. The DLC also issues an interrupt to the microprocessor to request D-channel data bytes when the D-chan-
40
The D-channel Transmit Byte Count Register is decremented each time a byte of data is transferred from the
D-channel Transmit buffer to the DLC. The count represents the number of bytes left to be transferred, excluding the FCS and flags. If the transmit abort bit (INIT bit
7) is set, the transmit byte count is frozen and indicates
the number of bytes left to transfer, not the number of
bytes transmitted. The last byte of the packet is determined by the D-channel Transmit Byte Count decrementing to zero. When this occurs, DSR2 bit 3 is set to
a logical 1.
After the last byte of the packet is transmitted, the DLC
adds the FCS and closing flag. Then the DLC issues an
interrupt (bit 6 of DSR1) to signify the end of the packet
transmission. This interrupt can be masked by setting
DMR3 bit 1 to a logical 0, and is reset either by reading
DSR1 or when the D-channel Transmit Byte Count
Register is loaded for the next packet.
Once the D-channel Transmit Byte Count has decremented to 0, a second packet may be loaded into the
D-channel Transmit FIFO. If the MSB of the D-channel
Transmit Byte Count Register is loaded prior to the
end-of-transmit packet interrupt, the second packet is
transmitted back-to-back with the previous packet. The
End-of-Transmit Packet interrupt is not set between the
two packets. If the MSB of the D-channel Transmit Byte
Count Register is loaded after the end-of-packet interrupt, the second packet is transmitted once the LIU priority mechanism has been resatisfied.
Collision Detection
The Network Terminator echoes the transmitted
D-channel data back to the DLC in the E-channel bits
of the S-interface frame. If there is a difference between
the data transmitted and the data echoed back, a collision has occurred. The DLC alerts the microprocessor
to this event by asserting the interrupt line (INT) and
setting DER bit 2. If a collision occurs during the transmission of an abort sequence, the interrupt is still issued. The collision detect interrupt can be masked by
setting DMR2 bit 2 to a logical 0.
Am79C30A/32A Data Sheet
D-Channel Receive and Transmit Errors
Non-Integer Number of Bytes
Underflow
A non-integer number of bytes occurs when the number of D-channel bits received between opening and
closing flags is not divisible by eight. If a received
packet consists of a non-integer number of bytes, the
DLC sets bit 1 in the D-channel Error Register (DER) to
a logical 1 when the last byte of the associated packet
is read from the D-channel Receive buffer.
If a received D-channel (including FCS) packet is less
than 5 bytes for a 2-byte address packet, an underflow
error condition occurs, and the DLC sets DER bit 5 to a
logical 1 when the last byte of the associated packet is
read from the D-channel Receive buffer.
Frame Check Sequence Error
If a received packet, including its 16-bit Frame Check
Sequence, is not received perfectly, the DLC sets DER
bit 3 to a logical 1 when the last byte of the associated
packet is read from the Receive buffer.
Receive Packet Abort
If seven contiguous 1s are received while receiving a
packet, the packet will be terminated. DER bit 0 will be
set to a logical 1 when the last byte of the associated
packet is read from the D-channel Receive buffer.
Overflow
Overflow occurs when the total number of D-channel
bytes within a packet (including, only when enabled,
the Frame Check Sequence bytes) exceeds the limit
contained in the D-channel Receive Byte Limit Register. (See Receiving D-channel Packets section.) When
overflow occurs, the DLC terminates the packet, and
sets DER bit 4 to a logical 1 when the last byte of the
associated packet is read from the D-channel Receive
buffer.
Overrun
A D-channel overrun error occurs when the receiver
buffer is full, and another byte is received. This can
happen if the D-channel Receive buffer fills, and is not
read within 425 µs. When this error occurs, the DLC
sets DER bit 6 to a logical 1 and terminates the packet.
Underrun
A D-channel underrun error occurs when an empty
D-channel buffer is transmitted. This can happen if the
D-channel Transmit buffer is not loaded within 375 µs
of the D-channel Transmit buffer Empty interrupt being
asserted (IR bit 0). When this error occurs, the DLC
sets DER bit 7 to a logical 1 and terminates the packet.
Receive Packet Lost
Receive Packet Lost occurs when two outstanding
packets have been received and not serviced (the microprocessor has not read the DCRB register), and a
third packet is received. When this error occurs, DSR2
bit 2 is set to a logical 1 and the incoming packet is terminated (not received).
DLC REGISTERS
The DLC contains the following registers.
Registers
Number of Registers Mnemonic
First Received Byte Address Registers
4
FRAR
Second Received Byte Address Registers
4
SRAR
Transmit Address Register (16-bit)
1
TAR
D-channel Receive Byte Limit Register (16-bit)
1
DRLR
D-channel Receive Byte Count Register (16-bit) (2-word FIFO)
1
DRCR
D-channel Transmit Byte Count Register (16-bit)
1
DTCR
Random Number Generator Registers
2
RNGR
D-channel mode registers
4
DMR
Address Status Register (2-byte FIFO)
1
ASR
Extended FIFO Control Register
1
EFCR
D-channel Transmit buffer Register
—
DCTR
D-channel Receive buffer Register
—
DCRB
D-channel Status Register #1
1
DSR1
D-channel Status Register #2
1
DSR2
D-channel Error Register (2-byte FIFO)
1
DER
Am79C30A/32A Data Sheet
41
Transmit Address Register — (TAR) — Read/Write
Address = Indirect 83H
This register contains the address of the packet to be transmitted if the TAR bit is enabled (DMR1 bit 2).
First Received Byte Address Register — (FRAR1–FRAR4) — Read/Write
Address = Indirect FRAR1–FRAR3 = 81H, FRAR4 = 8CH
These registers contain the value to match against the first byte of the incoming address. If DMR1 bits 4–7 are disabled, these registers are ignored.
Second Received Byte Address Register — (SRAR1–SRAR4) — Read/Write
Address = Indirect SRAR1–SRAR3 = 82H, SRAR4 = 8DH
These registers contain the value to match against the first byte of the incoming address. If DMR1 bits 4–7 are disabled, these registers are ignored.
D-Channel Receive Byte Count Register — (DRCR) — Read
Address = Indirect 89H
This register determines the maximum number of bytes in a received packet.
D-Channel Receive Byte Limit Register — (DRLR) — Read/Write
Address = Indirect 84H
This register contains the total number of received bytes.
D-Channel Transmit Byte Count Register — (DTCR) — Read/Write
Address = Indirect 85H
This register contains the total number of transferred bytes.
Random Number Generator Register — (RNGR1, RNGR2) — Read/Write
Address = Indirect RNGR1 = 8AH, RNGR2 = 8BH
These registers control the operation of the Random Number Generator. When read, they display the random number generated by the chip.
D-Channel Transmit Buffer Register — (DCTB) —Write
D-channel transmit FIFO.
D-Channel Receive Buffer Register — (DCRB) — Read
D-channel receive FIFO.
D-Channel Mode Register 1 — (DMR1) — Read/Write
Address = Indirect 86H
DMR1 controls the enable/disable options for the DLC. It is under sole control of the microprocessor and does not
generate any interrupts. DMR1 is defined in Table 39.
Table 39.
Bit
42
D-Channel Mode Register 1
Logical 1
Logical 0
0
Enable D-channel Transmit Threshold interrupt (see IR bit 0) Disable interrupt (default value)
1
Enable D-channel Receive Threshold interrupt (see IR bit 1)
Disable interrupt (default value)
2
Enable Transmit Address Register
Disable Transmit Address Register (default value)
3
Enable End of Receive Packet interrupt (see DSR1 bit 1)
Disable interrupt (default value)
4
Enable FRAR1/SRAR1
Disable FRAR1/SRAR1 (default value)
5
Enable FRAR2/SRAR2
Disable FRAR2/SRAR2 (default value)
6
Enable FRAR3/SRAR3
Disable FRAR3/SRAR3 (default value)
7
Enable FRAR4/SRAR4
Disable FRAR4/SRAR4
Am79C30A/32A Data Sheet
D-Channel Mode Register 2 — (DMR2) — Read/Write
Address = Indirect 87H
DMR2 is used to enable/disable the interrupts generated in the DER (see DER definition on page 41). DMR2 is controlled by the microprocessor and does not generate interrupts. DMR2 is defined in Table 40.
Table 40.
Bit
D-Channel Mode Register 2
Logical 1
Logical 0 (Default Value)
0
Enable Receive Abort interrupt (see DER bit 0)
Disable interrupt
1
Enable Non-integer Number of Bytes Received interrupt (see DER bit 1)
Disable interrupt
2
Enable Collision Abort Detected interrupt (see DER bit 2)
Disable interrupt
3
Enable FCS Error interrupt (see DER bit 3)
Disable interrupt
4
Enable Overflow Error interrupt (see DER bit 4)
Disable interrupt
5
Enable Underflow Error interrupt (see DER bit 5)
Disable interrupt
6
Enable Overrun Error interrupt (see DER bit 6)
Disable interrupt
7
Enable Underrun Error interrupt (see DER bit 7)
Disable interrupt
D-Channel Mode Register 3 — (DMR3) — Read/Write
Address = Indirect 8EH
Table 41.
Bit
D-Channel Mode Register 3
Logical 1
Logical 0 (Default Value)
0
Enable Valid Address/End of Address interrupt (default value) (see DSR1 bit 0) Disable interrupt
1
Enable End of Valid Transmit Packet interrupt (default value) (see DSR1 bit 6) Disable interrupt
2
Enable Last Byte of Received Packet interrupt (see DSR2 bit 0)
Disable interrupt (default value)
3
Enable Receive Byte Available interrupt (see DSR2 bit 1)
Disable interrupt (default value)
4
Enable Last Byte Transmitted interrupt (see DSR2 bit 3)
Disable interrupt (default value)
5
Enable Transmit buffer Available interrupt (see DSR2 bit 4)
Disable interrupt (default value)
6
Enable Received Packet Lost interrupt (see DSR2 bit 2)
Disable interrupt (default value)
7
Enable FCS transfer to FIFO
Disable FCS transfer to FIFO
(default value)
Am79C30A/32A Data Sheet
43
D-Channel Mode Register 4 — (DMR4) — Read/Write
Address = Indirect 8FH
Table 42.
Bit
7
X
6
X
5
X
4
X
3
X
2
X
1
0
0
0
X
X
X
X
X
X
0
1
X
X
X
X
X
X
1
0
X
X
X
X
X
X
1
1
X
X
X
X
0
0
X
X
X
X
X
X
0
1
X
X
X
X
X
X
1
0
X
X
X
X
X
X
1
1
X
X
X
X
X
0
1
X
X
X
X
X
X
X
0
1
X
X
0
1
1
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D-Channel Mode Register 4
Control
Function
Receiver Threshold
1 byte (EFCR bit 0 = 0)
1 byte (EFCR bit 0 = 1)
2 bytes (EFCR bit 0 = 0)
16 bytes (EFCR bit 0 = 1)
4 bytes (EFCR bit 0 = 0)
24 bytes (EFCR bit 0 = 1)
8 bytes (EFCR bit 0 = 0)
30 bytes (EFCR bit 0 = 1)
1 byte (EFCR bit 0 = 0)
1 byte (EFCR bit 0 = 1)
2 bytes (EFCR bit 0 = 0)
6 bytes (EFCR bit 0 = 1)
4 bytes (EFCR bit 0 = 0)
10 bytes (EFCR bit 0 = 1)
8 bytes (EFCR bit 0 = 0)
14 bytes (EFCR bit 1 = 1)
Mark Idle (default value)
Flag Idle
2-byte (default value)
First Received Byte only
Second Received Byte only
Disable FRAR bit 1 compare (default value)
Enable FRAR bit 1 compare
Transmitter Threshold
Interframe Fill
Address Recognition
C/R Bit Compare
Note:
The receiver and transmitter thresholds can only be changed when the Am79C30A/32A is in Idle mode.
Address Status Register — (ASR) — Read Only
Address = Indirect 91H
Table 43.
Bit
Logical 1
Logical 0 (Default Value)
0
FRAR1/SRAR1 address recognized
No FRAR1/SRAR1 address match
1
FRAR2/SRAR2 address recognized
No FRAR2/SRAR2 address match
2
FRAR3/SRAR3 address recognized
No FRAR3/SRAR3 address match
3
FRAR4/SRAR4 address recognized
No FRAR4/SRAR4 address match
Reserved
Reserved
4–7
44
Address Status Register
Am79C30A/32A Data Sheet
D-Channel Status Register 1 — (DSR1) — Read Only
DSR1 has the format shown in Table 44.
Table 44.
Bit
D-Channel Status Register 1
Logical 1
Logical 0 (Default Value)
0
Valid Address (VA) if the address decode logic is enabled or
End-of-Address (EOA) if the address decode logic is disabled
No valid address
1
End of receive packet
Not end of packet
2
Packet reception in progress
Packet not being received
3
Loopback in operation at Am79C30A/32A
No loopback in operation at Am79C30A/32A
4
Loopback in operation at LIU
No loopback in operation at LIU
5
D-channel back-off not in operation
D-channel back-off in operation
6
End of valid transmit packet
No end-of-transmit packet or no transmission
7
Current transmit packet has been aborted
No transmit packet abort
The DSR1 bits generate interrupts and are set/reset under the conditions shown in Table 45 (in addition to a hardware reset or Idle mode).
Table 45.
Bit Generate Interrupt
DSR1 Interrupts
Bit Set
Bit Reset
0
Yes, if DMR3 bit 0 = 1
Two bytes after an opening flag if a VA is
decoded or address recognition is disabled
When the microprocessor reads DSR1 or
associated DRCR
1
Yes, if DMR1 bit 3 = 1
When a closing flag is received
When the microprocessor reads DSR1 or
associated DRCR
2
No
One byte after the opening flag of any packet,
valid or not
When a flag or an abort is received
3
No
When the operation is in progress
When the operation is not in progress
4
No
When the operation is in progress
When the operation is not in progress
5
No
When the operation is in progress
When the operation is not in progress
6
Yes, if DMR3 bit 1 = 1
When the closing flag is transmitted
When the microprocessor reads DSR1 or when
DTCR is loaded
7
No
When seven 1s and a 0 have been transmitted When the microprocessor reads DSR1 or when
DTCR is loaded
Am79C30A/32A Data Sheet
45
D-Channel Status Register 2 — (DSR2) — Read Only
DSR2 has the format illustrated in Table 46.
Table 46.
Bit
D-Channel Status Register 2
Logical 1
Logical 0 (Default Value)
0
Last byte of received packet
Not last byte of received packet
1
Receive byte available
Receive byte not available
2
Receive packet lost
Receive packet not lost
3
Last byte transmitted
Last byte not transmitted
4
Transmit buffer available
Transmit buffer not available*
5
Mark idle detected (15 or more contiguous 1s)
Mark idle not detected
6
Flag idle detected (more than two contiguous flags) Flag idle not detected
7
Start of second received packet in FIFO
Second packet not yet in FIFO
Note:
*Following RESET, the Transmit buffer Available (bit 4) is set, producing a default value of 10H.
The DSR2 bits generate interrupts and are set/reset under the conditions shown in Table 47 (in addition to a hardware reset or Idle mode).
Table 47.
Bit
46
DSR2 Interrupts
Generate Interrupt
Bit Set
Bit Reset
0
Yes, if DMR3 bit 2 = 1
When last byte of a received packet is read from the
DCRB
When the microprocessor reads the
DSR2
1
Yes, if DMR1 bit 3 = 1
When DCRB contains one or more bytes of data
When DCRB is empty
2
Yes, if DMR3 bit 6 = 1
When two outstanding packets are received and not
serviced, and a third packet is received
When the microprocessor reads
DSR2
3
Yes, if DMR3 bit 4 = 1
When the last byte of a transmit packet is transferred from When the microprocessor reads
the DCTB
DSR2
4
Yes, if DMR3 bit 5 = 1
When the DCTB is available to be loaded with a data byte When the DCTB is full
5
No
When 15 contiguous one bits have been detected in the
incoming D channel
6
No
When more than two contiguous flags are detected on the When a non-flag character is
incoming D channels, not including a closing flag
detected on the incoming D channel
7
Yes, if EFCR bit 1 = 1
When start of second packet is in the receive FIFO
Am79C30A/32A Data Sheet
When the first zero bit is detected
on the incoming D channel
When second receive packet is not
present
D-Channel Error Register — (DER) — Read Only
The DER has the format illustrated in Table 48.
Table 48.
Bit
D-Channel Error Register
Logical 1
Logical 0 (Default Value)
0
Received Packet Abort
No abort received
1
Non-integer number of bits have been received
Integer number of bits received
2
Collision Detected
No error
3
FCS Error
No error
4
Overflow Error
No error
5
Underflow Error
No error
6
Overrun Error
No error
7
Underrun Error
No error
DER bits 0, 1, 3, 4, 5, and 6 are set when the last byte of the associated packet is read from the D-channel Receive
buffer.
The DER bits generate interrupts and are set/reset under the conditions shown in Table 49 (in addition to a hardware
reset).
Table 49.
Bit Generates Interrupt
DER Interrupts
Bit Set
Bit Reset
0
Yes, if DMR2 bit 0 = 1 When seven consecutive 1s are received
within a packet (DSR1 bit 2 = 1)
When the microprocessor reads the DER or
associated DRCR
1
Yes, if DMR2 bit 1 = 1 Upon error condition after closing flag has
been received
When the microprocessor reads the DER or
associated DRCR
2
Yes, if DMR2 bit 2 = 1 See section on collision detection
When the microprocessor reads the DER or when
DTCR is loaded
3
Yes, if DMR2 bit 3 = 1 If error occurs
When the microprocessor reads the DER or
associated DRCR
4
Yes, if DMR2 bit 4 = 1 If error occurs
When the microprocessor reads the DER or
associated DRCR
5
Yes, if DMR2 bit 5 = 1 If error occurs
When the microprocessor reads the DER or
associated DRCR
6
Yes, if DMR2 bit 6 = 1 If error occurs
When the microprocessor reads the DER or
associated DRCR
7
Yes, if DMR2 bit 7 = 1 If error occurs
When the microprocessor reads the DER or when
DTCR is loaded
Extended FIFO Control Register — (EFCR) — Read/Write
Address = Indirect 92H
Bit
7
6
5
4
3
2
1
0
0
X
X
X
X
0
X
X
See Table 20.
Function
Bits 7 and 2 reserved, must be written to 0
Bits 6–3 control attenuation of the analog sidetone path (ASTG)
0
X
X
X
X
0
0
X
Start of Second Received Packet In FIFO interrupt disabled
0
X
X
X
X
0
1
X
Start of Second Received Packet In FIFO interrupt enabled
0
X
X
X
X
0
X
0
Normal mode of FIFO operation
0
X
X
X
X
0
X
1
Extended mode of FIFO operation
Am79C30A/32A Data Sheet
47
Peripheral Port (PP)
Overview
The purpose of the Peripheral Port is to allow external
peripherals to be connected to the DSC/IDC circuit.
There are two basic modes of operation, Serial Bus
Port mode, and IOM-2 Terminal mode. Within IOM-2
Terminal mode, the DSC/IDC circuit may be configured
as any combination of IOM-2 timing/control master or
slave. The definition of the Peripheral Port pins depends on the operating mode of the port, as described
in Table 50.
Serial Bus Port (SBP) Mode
The SBP mode of operation is backwards compatible
with the Revision D DSC circuit serial port and is entered either following a device RESET or if programmed in PPCR1.
In SBP mode, the SCLK output provides a 192-kHz 1X
data clock of programmable polarity. The SBIN and
SBOUT pins support three 8-bit serial data channels,
designated Bd, Be, and Bf. The SFS output provides an
8-kHz serial frame sync pulse eight bit periods in width,
coincident with the Bd channel. The SBP mode timing
is illustrated in Figure 5.
Table 50.
Following a RESET, the SCLK and SFS outputs will default to a high-impedance state, which will be maintained until any MUX connection is programmed (or
until the Peripheral Port is programmed to an IOM-2
mode). SCLK and SFS will remain in a high-impedance
state if the Peripheral Port is explicitly disabled. The
SCLK and SFS signals are synchronized to the received S-interface frame. If there is no S-interface
frame synchronization, the SCLK and SFS signals will
free-run at 192 kHz and 8 kHz respectively.
If the DSC/IDC circuit is programmed to Idle mode, the
SFS output is driven Low but SCLK continues to run. In
Power-Down mode, both the SFS and SCLK outputs
are high-impedance.
IOM-2 Terminal Mode Overview
The IOM-2 Interface standard encompasses both a Linecard mode and a Terminal mode. The Terminal
mode was defined to provide four functions, as follows:
1. Connection of multiple Layer-2 devices to a Layer-1
device (in this case, the Layer-1 device is the S/T Interface LIU). Provision for the connection of
non-IOM-2 devices is included.
2. Programming and control of Layer-1 or Layer-2 devices that do not have a microprocessor interface,
for example, a U-interface transceiver.
Pin Operation versus Peripheral Port Modes
SBP
On
Port
IOM-2 M
Disabled Activated
IOM-2 M
Deactivated
IOM-2 S* Bus IOM-2 S No IOM-2 S No
IOM-2 S*
Bus Reverse Bus Reverse
Bus Reverse Reverse
Deactivated
Deactivated Activated
Activated
SBIN
IN
Z
IN
IN
IN/OD
OD
OD
Z
SBOUT
OUT
Z
OD
Z
OD/IN
Z
IN
Z
SCLK
OUT
Z
OUT
Low
IN
IN
IN
IN
SFS
OUT
Z
OUT
Low
IN
IN
IN
IN
BCL/CH2STRB
OUT
Z
OUT
Low
Z
Z
Z
Z
Pin
IN = Input
OUT = Output
Z = High Impedance
OD = Open Drain Output
Note:
*The Am79C30A is a non-Layer-1 component when operated in the Slave mode; however, it has a microprocessor interface.
As a result, it is required to change the direction of its I/O pins at certain times in order to communicate with both the upstream
Layer-1 device and any downstream peripheral devices. In the IOM-2 Slave mode, the direction of data flow is reversed with
respect to the DSC circuit during Sub-frame 0 and during the deactivated state. The rule is that the upstream Layer-1 device
only uses Sub-frame 0 and does not reverse its pins. Any non-Layer-1 component that does not contain a microprocessor
interface (i.e., program by the DSC circuit over the Monitor channel in Sub-frame 1) uses Sub-frame 0 to talk to the Layer-1
device and Sub-frame 1 to talk to the DSC circuit. It does not reverse its pins.
48
Am79C30A/32A Data Sheet
52 µs
SCLK
192 kHz
LSB
MSB
SBIN or
SBOUT
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Bf
B3
Bd
SFS
41.7 µs
125 µs
Note:
SBIN is sampled on the rising edge of SCLK. SBOUT is changed on the falling edge of SCLK.
Figure 5.
09893H-6
Serial Bus Port Mode Timing
3. Inter-chip communication between devices on the
bus, for instance, data flow between the DSC circuit
MAP and an external speech encryption device.
•
One 16-kbits/s D channel for signaling and data
packets.
•
Two Command/Indicate channels, labeled C/I0, and
C/I1, to provide status and command for devices
connected via the monitor channels. The Command/Indicate channel in the first IOM-2 subframe
consists of four bits, providing 16 states in each direction. In the second subframe the C/I channel is 6
bits, providing 64 states in each direction.
•
Two 64-kbits/s intercommunication channels, labeled IC1 and IC2, to provide additional interdevice
communications bandwidth.
4. Connection of multiple DLCs to the D channel, including access arbitration. This function is referred
to as the TIC channel.
The IOM-2 Terminal mode bus consists of three IOM-2
subframes, each containing 32 bits. This 12-byte frame
is repeated at 8 kHz, resulting in an aggregate data rate
of 768 kbits/s. The frame structure is illustrated in Figure 7, and contains the following channels:
•
Two 64-kbits/s data channels, labeled B1 and B2.
•
Two device programming channels, labeled Monitor
0 and 1. Each channel has an associated pair of MX
and MR handshake bits that control data flow.
All data transmitted on the IOM-2 Interface via the
SBOUT pin is transmitted MSB first, with the exception
of D-channel data, which is transmitted LSB first. The
receiver operates in a compatible way via the SBIN pin.
SFS
MR,MX
MR,MX
SBIN/
B1
B2
MON0 D C/I
IC1
IC2 MON1
C/I
TIC
SBOUT
IOM channel 0
IOM channel 1
IOM channel 2
09893H-7
Figure 6.
IOM-2 Terminal Mode Frame Structure
Am79C30A/32A Data Sheet
49
DSC/IDC Circuit IOM-2 Terminal Mode
Implementation
Data Channels
The B1 and B2 channels are physically the first two
8-bit time slots after the frame sync pulse. When making a MUX connection to these channels, IOM-2 channels B1 and B2 correspond to MUX channels Bd and
Be, respectively. When in an IOM-2 mode, a MUX connection to channel Bf provides access to one of the two
intercommunication channels as selected in PPCR1.
Command/Indicate Channels
The Peripheral Port supports the C/I channels of the
first and second IOM-2 subframes. The Peripheral Port
monitors these two channels, and generates an interrupt any time the received data changes and is stable
for two frames. The received data is read from C/I Receive Data Register 0 or 1, and C/I transmit data is written to C/I Transmit Data Register 0 or 1. When the TIC
bus feature is enabled, C/I0 transmit access to the
IOM-2 Interface is controlled by CITDR0 bit 7, Bus Access Request.
D Channel
If the peripheral Port is configured as IOM-2 master
with TIC bus disabled, the DLC will transmit and receive D-channel data to and from the S Interface
through the LIU. The D-channel data received from the
S Interface is also output on the IOM-2 Interface.
D-channel data received from the IOM-2 Interface is
disregarded. If, however, TIC bus is enabled, the TIC
bus control logic will arbitrate D-channel data flow between the S Interface and either the DLC or IOM-2 Interface based on TIC bus access procedures.
When the Peripheral Port is configured as IOM-2 slave,
the DLC will transmit and receive D-channel data to
and from the IOM-2 Interface. This will be a dedicated
path if the TIC bus feature is disabled, or with DLC access arbitrated according to TIC bus access procedures if the TIC bus feature is enabled. The LIU is not
used in this situation, so there is no D-channel data
flow between the DLC and LIU.
Monitor Channels
Support for the two Monitor channels is provided on a
one-at-a-time basis. A bit in Peripheral Port Control
Register 1 selects which one of the two Monitor channels is utilized at any time.
TIC Bus
The IOM-2 TIC bus control bits reside in the last byte to
the IOM-2 Terminal mode frame (channel 2, byte 4).
The bits and their definitions are shown in Figure 7
Data Upstream (output)
1
1
BAC TBA2 TBA1 TBA0
1
1
Data Downstream (input)
E
E
S/G
1
1
A/B
1
1
Notes:
BAC bit (Bus Accessed): indication to other devices that the TIC bus is being accessed. When 0 the bus is accessed, when 1 it
is free. This bit is driven to zero by the device that gets an address match on the TBA2–0 bits.
TBA2–0 bits (TIC Bus Address): address bit used for arbitration of TIC bus control Assumes Open–Drain bus such that device
with highest zero content in its address has the highest priority. Lowest priority address, which is also the default, is 111.
E-bits (Echo): D-channel Echo bits from the S-bus. Will not be supported by the DSC.
S/G bit (Stop/Go): used to indicate availability of the S-bus D-channel. When 0, the D-channel is clear for transmission. When
1, D-channel transmission should be halted.
A/B bit (Available/Blocked): supplementary bit for D-channel control. 1 indicates D-channel available, 0 D-channel blocked.
Optional, will not be supported by the DSC.
Figure 7.
50
TIC Bus Control Bits and Definitions
Am79C30A/32A Data Sheet
MASTER Mode
DSC is the timing master (FSC and SCLK are outputs)
and control master (can communicate with downstream devices). The configuration of timing master
and control slave is covered within this mode. The pres-
ence of the TIC bus provides D and C/I0 access to all
downstream devices. For control slave applications,
the DSC can disable all IOM-2 channel 1 communications.
B1, B2, D, MON0, C/10, IC1, IC2, MON1, C/I1, S/G(out), TIC(in)
SBOUT
upstream
DSC
SBIN
DD
Downstream
#1
DU
DD
Downstream
#2
DU
downstream
Figure 8.
IOM-2 Master Mode Operation
Am79C30A/32A Data Sheet
51
SLAVE Mode — Bus Reversal Enabled
DSC is the timing slave (FSC and SCLK are inputs)
and control master (can communicate with other down-
stream devices via MONI and C/I1). D and C/I0 arbitration provided by TIC bus capability.
Utransceiver
IC1, IC2, MON1, C/I1
DD
DU
B1, B2, D, MON0, C/I0, S/G(in), TIC(out)
SBOUT
upstream
DSC
SBIN
DD
Downstream
#1
DU
DD
Downstream
#2
DU
downstream
Figure 9.
52
IOM-2 Slave Mode Operation with Bus Reversal
Am79C30A/32A Data Sheet
SLAVE Mode — Bus Reversal Disabled
DSC is the timing slave (FSC and SCLK are inputs)
and control master (cannot communicate with other
downstream devices). D and C/I0 arbitration provided
by TIC bus capability.
DSC
Master
SBOUT
SBIN
B1, B2, D, MON0, C/I0,
IC1, IC2, MON1, C/I1, S/G(in), TIC(out)
SBOUT
upstream
DSC
SBIN
DD
Downstream
#1
DU
DD
Downstream
#2
DU
downstream
Figure 10.
IOM-2 Slave Mode Operation without Bus Reversal
Am79C30A/32A Data Sheet
53
Intelligent NT
DSC to send its D-channel frame to the U-transceiver
on DU by driving S/G low on DD. The S-transceiver
also sets its transmitted E-channel bits on the S-Interface to zero (inversion of received D bits) to prevent all
connected TEs from transmitting data into the D-channel. When the DSC completes its D-channel transmission, it releases the TIC bus by setting BAC=1. The
S-transceiver then mirrors the incoming D bits into the
E-channel, thus behaving as a normal NT with transparent D-channel handling.
Either Slave mode can be used to implement the Intelligent NT configuration. The diagram below depicts this
configuration using DSC Slave mode with bus reversal
disabled.
The U-transceiver operates as the IOM-2 master device, programmed to TE mode and outputting at
1536-kHz DCL. The DSC indicates a D-channel request according to the TIC bus procedure using the
BAC bit on the DU line (BAC=0). The S-transceiver surveys the received D channel and if it is idle, enables the
U-transceiver
Master
DOUT/DD
DIN/DU
B1, B2, D, MON0, C/I0,
IC1, IC2, MON1, C/I1, S/G(in), TIC(out)
SBOUT
upstream
DSC
SBIN
D-channel
DD
S-transceiver
LT-S
E-channel
DU
S Interface
downstream
Figure 11.
54
IOM-2 Intelligent Configuration
Am79C30A/32A Data Sheet
Monitor Channel Procedures
The Monitor channel operates on an event-driven basis; although data transfers on the bus are synchronized to the frame sync, the flow of data is controlled by
a handshake procedure using the outgoing MX and incoming MR bits. Thus, the actual data rate is not fixed,
but is dependent upon the response speed of transmitter and receiver. Figure 12 illustrates the sequence of
events in the monitor handshake procedure.
Idle State
The outgoing MX and incoming MR bits held inactive
for two or more frames indicates that the Monitor channel is Idle in the outgoing direction.
Start of Transmission
The PPCR1 register is programmed to select one of the
two monitor channels. Data is then loaded into the
monitor Transmit Data Register, causing the first data
byte to be presented to the bus as well as an inactive-to-active transition of outgoing MX. The Monitor
channel transmit buffer available interrupt is also generated when data is placed on the bus, indicating that
the next data byte may be written to the buffer. Outgoing MX remains active, and the data is repeated until an
inactive-to-active transition of the incoming MR is received.
Subsequent Transmission
Following detection of the first inactive-to-active transition of incoming MR, all following bytes to be transmitted will be presented to the bus coincident with an
active-to-inactive transition of outgoing MX. The IOM-2
specification defines a general case (Figure 12a) in
which the transmitter waits for an inactive-to-active
transition of incoming MR, and a maximum speed case
(Figure 12c) in which the transmitter achieves a higher
transmission rate by anticipating the falling edge of incoming MR.
The DSC/IDC circuit Monitor channel transmitter implements the maximum speed case as follows: the second
byte is placed onto the bus at the start of the frame following the transition of incoming MR (High to Low), and
a Monitor channel transmit buffer available interrupt is
generated. Simultaneously, outgoing MX is returned inactive for one frame, then reactivated. Note that two
frames of outgoing MX inactive signifies the end of a
message. Outgoing MX and the data byte remain valid
until incoming MR goes inactive. The next byte is transmitted during the next frame, meaning one frame after
incoming MR goes inactive. In this manner, the transmitter is anticipating incoming MR returning active,
which it will do one frame time after it is deactivated, unless an abort is signaled from the receiver. After the last
byte of data has been transmitted, indicated by the
Monitor Transmit Data Register being empty and the
end-of-transmission (EOM) bit being set in PPCR1,
outgoing MX is deactivated in response to incoming
MR going inactive, and left inactive.
First Byte Reception
At the time the receiver sees the first byte, indicated by
the inactive-to-active transition of incoming MX, outgoing MR is by definition inactive. Outgoing MR is activated in response to the activation of incoming MX, the
data byte on the bus is loaded into the Monitor Receive
Data Register, and a Monitor channel receive data
available interrupt is generated. Outgoing MR remains
active until the next byte is received or an end-of-message is detected (incoming MX held inactive for two or
more frames).
Subsequent Reception
Data is received into the buffer on each falling edge of
incoming MX, and a Monitor channel receive data
available interrupt is generated. Note that the data was
actually valid at the time incoming MX became inactive,
one frame prior to becoming active. Outgoing MR is deactivated at the time data is read and reactivated one
frame later. The reception of data is terminated by reception of an end-of-message indication, which is incoming MX remaining inactive for two or more frames.
End-of-Transmission (EOM)
The transmitter sends an EOM in response to the EOM
request bit being set in PPCR1. Once the EOM bit is
set, the EOM is transmitted as soon as the Monitor
Transmit Data Register becomes empty. This is normally done when the last byte of a message has been
transmitted. The DSC/IDC circuit transmits an EOM
simply by not reactivating MX after deactivating it in response to MR going inactive. The EOM request bit in
PPCR1 is automatically cleared when the EOM has
been transmitted, indicating that the monitor transmitter is available for a new message.
Abort
An abort is a signal from the receiver to the transmitter
indicating that data has been missed. The receiver
sends an abort by holding MR inactive for two or more
frames in response to MX going active. An interrupt is
generated when an abort is received.
Flow Control
The transmitter is held off until the Monitor Receive
Data Register is read, since MR is held active until the
receive byte is read. The transmitter will not start the
next transmission cycle until MR goes inactive.
Am79C30A/32A Data Sheet
55
MX
EOM
Transmitter
MX
First Byte
New Byte
Last Byte
MR
Receiver
MR
ACK
ACK
ACK
n • 125 µs 125 µs
a. General Case
MX
EOM
Transmitter
MX
New Byte
MR
Receiver
MR
Abort
Request
b. Abort Request from the Receiver
MX
EOM
Transmitter
MX
First Byte
Second Byte Third Byte
MR
Receiver
MR
First Byte
ACK
Second Byte
ACK
Third Byte
c. Maximum Speed Case
Figure 12.
56
Monitor Handshake Timing
Am79C30A/32A Data Sheet
09893H-8
IOM-2 Activation/Deactivation
DSC/IDC Circuit as Upstream Device (Clock Master)
The IOM-2 Interface includes an activation/deactivation
capability (see Figure 13). Activation and deactivation
can be initiated from either upstream or downstream
components on the bus. When deactivated, the upstream device holds all the clock outputs Low, and the
downstream devices force their open drain data outputs to a High-Z state (seen as a High on the system
bus due to the external pullup resistor). The activation/deactivation procedure is a combination of software handshakes via the C/I channel, and hardware
indications via the clock and data lines. The IOM-2
specification describes both the hardware and software
protocols in detail; the hardware operation supported
by the Am79C30A IOM-2 implementation is outlined in
Figure 13.
Deactivation
SBIN goes Low
Timing Request Interrupt generated
clk pend
(clks off)
D e a c t iva t io n o f t h e IO M -2 I n t e r fa c e f ro m th e
Am79C30A operating as an upstream device is initiated and controlled by the microprocessor. A series of
software handshakes via the C/I channel must be performed before the hardware deactivation can take
place. The upstream device must issue a deactivation
request command on the C/I channel and wait for a deactivation indication from all downstream units. Once
this is received, a deactivation confirmation command
must be sent on the C/I channel by the upstream device. The upstream device will then stop all clocks and
hold them Low. On the Am79C30A, the IOM-2 clocks
(SCLK,SFS, and BCL/CH2STRB) are stopped and
forced Low when the microprocessor clears the activation/deactivation bit in the Peripheral Port Control
Idle
(clks off)
Software clears
Activation bit
Software sets
Activation bit
Software sets
Activation bit
ACTIVE
(clks on)
a. Am79C30A as Upstream Device
Software sets Activation bit
SBIN output forced Low
Idle
(clks off)
(SBIN = Z)
SBIN output forced to Z
(SBIN = 0)
(clks off)
Clock received from
upstream; Timing Request
interrupt generated
Timeout
(clks off)
(SBIN = 0)
(clks on)
Software sets Activation bit
ACTIVE
(clks on)
(SBIN = data)
Clocks stopped by upstream device
a. Am79C30A as Downstream Device
09893H-9
Notes:
This diagram shows only the portions of the IOM-2 activation/deactivation procedures that are affected by the Am79C30A
hardware. The C/I-channel software handshakes are not shown.
Figure 13.
IOM-2 Activation/Deactivation
Am79C30A/32A Data Sheet
57
Register Number 1 (PPCR1). When this bit is cleared,
the data output pin (SBOUT) is also forced to High-Z
(seen as a High on the system bus due to the external
pullup resistor), and the Am79C30A begins monitoring
the data input pin (SBIN) for the presence of a timing
request from any downstream units.
Activation
Activation can be initiated locally by the processor or remotely by one of the downstream units. To activate locally, the processor sets the activation/deactivation bit in
PPCR1 (starting the clocks), and then proceeds through
the software activation protocol on the C/Ichannel. For
remote activation, the upstream device receives a request from the downstream device via the data input pin.
When the data input pin (SBIN) goes Low, Am79C30A
will generate an IOM-2 timing-request interrupt, bit 6 in
the Peripheral Port Status Register (PPSR). The processor must respond to this interrupt, and restart the IOM-2
clocks by setting the activation/deactivation bit in
PPCR1. Once the clocks are running, the downstream
device can request full activation via the C/I channel
using the IOM-2 software protocol.
DSC/IDC Circuit as a Downstream Device
(Clock Slave)
Deactivation
Deactivation is normally initiated by the upstream device as described above. When the deactivation request is received by the downstream device over the
C/I channel, the processor must respond by sending
the deactivation indication over the C/I channel. The
upstream device will then send the deactivation confirmation command over the C/I channel and stop the
IOM-2 clocks. The Am79C30A will detect that the clock
has stopped (defined as no clock pulse received for
650 ns) and force itself to the deactivated state. In the
deactivated state, SBIN, and SBOUT are both forced to
a High-Z state, and the SCLK input is monitored for any
rising edge that would indicate an activation request
from the upstream device.
Activation
Once again, activation can originate from either the upstream or the downstream device. To activate the interface from the downstream device, the processor sets
the activation/deactivation bit in the PPCR1 register.
This will force the Am79C30A to pull its data output pin
(SBIN in this case, since the I/O pin definition is reversed when talking to the upstream device) Low,
causing the upstream device to start the IOM-2 clocks.
Once the clocks are running, as indicated by SCLK
input going High, the Am79C30A will generate an
IOM-2 timing request interrupt (bit 6 in PPSR). The processor must respond to the interrupt by loading the
proper C/I command response into C/ITRDO, then
clearing the activation/deactivation bit in PPCR1. This
will release the data output pin (SBIN) from being held
58
Low and allow the processor to complete the activation
procedure by sending the proper commands over the
C/I channel.
When the activation is originated from the upstream
device, the Am79C30A will generate an IOM-2 timing
request interrupt (bit 6 in PPSR) when the IOM-2clocks
become active as indicated by the SCLK input pin
going High. The Am79C30A will begin normal IOM-2
transmission/reception as soon as SCLK appears; no
intervention from the microprocessor is required. However, the processor must respond to the interrupt and
perform the normal C/I channel software handshakes
before activation will be complete.
TIC Bus Operation
C/I0 Channel Arbitration
Software control for the IOM-2 Bus Accessed (BAC) bit
will be added at bit 7 of CITDR0, which is currently reserved. It will be referred to as the BAR, “Bus Access
Request” bit. This bit will be used to gain access to the
C/I0 channel when TIC bus supp or t is enabled
(PPCR3.3=1). The BAR bit should be set whenever the
DSC has C/I0 data available to transmit. When
CITDR0.7=1, the TIC bus will arbitrate access to the
C/I0 channel with other devices on the IOM-2 interface
using the TIC address programmed into PPCR3.2–0.
The TIC bus control logic will check to see if the BAC
bit on the line is 0 or 1 to determine if another downstream device currently owns the bus. If zero, the DSC
will wait. Once a one is detected in BAC, the logic will
place the DSC's TIC bus address on the open drain
output. It will then sample this output with the IOM-2 received data strobe timing to check for conflict with other
downstream devices. If the received TIC address and
the contents of PPCR3.2–0 match, the logic will set the
BAC output to “0” indicating to other downstream devices that the DSC has taken control of the D and C/I0
channels.
After it sets its BAC output to 0, the logic will compare
the TIC address on the line with PPCR3.2–0 in one
more frame to ensure ownership of the bus. If a miscompare occurs, the DSC will set its BAC output to 1
and return to the beginning of arbitration.
Once access is gained, the D and C/I0 channels are
the possession of the DSC. This allows the DSC to
complete C/I0 communication with the Layer 1 device
without interruption from other downstream devices.
(Since the TIC bus is used for arbitration of both D and
C/I0 channel communication, gaining access for one
implicitly gives you access to the other). After the DSC
completes C/I0 communication, software should set
CITDR0.7=0 to allow other downstream devices access to the D and C/I0 channels. The logic will set the
BAC bit output of the DSC back to 1, as long as the
Am79C30A/32A Data Sheet
DSC has no D-channel communications also in
progress.
A priority scheme is included to prevent the DSC from
dominating the bus. A new bus access will not be allowed until the device detects BAC bit set to 1 in two
successive frames.
Care must be taken in use of the Bus Access Request
bit (CITDR0.7). As stated above, once access is gained
through use of this bit, the DSC will control the D and
C/I0 channels as long as it remains set. Software must
remember to clear this bit to allow other devices access.
D-Channel Arbitration
When the TIC bus feature is enabled (PPCR3.3=1), the
DLC will automatically request TIC bus access without
software intervention. The access procedure is much
the same as the C/I0 channel above.
The TIC bus control logic will check to see if the BAC
bit on the line is 0 or 1 to determine if another downstream device currently owns the bus. If zero, the DSC
will wait. Once a one is detected in BAC, the logic will
place the DSC's TIC bus address on the open drain
output. It will then sample this output at the IOM-2 received data strobe point to check for conflict with other
downstream devices. If the received TIC address and
the contents of PPCR3.2-0 match, the logic will set the
BAC output to 0 indicating to other downstream devices that the DSC has taken control of the D and C/I0
channels.
After is sets its BAC output to 0, the logic will compare
the TIC address on the line with PPCR3.2-0 in one
more frame to ensure ownership of the bus. If a miscompare occurs, the DSC will set its BAC output to 1
and return to the beginning of arbitration.
Once access is gained, the D and C/I0 channels are
the possession of the DSC. This allows the DSC to
complete D-channel communications with the Layer 1
device without interruption from other downstream devices. After the DSC completes D-channel communication, logic will set the DSC's BAC bit output back to 1,
as long as the BAC request bit (CITDR0.7) is not set.
This allows other downstream devices access to the D
and C/I0 channels. If CITDR0.7=1, the device assumes
C/I0 communication is still in progress and the BAC
output remains 0 until software clears CITDR0.7.
A priority scheme is included to prevent the DSC from
dominating the bus. A new bus access will not be allowed until the device detects BAC bit set to 1 in two
successive frames.
Am79C30A/32A Data Sheet
59
Peripheral Port Registers
The PP contains the following registers:
Registers
# of Registers
Mnemonic
Peripheral Port Control Register
3
PPCR1, PPCR2, PPCR 3
Peripheral Port Status Register
1
PPSR
Peripheral Port Interrupt Enable Register
1
PPIER
Monitor Transmit Data Register
1
MTDR
Monitor Receive Data Register
1
MRDR
C/I Transmit Data Register
2
CITDR0, CITDR1
C/I Receive Data Register
2
CIRDR0, CIRDR1
Peripheral Port Control Register 1 (PPCR1) Default = 01 Hex
Address = Indirect C0 Hex, Read/Write
7
6
5
4
3
2
1
0
MONTR
ABORT
RQST
MONTR
ENABL
MONTR
CHANL
SELECT
MONTR
EOM
RQST
IC
CHANL
SELECT
IOM 2
ACTV/
DEACT
PORT
MODE
SELECT
BIT 1
PORT
MODE
SELECT
BIT0
Bit
Function
7
Monitor Channel Abort Request—This bit is automatically cleared during RESET or manually by software as follows:
to send an ABORT message, software should set this bit, wait at least two frames, then clear the bit.
6
Monitor Channel Enable—This bit only affects IOM-2 operation. When set, the selected monitor channel is enabled.
When cleared, both monitor channels are disabled. Whenever the monitor channel is disabled, the Monitor Transmit and
Receive Data Register (MTDR, MRDR) are updated to their default states: MTDR = FFH, MRDR = 00H.
5
Monitor Channel Select—This bit only affects IOM-2 operation. When set, Monitor channel 1 is used (second
subframe). When cleared, Monitor channel 0 is used (first subframe).
4
Monitor End-of-Message Request—When set, this bit forces the Monitor channel transmitter to send an EOM once all
data written into the Monitor Transmit Data Register has been transmitted. This tells the receiving device that the
message is complete. The bit is cleared by hardware when the EOM is sent by reset or by software.
3
IC Channel Select—This bit only affects IOM-2 operation. When set, the IC2 time slot is used (sixth octet after the frame
sync). When cleared, the IC1 time slot is used (fifth octet after the frame sync). The unused channel is always placed in
a high-impedance state.
2
IOM-2 Activation/Deactivation Bit—This bit only affects IOM-2 operation. Note that this bit controls only the starting
and stopping of SCLK, BCL/CH2STRB, SFS, and the state of the SBIN/SBOUT pins; this alone does not constitute
activation or deactivation of the IOM-2 bus. The activation/deactivation procedure involves the exchange of a series of
commands and indications over the C/I channel. This procedure, including a state diagram, is detailed in the IOM-2
specification.
IOM-2 Master mode—This bit is set by software. When deactivated, the master will turn on SCLK, BCL/CH2STRB, and
SFS clocks via software by setting this bit when the SBIN pin is pulled Low, indicating that a downstream device wishes
to communicate over the interface.
The IOM-2 activation/deactivation bit is cleared by software or reset. When cleared, the clocks are stopped, and SBIN is
monitored for the reactivation request from the slave (SBIN held Low). [Reset defaults the Peripheral Port to SBP
operation.]
IOM-2 Slave mode—This bit is set by software to initiate an activation request to the master. When set, the SBIN pin is
driven Low, and held Low until the activation/deactivation bit is cleared by software. In response to SBIN going Low the
master will start SCLK, which generates a timing request interrupt in the DSC circuit. The activation/deactivation bit is
cleared by software in response to this interrupt.
60
Am79C30A/32A Data Sheet
Peripheral Port Control Register 1 (PPCR1) — (continued)
Bit
Function
1–0
Port Mode Select Field—These two bits select the configuration of the Peripheral Port as follows.
Bit
1
0
Function
0
0
Port Disabled
0
1
SBP mode enabled
1
0
IOM-2 Slave mode enabled
1
1
IOM-2 Master mode enabled
When the port is disabled, SBOUT, SBIN, and all port-related clocks are placed in a high-impedance state.
When the DSC circuit is reset, this bit field is set to 01, and the port is not enabled until a MUX MCR register is written
to. If this bit is cleared prior to such a path being programmed, the port will remain disabled until the bit is set via a
software write operation.
Peripheral Port Status Register (PPSR)
Default = Bit 1 = 1, Bits 6–2 and 0 = 0, Bit 7 is Indeterminate
Address = Indirect C1 Hex, Read
7
6
5
4
3
2
1
0
RSRVD
IOM-2
TIME
RQST
CHNG
IN
C/I 1
DATA
CHNG
IN
C/I 0
DATA
MONTR
ABORT
RECVD
MONTR
EOM
RECVD
MONTR
XMIT
BUFFR
AVAIL
MONTR
RECV
DATA
AVAIL
The Peripheral Port Status Register presents various status conditions to the user, and is only used in the IOM-2
mode. Each of these conditions can generate an interrupt to the user. The interrupts are enabled via the Peripheral
Port Interrupt Enable Register. The state of the respective interrupt enable bits does not affect the setting of bits in
this register. Bits 6, 3, and 2 are cleared when this register is read. Bit 1 is cleared when the Data Register is written,
and bit 0 is cleared when the Data Register is read. In addition, bits 3, 2, 1, and 0 are cleared when the Monitor
channel is disabled (via bit 6 of the PPCR1 Register). Because bit 7 is reserved, the default value of this register is
either 02H or 82H.
Bit
Function
6
IOM-2 Timing Request—When the DSC circuit is the upstream device (master mode), this bit is set by hardware to
indicate that a downstream device has requested the starting of the IOM-2 clocks. The clocks are started by software.
This bit does not indicate the receipt of an activation request on the C/I channel. When the DSC circuit is the downstream
component (slave mode), this bit is set in response to SCLK starting (going High) when the bus is deactivated.
5
4
3
2
1
0
Notes:
1. The DSC circuit will not exit Power-Down mode in response to either a timing request or the clocks being started if
this interrupt is masked. It is essential that an interrupt be generated when the DSC circuit leaves Power-Down mode.
Otherwise, power consumption could increase significantly without the processor’s knowledge.
Change in C/I 1 Channel Status—This bit is set by hardware to indicate that the contents on the receive side of C/I
channel 1 have changed since the C/I Receive Data Register was last read.
Change in C/I 0 Channel Status—This bit is set by hardware to indicate that the contents on the receive side of C/I
channel 0have changed since the C/I Receive Data Register was last read.
Monitor Channel Abort Request Received—This bit is set by hardware to indicate that an abort request has been
received on the monitor channel. This indicates that the receiver on the other end of the Monitor channel has failed to
receive the transmitted data correctly and requests that the current transmission be discontinued and the data
transmission repeated via software.
Monitor Channel End-of-Message Indication Received—This bit is set by hardware to indicate that an abort request
has been received on the monitor channel. This indicates that the message currently being received has concluded.
Monitor Channel Transmit Buffer Available—This bit is set by hardware to indicate that a new byte of data can be
loaded into the Monitor Transmit Data Register.
Monitor Channel Receive Data Available—This bit is set by hardware to indicate that a byte of data has been received
on the monitor channel and is available in the Monitor Receive Data Register.
Am79C30A/32A Data Sheet
61
Peripheral Port Interrupt Enable Register (PPIER) = 1
Default = Write = 00 Hex, Read = Bit 7 = 1, Bits 6–0 = 0
Address = Indirect C2 Hex, Read/Write
7
6
5
4
3
2
1
0
PP/MF
INT EN
ENABL
IOM-2
TIME
RQST
ENABL
CHNG
IN C/I1
DATA
ENABL
CHNG
IN C/I0
DATA
ENABL
MONTR
ABORT
RECVD
ENABL
MONTR
EOM
RECVD
ENABL
MONTR
XMIT
BUFFR
AVAIL
ENABL
MONTR
RECV
DATA
AVAIL
The Peripheral Port Interrupt Enable Register provides an individual interrupt-enable bit corresponding with eachof
the status conditions in the Peripheral Port Status Register. When set, the interrupt is enabled. Clearing the bit disables the interrupt. These bits are set and cleared by software.
Bit
Function
7
PP/MF Interrupt Enable—When set, this bit enables the Peripheral Port and Multiframing interrupts. When cleared, the
PP and MF interrupts are disabled.
Notes:
To ensure proper interrupt reporting, software must disable PP/MF interrupts when the interrupt routine is entered and
enable them when exiting.
Monitor Transmit Data Register (MTDR) Default = FF Hex
Address = Indirect C3 Hex, Write
7
6
5
4
3
2
1
0
DATA
BIT 7
(MSB)
DATA
BIT 6
DATA
BIT 5
DATA
BIT 4
DATA
BIT 3
DATA
BIT 2
DATA
BIT 1
DATA
BIT 0
(LSB)
The Monitor Transmit Data Register is the user-visible portion of the Monitor channel Transmitter Data buffer. Data
is written into this register by the user in response to a monitor transmit buffer available interrupt. It is then transmitted
to the receiver on the other side of the IOM-2 bus. The MTDR is emptied when the PP is reset.
Monitor Receive Data Register (MRDR) Default = 00 Hex
Address = Indirect C3 Hex, Read
7
6
5
4
3
2
1
0
DATA
BIT 7
(MSB)
DATA
BIT 6
DATA
BIT 5
DATA
BIT 4
DATA
BIT 3
DATA
BIT 2
DATA
BIT 1
DATA
BIT 0
(LSB)
The Monitor Receive Data Register is the user-visible portion of the Monitor channel Receiver Data buffer. Data is
written into this register by the hardware as it is received over the monitor channel. A monitor data available interrupt
is generated when the register is loaded. The register is overwritten by hardware only after the register has been
read. The default on reset is 00 hex.
62
Am79C30A/32A Data Sheet
C/I Transmit Data Register 0 (C/ITDR0) Default = 0F Hex
Address = Indirect C4 Hex, Write
7
Bus Access
Request
6
RSRVD
5
RSRVD
4
RSRVD
3
C/I0
DATA
BIT 3
(MSB)
2
1
0
C/I0
DATA
BIT 2
C/I0
DATA
BIT 1
C/I0
DATA
BIT 0
(LSB)
The C/I Transmit Data Register 0 is the user-visible portion of the C/I channel 0 transmitter. Data can be written into
this register by the user at any time and is transmitted continuously during each subsequent frame until changed.The
register is set to its default value, 0F hex (C/I channel idle), by reset or disabling of the Peripheral Port. Bus access
request bit-When set, the DSC will attempt to gain access to the C/I0 channel if TIC bus is enabled.
C/I Receive Data Register 0 (C/IRDR0) Default = XF Hex
Address = Indirect C4 Hex, Read
7
RSRVD
6
RSRVD
5
RSRVD
4
3
2
1
0
RSRVD
C/I0
DATA
BIT 3
(MSB)
C/I0
DATA
BIT 2
C/I0
DATA
BIT 1
C/I0
DATA
BIT0
(LSB)
The C/I Receive Data Register 0 contains data valid for two frames from C/I Receive channel 0. The register is set
to its default value of XF hex by a reset or the disabling of the Peripheral Port.
C/I Transmit Data Register 1 (C/ITDR1) Default = 3F Hex
Address = Indirect C5 Hex, Write
7
RSRVD
6
5
4
3
2
1
0
RSRVD
C/I1
DATA
BIT 5
(MSB)
C/I1
DATA
BIT 4
C/I1
DATA
BIT 3
C/I1
DATA
BIT 2
C/I1
DATA
BIT 1
C/I1
DATA
BIT 0
(LSB)
The C/I Transmit Data Register 1 is the user-visible portion of the C/I channel 1 transmitter. Data can be written into
this register by the user at any time. It is transmitted continuously during each subsequent frame until changed. The
register is set to its default value, 3F hex (C/I channel idle), by reset or disabling of the Peripheral Port.
C/I Receive Data Register 1 (C/IRDR1)
Default = Bits 7 and 6 are Indeterminate, Bits 5–0 = 1
Address = Indirect C5 Hex, Read
7
RSRVD
6
5
4
3
2
1
0
RSRVD
C/I1
DATA
BIT 5
(MSB)
C/I
DATA
BIT 4
C/I1
DATA
BIT 3
C/I1
DATA
BIT 2
C/I1
DATA
BIT 1
C/I1
DATA
BIT 0
(LSB)
The C/I Receive Data Register 1 contains the data (valid for two frames) from C/I Receive channel 1. The register
is set to its default value by a reset or the disabling of the Peripheral Port.
Am79C30A/32A Data Sheet
63
Peripheral Port Control Register 2 (PPCR2)
Default = Bits 7, 6, and 0 = 0, Bit 5 = 1, Bits 4–1 are Indeterminate*
Address = Indirect C8 Hex, Read/Write
7
6
5
4
3
2
1
0
REV
CODE
BIT 2
(MSB)
REV
CODE
BIT 1
REV
CODE
BIT 0
(LSB)
RSRVD
RSRVD
RSRVD
RSRVD
SCLK
INVRT
ENABL
The Peripheral Port Control Register 2 controls the inversion of the SCLK output in SBP mode. This provides flexibility in the connection of peripheral devices to the DSC circuit. The hardware revision code is also contained in this
register, which allows software to identify the revision of the hardware.
Note:
* The default value is revision-level dependent. Revision J will report a hardware revision code of 110.
Bit
Function
7–5
Hardware Revision Code—This read-only field reports the hardware revision level. Revision J of the DSC circuit will
report a hardware revision code of 110. The hardware revision codes for E and H are 100, 010, respectively.
SCLK Inversion Enable—When set, the SCLK output is inverted in SBP mode. When cleared, the SCLK output is
identical to the Revision D DSC circuit. This bit should not be changed while SCLK is enabled.
0
Peripheral Port Control Register 3 (PPCR3)
Default = Bits 7–5 are Indeterminate, Bit 4=1, Bit 3=0, Bits 2-0= 1
Address = Indirect C9 Hex, Read/Write
Bit
Function
7–5
RESERVED
4
SLAVE Mode Bus Reversal—PPCR3.4 controls the bus reversal function of the DSC’s IOM-2 SLAVE mode. By default
(PPCR3.4=1) the Slave bus reverses to ensure backwards compatibility with previous revisions. When PPCR3.4=0 the
IOM-2 bus will not reverse in SLAVE mode. This assures slave compatibility of the control function and allows use with
devices such as the ISAC-S.
3
TIC Bus Enable—PPCR3.3 controls enabling and disabling of TIC bus operation. When PPCR3.3=0 which is the default
condition, the IOM-2 bus will not support the TIC bus feature to ensure backwards compatibility with previous IOM-2
capable revisions of the 79C30A. The TIC bus control logic features are only enabled if PPCR3.3=1.
Features enabled when PPCR3.3=1
S/G bit
When the DSC is in IOM-2 MASTER mode the CTS output of the LIU is used to drive the transmitted S/G bit. This signal
indicates D-channel Clear To Send status and is set when the LIU collision detection logic fulfills the programmed priority
level requirements.
When in IOM-2 SLAVE mode the received S/G bit is used as the Clear To Send input into the DLC block.
TIC Address Bus and Bus Accessed
2–0
64
Refer to TIC bus operation section.
TIC Bus Address—Device address to be used on TIC bus. Default is 111.
Am79C30A/32A Data Sheet
APPLICATIONS
ISDN Feature Phone with Parallel and Serial Data
Ports Plus Other Peripherals
ISDN Feature Phone
This basic feature phone is the ISDN equivalent to the
common analog phone. The keypad can be a simple
four-by-four single-pole switch-matrix or a larger-matrix
to provide full-key system features. The display option
illustrated in Figure 14 can be included in any of theapplications shown in this section.
Access to the CCITT R reference interface is provided
via both the serial and parallel ports in Figure 15. This
application may easily have voice capability added by
using a DSC circuit in place of the IDC circuit. Figure 16
illustrates applications with increased B-channel data
processing requirements.
Am79C30A DSC Circuit
Audio
Processor
Telephone
Speaker
B-Channel
MUX
PP
Hook Switch
Surge
Protection
S/T
Interface
D-Channel
DLC
MPI
OSC
LIU
MCLK
Interrupt
RAM
ROM
Power Reversal Interrupt
Microcontroller
Power
Controller
5V
Keypad
LCD Display
Figure 14.
09893H-10
ISDN Telephone
Am79C30A/32A Data Sheet
65
Speaker
PSB2110 ISGN Terminal
Adaptor Circuit
Terminal
Interface
Tone
Am79C32A DSC Circuit
V.110 Processor
Serial
Port
Terminal
Port
UART
HDLC
FIFO
FIFO
PP
B-Channel
MUX
OSC
MPI
LIU
Surge
Protection
S/T Interface
D-Channel
DLC
Microprocessor Interface
MCLK
Interrupts
Power Reversal Interrupt
3
Power
Controller
Microcontroller
RAM
ROM
5V
09893H-11
Figure 15.
66
Terminal Adapter (V.110/V.120) With Voice Upgrade Capability
Am79C30A/32A Data Sheet
Analog
Telephone
Interface
Am85C30 or PSB82525
Data Link
Controller
Am79C30A DSC Circuit
Audio
Processor
Data Link
Controller
PP
B-Channel
MUX
Surge
Protection
LIU
S/T
Microprocessor Interface
MPI
DMA
Controller
D-Channel
DLC
80188
DMA
Dual-Port Dual-Port
RAM
RAM
Controller Interface
Timers
ROM
Optional Program
DRAM
Memory
Controller
Interrupts
Am85C30/PSB82525
CPU
Chip
Selects
DSC Circuit
Memory
PC Bus
Interface
Clock
PC Bus
Figure 16.
PC Add-On Board (1 or 2 Data Channels)
Am79C30A/32A Data Sheet
09893H-12
67
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
DC output current, LS1, LS2 only . . . . . . . . . 100 mA
Storage temperature –65°C to +150°C
Ambient temperature
with power applied . . . . . . . . . . . . . –55°C to +125°C
Supply voltage to ground,
potential continuous . . . . . . . . . . . . . . . 0 V to +7.0 V
Lead temperature (soldering, 10 sec) . . . . . . . . 300°C
Maximum power dissipation . . . . . . . . . . . . . . . 1.5 W
Voltage from any
pin to VSS . . . . . . . . . . . . .VSS – 0.5 V to VCC + 0.5 V
DC input/output current
(except LS1, LS2) . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Operating Ranges
Commercial (C) devices
Operating VCC range with respect
to VSS . . . . . . . . . . . . . . . . . . . . . . . . .4.75 V to 5.25 V
Ambient temperature (TA) . . . . . . . . . . . 0°C to +70°C
Operating Ranges define those limits between which the
functionality of the device is guaranteed.
DC Characteristics over Commercial Operating Ranges (unless otherwise specified)
Parameter Symbol Parameter Descriptions
Test Conditions
VIH
Input High Level, except XTAL2
VIH2
Input High Level XTAL2
Preliminary
Unit
Min
Max
2.0
VCC + .25
V
0.80 V CC
VCC + .25
V
VIL
Input Low Level
0.80
V
VOL
Output Low Level, except SBOUT
IOL = 2 µA
0.40
V
Output Low Level, SBOUT only
IOL = 7 µA
0.40
Output High Level
IOH = –400 µA
VOH
VSS – 0.25
= –10 µA
IOL
Output Leakage Current
0 < VOUT < VCC
V
2.4
0.90 V CC
± 10
µA
Digital Inputs
± 10
µA
LIN1/LIN2
± 200
µA
5.5 (TYP)
µA
10 (TYP)
pF
10 (TYP)
pF
Output in High-Z State
IIL
Input Leakage Current
0 < VIN < VCC
XTAL2
CI
CO
68
Input Capacitance
Temp = 255C
Digital Input
Freq = 1 MHz
Output Capacitance
Temp = 255C
Digital Input/Output
Freq = 1 MHz
Am79C30A/32A Data Sheet
Table 51.
Revision E Power Specifications for CCITT-Restricted Mode Phone Operation
Parameter Parameter
Symbol Descriptions
Preliminary
Test Conditions
Unit
Typ
Max
4
5
mW
20
25
mW
ICC0
VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Power-Down;
VCC Supply Current
Clocks & Oscillator Stopped; LIU Receiver Enabled; S Interface
(Power-Down mode)
Silent (INFO 0)
ICC1
VCC Supply Current
(Idle mode)
ICC2
VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Active, Data Only;
VCC Supply Current fMCLK = 3.072 MHz; LIU Receiver and Transmitter Enabled; S
(Active; Call Set-Up) Interface Activated with Data on D-Channel Only; S-interface
Load = 50 ohms
80
105
mW
ICC3
VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Active Voice &
Data; fMCLK = 384 MHz; LIU Receiver and Transmitter Enabled;
VCC Supply Current S Interface Activated with Data on D-channel and one
(Active; Voice mode) B-channel; S-interface Load = 50 ohms, AINA = –15 dBm0,
1-kHz Sine Wave; EAR1/EAR2 = –15 dBm0, 1-kHz Tone
Driving 600 ohms
155
190
mW
ICC4
VCC Supply Current
(Active; Ringing, No
Load*)
VCC = 5.25 V; VIH =VCC; VIL = VSS; mode = Active, Data Only;
fMCLK = 384 kHz; LIU Receiver and Transmitter Enabled, S
Interface Activated with Data on D-channel Only; S-Interface
Load = 50 ohms; Secondary Tone Ringer Enabled at 0 dB, 400
Hz, No Load
125
150
mW
VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Idle, Data Only;
fMCLK = 3.84 kHz; LIU Receiver Enabled; S Interface Silent
(INFO 0)
Note:
All power measurements assume PP disabled or in IOM-2 Deactivated mode.
(V
,peak )
OUT
( V CC )
*Power consumption with the output loaded will be I CC 4 + ----------------------------------
R LOAD
AC CHARACTERISTICS
VCC = 5 V ± 5%; VSS = 0 V; TA = 0°C to 70°C; MCLK = 3.072 MHz
Table 52.
MAP Analog Characteristics (Am79C30A only)
Parameter
Parameter Descriptions
Symbol
Test Conditions
Preliminary
Min
Analog Input Impedence
AINA or AINB to AREF
–1.25 V < V IN < +1.25 V
fIN < 4 kHz
200
VIOS
Allowable Offset Voltage at
AINA or AINB
with respect to AREF pin
–5
LLS
Allowable Load LS1 to LS2
ZIN
LEAR
Allowable Load EAR1 to
EAR2
LAREF
Allowable Load AREF to VSS
or VCC
VAREF
Analog Reference Voltage
Typ
Max
Unit
Kohm
+5
mV
2.4
V
RLOAD > 40 ohms and
CLOAD < 100 pF
RLOAD > 130 ohms
and
CLOAD < 100 pF
RLOAD > 1 Kohm
and
CLOAD < 100 pF
2.1
Am79C30A/32A Data Sheet
2.25
69
MAP Transmission Characteristics
(Am79C30A only)
The codec is designed to meet CCIIT Recommendation G.714 requirements for signal to distortion, gain
tracking, frequency response, and idle channel noise
specification as defined in Table 53. Verification of conformance to G.714 is by device characterization. Production testing of individual par ts includes those
parameters shown in Table 54.
Half-channel parameters are specified from AINA or
AINB input pins to a B channel for the transmit path,
Table 53.
and from a B channel to EAR1/EAR2 or LS1/LS2 pins
measured differentially for the receive path. These parameters are applicable for both A- or µ-law conversion.
(A-law assumes psophometric filtering, and µ-law assumes c-message weighting). All parameters are specified with the GR, X, R, GX and GER filters disabled;
STG filter is enabled but programmed for infinite attenuation.
All values are for V cc=5V +5%, TA = 0–70°C, and programmable filters/gains disabled (0 dB, flat) unless otherwise indicated.
MAP Transmission Characteristics (Am79C30A only)
Parameter
Symbol Parameter Descriptions
Test Conditions
Preliminary
Min
Typ
Max
Unit
+0.25
+0.9
dB
dB
dB
dB
dB
dB
dB
+0.25
+0.9
dB
dB
dB
dB
dB
dB
TXD
500 Hz–600 Hz
Transmit Group Delay Variation vs. Frequency at
600 Hz–1000 Hz
–10 dBm0 Relative to Minimum Delay Frequency—
1.0 kHz–2.6 kHz
see Figure 18
2.6 kHz–2.8 kHz
750
380
130
750
µs
µs
µs
µs
RXD
500 Hz–600 Hz
Receive Group Delay Variation vs. Frequency at
600 Hz–1000 Hz
–10 dBm0 Relative to Minimum Delay Frequency—
1.0 kHz–2.6 kHz
see Figure 22
2.6 kHz–2.8 kHz
750
380
130
750
µs
µs
µs
µs
TXF
*50 Hz–60 Hz
< 300 Hz
0.3 kHz–3.0 kHz
Transmit Frequency Response (Attenuation vs.
Frequency Relative to –10 dBm0 at 1020 Hz)—see 3.0 kHz–3.4 kHz
3.4 kHz–3.6 kHz
Figure 17
3.6 kHz–3.9 kHz
3.9 kHz–4.0 kHz
24.0
–0.25
–0.25
–0.25
–0.25
0.0
9.0
RXF
<300 Hz
0.3 kHz–3.0 kHz
Receive Frequency Response (Attentuation vs.
3.0 kHz–3.4 kHz
Frequency Relative to –10 dBm0 at 1020 Hz)—see
3.4 kHz–3.6 kHz
Figure 21
3.6 kHz–3.9 kHz
3.9 kHz–4.0 kHz
–0.25
–0.25
–0.25
–0.25
0.0
9.0
TXSTD
Transmit Signal/Total Distortion vs. Level; CCITT
Method 2, 1020 Hz (Transmit Gain = 0dB)—See
Figure 20
0 to –30 dBm0
–40 dBm0
–45 dBm0
35.0
29.0
24.0
dB
dB
dB
RXSTD
Receive Signal/Total Distortion vs. Level; CCITT
Method 2, 1020 Hz (Transmit Gain = 0dB)—See
Figure 24
0 to –30 dBm0
–40 dBm0
–45 dBm0
35.0
29.0
24.0
dB
dB
dB
TXGT
+3 to –40 dBm0
Transmit Gain Tracking vs. Level; CCITT Method 2,
–40 to –50 dBm0
1020 Hz (Transmit Gain = 0 dB)—See Figure 19
–50 to –55 dBm0
–0.3
–0.6
–1.6
+0.3
+0.6
+1.6
dB
dB
dB
RXGT
+3 to –40 dBm0
Receive Gain Tracking vs. Level; CCITT Method 2,
–40 to –50 dBm0
1020 Hz (Receive Gain = 0 dB)—See Figure 23
–50 to –55 dBm0
–0.3
–0.6
–1.6
+0.3
+0.6
+1.6
dB
dB
dB
–82
–79
–76
–73
–70
–78
–75
–72
–69
–66
dBm0
dBm0
dBm0
dBm0
dBm0
–90
–80
–85
–75
dBm0
dBm0
TXICN
Transmit Idle channel Noize AINA or AINB
Connected to AREF
GX =
GX =
GX =
GX =
GX =
0 dB, GA = 0 dB
6 dB, GA = 0 dB
6 dB, GA = 6 dB
6 dB, GA = 12 dB
6 dB, GA = 18 dB
RXICN
Receive Idle channel Noise
GR = 0 dB, GER = 0 dB
GR = –12 dB, GER = 0 dB
Note:
*Measured with the high pass filter and auto-zero enabled in MMR2.
70
Am79C30A/32A Data Sheet
Table 54.
Codec Performance Specifications (Am79C30A only)
Parameter
Parameter Descriptions
Symbol
Test Conditions
Preliminary
Min
Max
Unit
Transmit absolute gain
0 dBm0; 1020 Hz; VCC = 5 V ±5%, TA
= 0°C–70°C; over all GA
–0.50
+0.50
dB
RXGE
Receive absolute gain at EAR1/EAR2
(nominal)
0 dBm0; 1020 Hz; VCC = 5 V ±5%; TA
= 0°C–70°C; Rload = 540 ohms
–0.50
+0.50
dB
RXGL
Receive absolute gain
0 dBm0; 1020 Hz; VCC = 5 V ±5%; TA =
0°C–70°C; Rload = 40 ohms
–0.80
+0.80
dB
TXSTD
Transmit signal/total distortion; CCITT method
2, 1020 Hz (Tx gain = 0)
–10 dBm0
–45 dBm0
35
24
dB
RXSTD
Receive signal/total distortion; CITT method 2, –10 dBm0
1020 Hz (Rx gain = 0)
–45 dBm0
35
24
dB
TXG
TXGT
Transmit gain tracking; CCITT method 2, 1020 –45
Hz (Tx gain = 0)
–0.60
+0.60
dB
RXGT
Receive gain tracking; CCITT method 2, 1020
Hz (Rx gain = 0)
–0.60
+0.60
dB
TXICN
Transmit Idle channel Noise AINA connected to GX = 6 dB, GA = 18 dB
AREF
–66
dB
–75
dB
RXICN
Receive Idle channel Noise
Notes:
The following test conditions apply to all MAP tests:
–45
GR = –12 dB, GER = 0 dB
1. An external 1-Kohm ± 5% resistor and 2200-pF ±10% capacitor are connected in series between the CAP1 and CAP2 pins
for all transmit tests.
2. All tests are half-channel with the sidetone path enabled but programmed for infinite attentuation (STG = 9008 hex).
3. Transmit specs are guaranteed for both AINA and AINB inputs with the auto-zero and high-pass filters enabled in MMR2.
4. Transmit specs are tested and guaranteed with the input signal source referenced to AREF; see test circuit below.
5. Receive specs are guaranteed for both EAR1/EAR2 and LS1/LS2 outputs measured differentially. Some degradation in
performance may occur if used single ended rather than differential.
Transmitter 0-dB Reference Point:
Nominal input voltage at AINA or AINB will produce a 0-dBm, 1-kHz digital code at the transmit output with all transmit gains at
0 dB.
A law = 625 mV rms
µ law = 620 mV rms
Receiver 0-dB Reference Point:
Nominal input voltage between EAR1/EAR2 or LS1/LS2 resulting from a 0-dBm, 1-kHz digital code at the receive input with all
receive gains at 0 dB.
A law = 1.25 mV rms
µ law = 1.2 mV rms
0.1 µF
AINA or AINB
~
100K
AREF
Transmit Test Circuit with Input Source Referenced to AREF
Am79C30A/32A Data Sheet
71
34 dB
9 dB
Attenuation (dB)
0.9
0.25
0
Frequency (Hz)
Figure 17.
3900
3600
3400
3000
1020
300
60
50
–0.25
09893H-13
Attenuation/Frequency Distortion (Transmit)
Group Delay (µs)
750
380
130
500
600
1000
2600 2800
Frequency (Hz)
Figure 18.
72
Group Delay Variation with Frequency (Transmit)
Am79C30A/32A Data Sheet
09893H-14
1.6
0.6
Gain Variation (dB)
0.3
–55 –50
–40
–10
+3
–0.3
–0.6
Input Level (dBm0)
–1.6
09893H-15
Figure 19.
Gain Tracking Error (Transmit) (CCITT Method 2 at 1020 Hz)
Am79C30A/32A Data Sheet
73
35
Signal-to-Total Distortion Ratio (dB)
29
24
0
–45
–40
–30
–10
0
09893H-16
Input Level (dBm0)
Figure 20.
Signal-to-Total Distortion Ratio (Transmit) (CCITT Method 2 at 1020 Hz)
9 dB
Attenuation (dB)
0.9
0.25
0
–0.25
300
1020
3000 3400 3600 3900
Frequency (Hz)
Figure 21.
74
Attenuation/Frequency Distortion (Receive)
Am79C30A/32A Data Sheet
09893H-17
Group Delay (µs)
750
380
130
500
600
1000
2600 2800
09893H-16
Frequency (Hz)
Figure 22.
Group Delay Variation with Frequency (Receive)
1.6
0.6
Gain Variation (db)
0.3
–55
–50
–40
–10
+3
–0.3
–0.6
Input Level (dBm0)
–1.6
09893H-17
Figure 23.
Gain Tracking Error (Receive) (CCITT Method 2 at 1020 Hz)
Am79C30A/32A Data Sheet
75
35
Signal-to-Total Distortion Ratio (dB)
29
24
0
–45
–40
–30
–10
0
Input Level (dBm0)
Figure 24.
76
Signal-to-Total-Distortion Ratio (Receive) (CCITT Method 2 at 1020 Hz)
Am79C30A/32A Data Sheet
09893H-18
LIU Characteristics
All of the parameters below are measured at the chip terminals and are consistent with 2:1 transformers.
Preliminary
Parameter
Symbol Parameter Descriptions
VLOUT
Output mark amplitude measured between LOUT2 and LOUT1 (Note 1)
Unit
Min
Typ
Max
2.210
2.326
2.442
V
1800
mV
VLIN
Receivable input level measured between LIN2 and LIN1, with noise added as
specified by CCITT I.430 section 8.6.2.1 (Note 2)
ZOUT
Output impedence measured between LOUT2 and LOUT1 spacing condition
20
Kohm
Input impedence measured between LIN2 and LIN1
20
Kohm
Timing extraction jitter on LOUT
–7
+7
ZIN
J
530
%
PD
Total phase deviation (LOUT with respect to LIN)
–7
+15
%
PU
Pulse unbalanced measured between LOUT2 and LOUT1 (Note 1)
–5
+5
%
PW
Output pulse width measured between LOUT2 and LOUT1 (Note 1)
4.7
5.7
µs
5.2
Notes:
1. See the equivalent test load circuit and pulse template in Figures 26 and 27.
2. The 530-mV receive input level is equivalent to 9.0 dB of attenuation from a nominal transmit level when measured at the
LIN pins. Allowing 0.5-dB loss in the isolation transformer, and 1.0-dB loss in the input isolation resistors, this level will
guarantee compliance to the CCITT receiver sensitivity spec of 7.5 dB when measured at the S reference point.
3. Typical receiver performance is 220 mV.
Am79C30A/32A Data Sheet
77
R2
2:1
+
LOUT2
+
VLOUT
LOUT1
RL
CL
V (s-reference)
RL
CL
V (s-reference)
–
R1
2:1
R3
LIN1
LIN2
R4
09893H-19
Notes:
1. V(s-interface): Transmitter output at the S-interface reference point.
2. RL is the termination impedence at the S interface.
3. CL is the effective capacitance at the S interface.
4. R1 and R2 are the transmitter output series resistors; their value depends upon the characteristics of the pulse transformer
(see Figure 28).
5. R3 and R 4 are required for multipoint operation to prevent loading of the line when power is removed from the terminal.
Figure 25.
System Interface to LIU
High Mark
VLOUT
50 ohms
LOUT2 +
RL
VLOUT
CL = 200 pF
a
b
200 ohms
LOUT1 –
c
50%
50%
PW
50 ohms
Low Mark
09893H-19
PU
b
High Mark
a
c
Low Mark
b
09893H-20
Figure 26.
78
Equivalent Test Load
Conditions
Figure 27. Differential Output Signals
Between LOUT2 and LOUT1 (Using the
Test Circuit in Figure 24)
Am79C30A/32A Data Sheet
ILOUT
R2
LOUT2
RSEC
RPRIM • N2
RCORD • N2
+
RL • N 2
VLOUT
LOUT1
–
R1
09893H-20
Notes:
1. RSEC is the DC impedance of the transformer secondary (IC side of transformer).
2. RPRIM is the DC impedance of the transformer primary (line side of transformer).
3. RCORD is the DC impedance of the TE connecting cord; typically 4–6 ohms.
4. N is the transformer turns ratio (N = 2 for Am79C30A/32A).
5. RL is the S-interface line impedance (50 ohms).
6. ILOUT is the desired load current for the CCITT transmission templates (7.5 mA for 50-ohm line).
7. VLOUT is the nominal output voltage from the DSC/IDC line driver.
Figure 28.
Equivalent DC Circuit at LOUT Pins for Calculation of R1 and R2
Series Resistor Calculations
Equation 1
V LOU T
I LOUT = -------------------------------------------------------------------------------------------------------------------------------------------------------------2
2
2
R 1 + R 2 + R SEC + ( R PRIM • N ) + ( R L • N ) + ( R CORD • N )
Equation 2
( V LOU T )
2
2
2
R 1 + R 2 = ---------------------- – R SEC – ( R PRI M • N ) – ( R L • N ) – ( R CORD • N )
( I LOUT )
Equation 3
Let R1 = R 2
Equation 4
2
2
2
1 V LOUT
R 1 + R 2 = --- ----------------- – R SEC – ( R PRIM • N ) – ( R L • N ) – ( R COR D • N )
2 ILOUT
Notes:
N=2
RL = 50 ohms
VLOUT = 2.326 V
ILOUT = 7.5 mA
Equation 5
1
R 1 = R 2 = 55.067 + --- { R SEC + ( 4 • R PRI M ) + ( 4 • R COR D ) }
2
Equation 5 should be used to determine the value of R1 and R 2 for the particular transformer used by each customer.
Am79C30A/32A Data Sheet
79
Microprocessor Read/Write Timing
Microprocessor Read Timing
Parameter Symbol
Parameter Description
Min
tRLRH
RD Pulse Width
200
Max
Units
ns
tRHRL
Read Recovery Time (Notes 1, 2)
200
ns
tAVRL
Address Valid to RD Low
20
ns
tAHRH
Address Hold After RD High
10
ns
tRHCH
RD High to CS High (Note 7)
0
ns
tRACC
Read Access Time (Note 3)
80
ns
tRHDZ
RD High to Data Hi-Z
50
ns
tRDCS
RD Low to CS Low (Note 4)
30
ns
Max
Units
Microprocessor Write Timing
Parameter Symbol
Parameter Description
Min
tWLWH
WR Pulse Width
200
ns
tWHWL
Write Recovery Time (Note 1)
200
ns
tAVWL
Address Valid to WR Low
20
ns
tAHWH
Address Hold After WR High (Note 8)
10
ns
tWHCH
WR High to CS High (Note 7)
0
ns
tDSWH
Data Setup to WR High
100
ns
tDHWH
Data Hold After WR High
10
ns
tWRCS
WR Low to CS Low (Note 4)
30
ns
Notes:
1. The read/write recovery time of 200 ns holds in all cases except when a write command register operation is followed by a
read data register operation when accessing the MAP coefficient RAM. This operation requires a minimum recovery time of
450 ns.
2. Successive reads of the D-Channel Receive Buffer require a minimum cycle time (t RLRH + tRHRL) of 480 ns.
3. Read access time is measured from the falling edge of CS or the falling edge of RD, whichever occurs last.
4. CS may go Low before either RD or WR goes Low.
5. In minimal systems, CS may be tied Low.
6. Read and write indirect register operations cannot be mixed without at least one write command register operation between
them.
7. CS may go High before either RD or WR goes High.
8. If CS goes High before WR goes High, the minimum Address Hold time becomes 12 ns.
9. RD and WR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where both
CS and RD or WR are Low simultaneously.
80
Am79C30A/32A Data Sheet
ADDR
tAVRL
tAHWH
tAVWL
tAHRH
tRDCS
tWRCS
CS
tWHCH
tRHCH
tRLRH
RD/WR
tWLWH
tFHFL
Read
tRACC
tWHWL
Write
Read
tDSWH
tRHDZ
Write
tDHWH
DATA
09893H-21
Figure 29.
Microprocessor Read/Write Timing
Interrupt Timing
Parameter Symbol
Parameter Description
Min
Max
Units
tINTC
INT Cycle Time
125
ms
tREC
INT Recovery Time
500
ns
tINTC
INT
tREC
Figure 30. INT Timing
Am79C30A/32A Data Sheet
09893H-22
81
Reset and Hookswitch Timing
Reset Timing
Parameter Symbol
Parameter Description
tRES
Reset Pulse Width
Min
1
Max
Units
µs
tPHRL
Power Stable to Reset Low
1
µs
tF
Reset Transition Fall Time
1
ms
tR
Reset Transition Rise Time
20
µs
Hookswitch Timing
Parameter Symbol
Parameter Description
Min
Max
Units
tB
Debounce Time
16
16.25
ms
t1
HSW Detected to INT Delay
0
370
µs
Note:
Due to clock start-up times, the hookswitch Min and Max Debounce times are approximately 3 ms greater in Power-Down Mode.
4.75 V
VCC
tPHRL
VIH
VIL
RESET
tRES
tR
Figure 31.
tF
09893H-23
Reset Timing
HSW
tB
t1
INT
09893H-24
Figure 32.
82
Hookswitch Debounce Timing
Am79C30A/32A Data Sheet
OSC (XTAL2) Timing
Parameter Symbol
Parameter Description
Test Conditions
Min
Max
Units
tCLCL
Oscillator Period
81.374
81.387
ns
tCH
High Time
33
ns
tCL
Low Time
33
ns
tCLCH
Rise Time
10
ns
tCHCL
Fall Time
10
ns
Max
Units
Note:
Frequency = 12.288 MHz ±80 ppm.
MCLK Timing
Parameter Symbol
Parameter Description
Test Conditions
tD
XTAL2 VCC/2 to
MCLK VCC/2
MCLK Load < 80pF
60
ns
tRISE1
Rise Time
MCLK Load < 80pF
0.5 V to (VCC–0.5V)
15
ns
tRISE2
Rise Time
MCLK Load < 40pF
1.0 V to 3.5 V
5
ns
tFALL1
Fall Time
MCLK Load < 80pF
(VCC–0.5V) to 0.5 V
15
ns
tFALL2
Fall Time
MCLK Load < 40pF
3.5 V to 1.0 V
5
ns
tPWH
tPWL
High Pulse Width
12.288 MHz
6.144 MHz
4.069 MHz
3.072 MHz
1.536 MHz
768 kHz
384 kHz
Low Pulse Width
12.288 MHz
6.144 MHz
4.096 MHz
3.072 MHz
1.536 MHz
768 kHz
384 kHz
MCLK Load < 80pF
33
73
114
155
317
643
1.294
ns
ns
ns
ns
ns
ns
µs
MCLK Load < 80pF
33
73
114
155
317
1.294
ns
ns
ns
ns
ns
µs
tCLCH
tCH
Min
tCHCL
VCC – 0.5 V*
0.5 V
tCL
Note:
*Not TTL VIH
tCLCL
09893H-25
Figure 33.
External Clock Driver (XTAL2) Timing
Am79C30A/32A Data Sheet
83
tD
VCC /2
OSC
VCC /2
Divide by 1
12.288 MHz
Divide by 2
6.144 MHz
Divide by 3
4.096 MHz
tRISE 1,2
tFALL 1,2
Divide by 4
3.072 MHz
tPWL
tPWH
tCLK
Figure 34.
09893H-26
OSC/MCLK Timing
SBP Mode Timing
Parameter Symbol
Parameter Description
Tp*
SCLK
Test Conditions
Min
Max
Units
5.025
5.392
µs
Ta
High time
2.594
2.615
µs
Tb*
Low time
2.431
2.777
µs
tRISE
SCLK rise time
SCLK Load < 80 pF
20
ns
tFALL
SCLK fall time
SCLK Load < 80 pF
20
ns
tMCSC
MCLK to SCLK
@ 6.144 MHz
MCLK Load < 80 pF
60
ns
50
250
ns
50
250
ns
200
ns
SCLK Load < 80 pF
tCHFS
SCLK High to frame sync
tCLDO
SBOUT
SBOUT/SFS
Data available
Load = 80 pF
tDICH
SBIN set-up time
tCHDZ
SBIN hold time
0
ns
Note:
*The frequency of SCLK is fXTAL2 / 64. Tp and Tb are based on this SCLK frequency but include a ±163-ns allowance for
internal-phase lock-loop correction.
84
Am79C30A/32A Data Sheet
Ta
Tb
Tp
SCLK
SBIN or SBOUT
Bd
Be
Bf
SFS
T1
BCL/CH2STRB
T1
09893H-27
Notes:
1. For PPCR2(0) = 0, SBIN data is sampled on the rising edge of SCLK; SBOUT data is changed on the falling edge of SCLK.
For PPCR2(0) = 1, SBIN data is sampled on the falling edge of SCLK; SBOUT data is changed on the rising edge of SCLK.
2. T1 width is eight SCLK periods.
Figure 35.
SBP Mode Timing
MCLK (6.144 MHz)
tMCSC
SCLK (192 kHz)
tCHFS
tCHFS
*SFS (8 kHz)
tCLDO
tCLDO
SBOUT
tDICH
tCHDZ
SBIN
09893H-28
Notes:
1. CH2STRB timing is identical to SFS timing but delayed by eight SCLK cycles.
2. This timing diagram reflects SCLK for PPCR2(0) = 0. For PPCR2(0) = 1, the diagram is identical except that the SCLK
waveform should be inverted.
Figure 36.
SBP Mode MCLK/SCLK/SFS Timing
Am79C30A/32A Data Sheet
85
IOM-2 Master Mode Timing
Parameter
Signal
Abbr
Test Condition
Data Clock Rise/Fall
SCLK
tR,tF
CL = 150 pF
Clock Period
SCLK
tSCL
1.536 MHz
Min
Max
Units
50
ns
487
815
ns
260
ns
± 100 PPM
±163 ns*
Pulse Width
SCLK
tWH,
tWL
Frame Sync
SFS
tR,tF
CL = 150 pF
Frame Sync Setup/Clock
SFS
tSF
CL = 150 pF
50
ns
Frame Sync Delay/Clock
SFS
tFD
CL = 150 pF
0
ns
Frame Sync Hold/Clock
SFS
tFH
CL = 150 pF
50
–tWL
Frame Delay
SFS
tDF
CL = 150 pF
Data Delay/Clock
SBOUT
tDSC
CL = 150 pF
Data Hold/Clock
SBOUT
tDHC
CL = 150 pF
Data Setup
SBIN
Data Hold
SBIN
50
ns
tWL + 50
ns
50
ns
100
ns
70
ns
tSD
tWH + 20
ns
tHD
50
ns
IOM-2 Slave Mode Timing
Parameter
Signal
Abbr
Data Clock Rise/Fall
SCLK
tR,tF
Clock Frequency (1/period)
SCLK
1/tSCLK
Clock Delay High/Low
BCL
tBLH, tBHL
Min
Max
Units
60
ns
Hz
1.536 MHz
±100 PPM
±163 ns*
30
ns
60
ns
Pulse Width
SCLK
tWH, tWL
Frame Sync Rise/Fall
SFS
tR,tF
Frame Set-up
SFS
tSF
70
ns
Frame Hold/Clock
SFS
tFH
20
ns
Frame Delay/Clock
SFS
tFD
0
ns
Frame Width High
SFS
tWFH
130
ns
Frame Width Low
SFS
tWFL
tSCLK
ns
Data Delay/Clock
SBOUT
tDSC
Data Hold/Clock
SBOUT
tDHC
Data Set-up
SBIN
Data Hold
SBIN
ns
100**
ns
70
ns
tSD
tWH + 20
ns
tHD
50
ns
Notes:
*The +163-ns value can occur once per frame for digital phase lock loop correction.
**CL = 150 pF
86
240
Am79C30A/32A Data Sheet
BCL
**
SFS
SBOUT
SBIN
Bit 95
Bit 0
Bit 1
Bit 2
Detail A
Note:
** SFS width is 16 SCLK cycles + setup and hold time.
tBLH
tBHL
BCL
tR
SCLK
tF
tWH
tSCU
tWL
tFD
SFS*
tFH*
tSF
tDF
tWFH
tDHC
SBOUT
tDSC
tHD
Transmitter Side
SBIN
Receiver Side
Detail A
tSD
09893H-29
Note:
* In Master Mode, SFS is 16 SCLK cycle + setup time + hold time in length.
Figure 37.
IOM-2 Timing
Am79C30A/32A Data Sheet
87
Switching Test Conditions
(Input)
2.4 V
2.0 V
2.0 V
Test Points
0.8 V
0.45 V
0.8 V
09893H-30
Note:
AC testing inputs are driven at 2.4 V for a logical 1, and 0.45 V for a logical 0. Timing measurements are made at 2.0 V and 0.8
V for a logical 1, and a logical 0, respectively.
Figure 38.
Switching Test Input/Output Waveform
Device
Under
Test
CL = 80 pF
CL Includes Jig Capacitance
09893H-31
Figure 39.
88
Switching Test Load Circuit
Am79C30A/32A Data Sheet
APPENDIX A
Table 1.
Hex
Gain
Coefficients for GX, GR, and STG Attenuators
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
–84.3
87
87
–53.0
90
E6
–36.0
90
D6
–78.3
86
87
–41.9
90
E5
–35.9
90
D5
–72.2
8F
8D
–41.8
8F
53
–35.8
8E
52
–66.2
84
87
–41.7
8F
51
–35.7
8E
4B
–60.2
8F
8B
–41.6
90
E4
–35.6
90
D4
–54.2
91
0F
–41.5
8F
42
–35.5
8E
42
–50.7
8F
92
–41.4
8F
41
–35.3
8E
41
–49.3
90
FB
–41.2
8F
3D
–35.2
8E
3C
–48.7
90
FC
–41.1
90
E3
–35.1
90
D3
–48.4
90
FD
–41.0
8F
33
–35.0
8E
33
–48.3
90
FE
–40.9
8F
32
–34.9
8E
32
–48.2
8E
91
–40.7
8F
31
–34.6
8E
31
–48.1
90
F7
–40.4
8F
2B
–34.4
8E
2B
–48.0
90
F6
–40.3
8F
2D
–34.3
8E
2C
–47.9
90
F5
–40.2
90
E2
–34.2
90
D2
–47.6
90
F4
–40.1
8F
24
–34.1
8E
24
–47.1
90
F3
–40.0
8F
23
–34.0
8E
23
–46.2
90
F2
–39.8
8F
22
–33.8
8E
22
–45.4
8F
A2
–39.4
8E
A2
–33.4
8D
A2
–45.0
8F
A3
–39.0
8E
A3
–33.0
8D
A3
–44.8
8F
A4
–38.8
8E
A4
–32.8
8D
A4
–44.7
8F
A5
–38.7
8E
A5
–32.7
8D
A5
–44.6
90
F1
–38.6
8D
92
–32.6
8D
A6
–44.5
8F
AC
–38.5
8F
15
–32.5
8E
15
–44.3
8F
AB
–38.4
8E
AC
–32.4
8E
14
–43.9
8F
B1
–38.3
8F
13
–32.2
8E
13
–43.6
8F
B2
–37.9
8E
B1
–31.9
8D
B1
–43.5
8F
B3
–37.6
8E
B2
–31.6
8D
B2
–43.4
8F
B4
–37.4
8E
B3
–31.4
8D
B3
–43.3
90
EB
–37.3
8E
B5
–31.3
8D
B4
–43.2
8F
BB
–37.2
8E
BC
–31.2
8D
BC
–43.0
8F
C1
–37.1
8E
BB
–31.1
8D
BB
–42.9
8F
C2
–37.0
8E
C1
–31.0
8D
C1
–42.8
8F
C3
–36.8
8E
C2
–30.8
8D
C2
–42.7
90
EC
–36.7
90
DC
–30.7
8D
C3
–42.6
8F
D1
–36.6
8E
CB
–30.6
8D
CB
–42.5
8F
D2
–36.5
8E
D1
–30.5
8D
D1
–42.4
90
ED
36.4
90
DD
30.4
8D
D2
–42.3
8E
96
–36.3
8E
E2
–30.3
8D
E1
–42.2
8F
F1
–36.2
8E
F1
–30.2
8C
96
–42.1
8D
91
–36.1
8C
91
–30.1
91
0B
–30.0
90
C7
–24.1
8A
91
–18.3
91
15
Am79C30A/32A Data Sheet
89
Table 1.
Hex
Gain
90
Coefficients for GX, GR, and STG Attenuators (Continued)
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
–29.9
8D
5C
–24.0
90
B7
–18.2
8B
E2
–29.8
90
C5
–23.9
90
B6
–18.1
8A
97
–29.7
8D
4A
–23.8
90
B5
–18.0
91
1F
–29.6
90
C4
–23.7
8C
4A
–17.9
91
1E
–29.5
8D
43
–23.6
90
B4
–17.8
91
1D
–29.4
8D
42
–23.5
8C
43
–17.7
8B
4A
–29.3
8D
3A
–23.4
8C
42
–17.6
8B
4D
–29.2
8D
3B
–23.3
8C
3A
–17.5
90
A4
–29.1
90
C3
–23.2
8C
3B
–17.4
8B
42
–29.0
8D
33
–23.1
90
B3
–17.3
8B
41
–28.8
8D
32
–23.0
8C
34
–17.2
8B
3B
–28.6
8D
2A
–22.9
8C
33
–17.1
8B
3D
–28.4
8D
2B
–22.8
8C
32
–17.0
90
A3
–28.3
8D
2C
–22.6
8C
31
–16.9
8B
33
–28.2
8C
A1
–22.4
8C
2B
–16.8
8B
32
–28.1
8D
24
–22.3
8C
2C
–16.6
8B
2A
–28.0
8D
23
–22.2
8C
2E
–16.3
8B
2B
–27.7
8D
22
–22.1
90
B2
–16.2
8B
2E
–27.3
8C
A2
–22.0
8C
24
–16.1
8A
A1
–27.0
8C
A3
–21.9
8C
23
–16.0
8B
24
–26.8
8C
A4
–21.7
8C
22
–15.9
8B
23
–26.7
8C
A5
–21.3
8B
A2
–15.7
8B
22
–26.6
8C
A6
–20.9
8B
A3
–15.3
91
22
–26.5
8D
15
–20.7
8B
A4
–14.9
91
23
–26.4
8C
AC
–20.6
8B
A6
–14.7
8A
A4
–26.2
8D
13
–20.5
8C
15
–14.6
8A
A5
–25.9
8C
B1
–20.4
8B
AC
–14.5
89
92
–25.6
8C
B2
–20.2
8C
13
–14.4
91
2D
–25.4
8C
B3
–19.9
8B
B1
–14.2
91
2B
–25.3
8C
B4
–19.5
8B
B2
–13.8
8A
B1
–25.2
8B
93
–19.4
8B
B3
–13.5
8A
B2
–25.1
8C
BB
–19.3
8B
B4
–13.4
91
33
–24.9
8C
C1
–19.2
8A
93
–13.3
91
34
–24.8
8C
C2
–19.1
8B
BB
–13.2
91
35
–24.7
8C
C3
–18.9
8B
C1
–13.1
91
3C
–24.6
90
BC
–18.8
8B
C2
–13.0
91
3B
–24.5
8C
D1
–18.7
8B
C3
–12.9
91
41
–24.4
8C
D2
–18.6
91
14
–12.7
8A
C2
–24.3
8C
E1
–18.5
8B
D1
–12.6
91
44
–24.2
90
BE
–18.4
8B
D2
–12.5
91
4B
–12.4
8A
D2
–7.7
92
A3
–3.6
9A
22
–12.3
A0
05
–7.6
93
22
–3.5
9A
1A
–12.2
91
61
–7.5
93
23
–3.4
9A
1B
Am79C30A/32A Data Sheet
Table 1.
Coefficients for GX, GR, and STG Attenuators (Continued)
Hex
Gain
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
–12.1
8A
F1
–7.4
93
2A
–3.3
A2
67
–12.0
08
11
–7.3
89
B3
–3.2
A2
E7
–11.9
90
96
–7.2
93
E7
–3.1
9A
12
–11.8
91
DA
–7.1
A0
2D
–3.0
A3
1C
–11.7
91
D3
–7.0
A0
2B
–2.9
A3
57
–11.6
91
D1
–6.9
94
13
–2.8
99
BA
–11.5
90
94
–6.8
93
A3
–2.7
A4
FC
–11.4
91
C2
–6.7
A0
32
–2.6
A5
FB
–11.3
91
C1
–6.6
94
D7
–2.5
AF
A7
–11.1
91
BB
–6.5
93
94
–2.4
AE
3F
–11.0
A0
0B
–6.4
89
D1
–2.3
AC
5F
–10.9
91
B3
–6.3
95
C7
–2.2
99
3C
–10.8
91
B2
–6.2
96
D5
–2.1
AB
F6
–10.5
92
12
–6.1
97
A7
–2.0
99
2A
–10.3
91
AB
–6.0
9F
54
–1.9
99
2B
–10.2
92
14
–5.9
9F
27
–1.8
AA
7F
–10.1
89
A1
–5.8
9D
74
–1.7
AA
2B
–10.0
92
1D
–5.7
9D
47
–1.6
AA
21
–9.9
92
1B
–5.6
89
4B
–1.5
B2
FE
–9.7
91
A2
–5.5
9C
FD
–1.4
A9
AA
–9.5
92
22
–5.4
9D
01
–1.3
B3
57
–9.4
92
23
–5.3
9C
1B
–1.2
BF
6B
–9.3
92
24
–5.2
9C
12
–1.1
BE
B7
–9.2
92
2C
–5.1
89
3C
–1.0
BB
6F
–9.1
92
2A
–5.0
9B
67
–0.9
C1
FF
–9.0
92
32
–4.9
89
33
–0.8
BB
01
–8.9
92
33
–4.8
9C
01
–0.7
C2
FE
–8.8
92
3B
–4.7
9B
22
–0.6
CE
3F
–8.7
92
42
–4.6
9B
1C
–0.5
CD
C7
–8.6
A0
15
–4.5
9B
13
–0.4
CA
7F
–8.5
92
F7
–4.4
9B
12
–0.3
DC
D7
–8.4
91
95
–4.3
89
2B
–0.2
DB
6F
–8.3
A0
1C
–4.2
9B
0B
–0.1
EB
E7
–8.2
92
BB
–4.1
9A
77
0.0
00
80
–8.1
92
B4
–4.0
89
24
0.1
6A
F7
–8.0
93
12
–3.9
9B
02
0.2
5B
E7
–7.9
93
13
–3.8
9A
2A
0.3
5C
5F
–7.8
A0
21
–3.7
89
22
0.4
4A
7F
0.5
4C
D7
4.6
12
12
8.7
01
1C
0.6
43
57
4.7
11
C1
8.8
01
14
0.7
42
FE
4.8
10
96
8.9
00
AB
0.8
41
FF
4.9
20
04
9.0
00
AA
0.9
3B
6F
5.0
09
93
9.1
00
B2
Am79C30A/32A Data Sheet
91
Table 1.
Coefficients for GX, GR, and STG Attenuators (Continued)
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
1.0
3D
C7
5.1
11
2C
9.2
00
BB
1.1
33
57
5.2
11
22
9.3
00
BA
1.2
29
AA
5.3
0A
A1
9.4
00
CA
1.3
32
FE
5.4
10
A5
9.5
00
08
1.4
2B
01
5.5
0A
93
9.6
00
69
1.5
2A
7F
5.6
0B
A2
9.7
00
4A
1.6
19
2A
5.7
0A
91
9.8
00
3A
1.7
2B
F6
5.8
0C
A1
9.9
00
3B
1.8
2C
5F
5.9
0D
A1
10.0
00
32
1.9
2E
B7
6.0
00
90
10.1
00
2A
2.0
24
FC
6.1
05
91
10.2
00
2B
2.1
23
D7
6.2
10
4F
10.3
00
23
2.2
23
57
6.3
04
B7
10.4
00
22
2.3
1A
12
6.4
03
A1
10.6
00
1A
2.4
22
67
6.5
03
B1
10.7
00
1B
2.5
1A
1A
6.6
03
77
10.8
00
1C
2.6
09
22
6.7
02
A1
10.9
00
15
2.7
1B
02
6.8
01
92
11.0
00
13
2.8
1A
77
6.9
02
B1
11.2
00
12
2.9
09
2B
7.0
02
C1
11.5
00
11
3.0
1C
00
7.1
02
41
11.8
00
0B
3.1
1B
67
7.2
02
31
11.9
00
10
3.2
1B
E7
7.3
01
A1
12.0
00
10
3.3
1C
FD
7.4
01
A2
12.1
00
05
3.4
1D
47
7.5
01
A3
12.2
00
04
3.5
17
A7
7.6
01
B1
12.3
00
03
3.6
16
B7
7.7
01
B2
12.6
00
2
3.7
14
F5
7.8
01
C1
13.1
00
01
3.8
20
2B
7.9
01
D1
14.0
00
00
3.9
13
E7
8.0
01
51
4.0
20
21
8.1
01
3B
–inf.
08
10
4.1
11
93
8.2
01
32
4.2
12
F7
8.3
01
2B
4.3
12
2A
8.4
01
23
4.4
12
22
8.5
01
22
4.5
09
A1
8.6
01
1A
Table 2.
Hex
Gain
92
Hex
Gain
Coefficients for GER Attenuators
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
–24.1
99
99
–11.4
47
99
–6.8
7D
C9
–20.6
A9
99
–11.3
DA
A9
–6.7
9E
C7
–19.2
99
9B
–11.2
99
54
–6.6
6E
C9
Am79C30A/32A Data Sheet
Table 2.
Hex
Gain
Coefficients for GER Attenuators (Continued)
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
–18.6
C9
99
–11.1
FA
A9
–6.5
69
CF
–18.3
D9
99
–11.0
A9
91
–6.4
5F
C9
–18.2
E9
99
–10.9
36
99
–6.3
66
9C
–18.1
99
9F
–10.8
9A
BB
–6.2
59
DE
–18.0
99
97
–10.7
C9
92
–6.1
59
DF
–17.9
99
96
–10.5
34
99
–6.0
57
9D
–17.8
99
95
–10.4
D9
92
–5.9
56
9D
–17.5
49
99
–10.2
E9
92
–5.8
49
DF
–17.0
39
99
–10.0
99
72
–5.7
D9
74
–16.1
29
99
–9.8
25
99
–5.6
55
9E
–15.7
BA
99
–9.7
FB
A9
–5.5
E9
64
–15.1
99
AC
–9.6
79
AB
–5.4
55
69
–14.8
DA
99
–9.5
69
AB
–5.3
F9
54
–14.7
99
AE
–9.4
BA
95
–5.2
66
49
–14.6
99
AF
–9.2
9A
CE
–5.1
E9
73
–14.5
19
99
–9.1
9A
CF
–5.0
37
9F
–14.4
A9
96
–9.0
CA
97
–4.9
36
9F
–14.3
59
9A
–8.9
ED
A9
–4.8
36
79
–14.0
A9
94
–8.8
19
9D
–4.7
A5
A7
–13.8
99
BC
–8.7
DA
97
–4.6
92
C7
–13.5
39
9A
–8.6
F9
91
–4.5
AA
55
–13.3
EB
99
–8.5
79
AF
–4.4
92
C5
–13.2
99
CC
–8.4
77
9A
–4.3
D3
93
–13.1
79
9B
–8.3
FA
95
–4.2
2F
F9
–12.9
B9
95
–8.2
BB
96
–4.1
27
9F
–12.7
99
CE
–8.1
49
AE
–4.0
91
A3
–12.6
DD
99
–8.0
9B
CE
–3.9
77
29
–12.5
C9
97
–7.9
A9
74
–3.8
D4
92
–12.4
99
DF
–7.8
FC
B9
–3.7
7A
BE
–12.3
EE
99
–7.7
29
AB
–3.6
6F
BA
–12.2
FE
99
–7.6
EA
AA
–3.5
A7
B7
–12.1
79
9E
–7.5
FD
B9
–3.4
66
AB
–12.0
09
99
–7.4
37
9A
–3.3
7A
CD
–11.9
59
9E
–7.3
39
BB
–3.2
6D
CA
–11.8
59
9F
–7.2
79
BE
–3.1
6E
CA
–11.7
57
99
–7.1
6F
B9
–3.0
A3
A3
–11.6
99
65
–7.0
B9
76
–2.9
5F
CA
–11.5
55
99
–6.9
DB
94
–2.8
7B
BC
–2.7
56
AC
1.4
EC
62
5.5
CF
06
–2.6
5A
DE
1.5
34
7F
5.6
BB
02
–2.5
7B
BD
1.6
C2
F5
5.7
BE
03
–2.4
66
AE
1.7
FD
33
5.8
CE
04
–2.3
4A
DF
1.8
D2
E5
5.9
DF
05
Am79C30A/32A Data Sheet
93
Table 2.
Hex
Gain
94
Coefficients for GER Attenuators (Continued)
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
–2.2
4A
EE
1.9
FE
62
6.0
EE
05
–2.1
5B
BF
2.0
E2
F5
6.1
09
70
–2.0
47
AF
2.1
D2
F4
6.2
96
00
–1.9
6D
CB
2.2
E2
E4
6.3
09
50
–1.8
65
5A
2.3
F2
F4
6.4
FC
03
–1.7
6B
CE
2.4
24
7E
6.5
AC
01
–1.6
6B
DD
2.5
24
6F
6.6
DE
03
–1.5
5B
CF
2.6
D2
F3
6.7
BE
02
–1.4
5B
DD
2.7
E2
E3
6.8
AD
01
–1.3
6C
CD
2.8
C1
D7
6.9
AE
01
–1.2
B7
D6
2.9
C1
E7
7.0
FA
01
–1.1
67
BE
3.0
FC
71
7.1
CD
02
–1.0
66
BF
3.1
D1
D6
7.2
BB
01
–0.9
4E
EB
3.2
C1
F5
7.3
CE
02
–0.8
5D
DC
3.3
FD
61
7.4
DD
02
–0.7
5C
DE
3.4
D1
E5
7.5
DE
02
–0.6
5D
DD
3.5
16
6D
7.6
FD
02
–0.5
A1
A3
3.6
E1
F5
7.7
EE
02
–0.4
5D
DE
3.7
E2
F2
7.8
EF
02
–0.3
4E
EC
3.8
EE
41
7.9
E7
20
–0.2
EA
42
3.9
15
6F
8.0
F6
20
–0.1
90
E7
4.0
17
4F
8.1
E5
20
0.0
67
EF
4.1
16
4F
8.2
D4
20
0.1
90
F6
4.2
BB
04
8.3
20
E4
0.2
90
F5
4.3
E1
F3
8.4
F4
20
0.3
55
EE
4.4
FF
31
8.5
10
B6
0.4
D4
E5
4.5
09
13
8.6
B5
10
0.5
90
C3
4.6
BC
05
8.7
20
B2
0.6
ED
44
4.7
DB
06
8.8
E3
20
0.7
D4
F4
4.8
CB
04
8.9
11
F2
0.8
EE
44
4.9
FB
06
9.0
C7
10
0.9
D3
E5
5.0
CC
06
9.1
10
C6
1.0
E3
F6
5.1
BD
04
9.2
C5
10
1.1
D3
E4
5.2
AD
02
9.3
20
C2
1.2
D3
F4
5.3
AE
02
9.4
D6
10
1.3
EE
43
5.4
CC
04
9.5
10
90
9.6
10
F6
13.8
E0
20
15.6
0A
00
9.7
E5
10
13.9
E0
20
15.7
61
00
9.8
E2
20
12.2
00
E5
15.8
50
10
9.9
10
E4
12.3
00
D4
15.9
22
00
10.0
10
C3
12.4
00
E4
16.1
40
10
10.1
40
A0
12.5
00
C3
16.6
30
10
10.2
46
10
12.6
47
00
16.9
B0
00
Am79C30A/32A Data Sheet
Table 2.
Hex
Gain
Coefficients for GER Attenuators (Continued)
Hex
Gain
Hex
Gain
(dB)
MSB
LSB
(dB)
MSB
LSB
(dB)
MSB
LSB
10.3
10
D3
12.7
46
00
16.6
30
10
10.4
10
E3
12.8
00
B2
16.9
B0
00
10.5
10
F3
12.9
00
E3
17.5
02
10
10.6
10
A1
13.0
F3
00
17.8
D0
00
10.7
BE
00
13.1
00
A1
17.9
E0
00
10.8
BF
00
13.2
16
10
18.0
F0
00
10.9
B7
00
13.3
15
10
18.1
70
00
11.0
00
B6
13.4
22
10
18.2
60
00
11.1
00
B5
13.6
14
10
18.3
50
00
11.2
01
D2
13.7
D0
20
18.6
40
00
11.3
01
E2
14.0
72
00
19.1
10
10
11.4
F2
01
14.1
13
10
20.0
02
00
11.5
00
C7
14.2
52
00
21.6
00
10
11.6
00
C6
14.4
1B
00
24.1
00
00
11.7
00
C5
14.5
42
00
11.8
D7
00
15.0
0C
01
–inf.
00
08
11.9
00
B3
15.3
0D
01
12.0
00
90
15.4
0E
01
12.1
F6
00
15.5
0F
01
12.2
00
E5
15.6
0A
00
12.3
00
D4
15.7
61
00
12.4
00
E4
15.8
50
10
12.5
00
C3
15.9
22
00
12.6
47
00
16.1
40
10
Am79C30A/32A Data Sheet
95
APPENDIX B
KEY DESIGN HINTS
FOR THE DSC/IDC CIRCUIT
Due to the high level of integration of the Am79C30A/
32A DSC/IDC circuit, it is easy to overlook important
design information when reading the data sheet. The
following list of key design hints has been compiled to
streamline the design process. A comprehensive series of ISDN application notes and tutorials is available
from AMD; please contact an AMD sales office or factory for current information.
•
•
•
The AREF pint must be used to bias the AINA and
AINB inputs. There is a datasheet parameter, Vios,
which states that the analog inputs must be biased
to within 5 mV of AREF. AREF is nominally 2.4 V;
normal device-to-device variation will exceed the
5-mV Vios specification. If a voltage other than
AREF is used, transmission performance at very
low signal levels will be degraded.
The recommended method of biasing the AINA and
AINB inputs is to use a 15–100 Kohm resistor between the input and AREF. The signal source
should be AC-coupled to the analog input. Take
care that the RC formed by the biasing resistor and
blocking capacitor does not distort the input signal.
The AREF output must not be loaded with a capacitor since it may cause the internal buffer amplifier to
become unstable. For some applications involving
significant gain external to the DSC circuit, the
AREF output may require a simple RC noise filter.
In this case, the AREF output should be isolated
from the capacitor by a resistance of greater than 1
Kohm to ensure stability.
•
The analog gain selection value (in MMR3) should
be written before the MAP is enabled.
•
The MAP auto-zero function (MMR2) should be enabled before the MAP is enabled.
•
The DSC/IDC circuit should be provided with decoupling capacitors, situated as close as possible to
the package power leads. In general, 0.1-µF ceramic capacitors are sufficient, but bulk decoupling
capacitors will be required if the LS1 and LS2 loudspeaker outputs are driving a heavy load.
•
The DSC/IDC circuit is constructed on a single substrate, and therefore the device power pins must not
be from separate supplies. If there is a DC offset between the analog and digital power-supply pins, excessive current may flow through the device
substrate.
•
96
The LS1, LS2, EAR1, and EAR2 outputs are intended to be used differentially. Although it is possible to use only a single output, the rejection of
power-supply noise and internal digital noise is improved if the outputs are used differentially.
•
Observe the maximum loading specification for the
Ls and EAR outputs. When used differentially, the
EAr outputs must see a minimum of 540 ohms between them. Similarly, the LS outputs must see a
minimum of 40 ohms. The maximum capacitive
loading in either case is 100 pF.
•
The LS and EAR outputs need not be matched to
the load. The LS and EAR outputs are voltage drivers and do not assume the presence of any particular load impedance. If the maximum loading
specification is met, the LS and EAR outputs will
function satisfactorily. In some cases, an external
resistor may be used to center the desired output
volume—for instance, while driving a 150-ohm earpiece with the EAR outputs.
•
If using an EAR or LS output in a single-ended fashion, AC-couple the pin to the load. If not, the excessive DC current will cause signal distortion.
•
When using programmable gains and filters in the
MAP, consider the dynamic range effects such as
truncation error and clipping. In case of questions in
any particular application, please contact the AMD
applications staff for assistance.
•
All MAP tone generators are referenced with respect to the +3-dBm0 overload voltage—that is, a
0-dB tone yields a +3-dBm0 output. Take care to
avoid clipping when adding tones to signals as, for
example, when generating DTMF waveforms.
•
The RC connected to CAP1/CAP2 must be situated
as close as possible to the DSC circuit package to
reduce the amount of noise coupled in from other
signal traces.
•
Observe the XTAL2 frequency accuracy requirement of 12.288 MHz ± 80 ppm. Since crystals from
different manufacturers will vary, the DSC circuit oscillator output frequency at the MCLK pin must be
measured and, if necessary, the value of the crystal
load capacitors should be adjusted as part of the initial design procedure. An application note of oscillator considerations is available from AMD (ISDN
Systems Engineering Application Note, order
#12557).
•
If driving the XTAL2 pin with the external oscillator,
it is necessary to observe the datasheet input voltage and rise/fall time requirements. Note that the
XTAL2 levels are not TTL-compatible.
•
Take care in board layout of the DSC circuit, as with
any sensitive analog device. An application note of
DSC circuit board layout hints is available from AMD
(ISDN Systems Engineering Application Note,
order #12557).
Am79C30A/32A Data Sheet
•
The sidetone path defaults to –18-dB attenuation. If
disabling the sidetone path is desired, the sidetone
block must be enabled and programmed for infinite
attentuation.
•
Consider the LIU transformers, series resistors, and
IC LIU output drivers as a functional unit. Transformers that meet CCITT I.430 requirements with other
transceivers are not necessarily appropriate for use
with the DSC circuit, and vice versa.
•
Interrupts should be masked when reading or writing any indirect or multibyte DSC circuit registers to
prevent the possibility of an interrupt occurring and
destroyed the contents of the Command Register.
•
If the MAP and secondary tone ringer are disabled,
the EAR, AREF, and LS outputs are high-impedance. If the MAP is enabled, the unselected audio
output is high-impedance.
•
The MAP should not be enabled until after the LIU
has achieved synchronization. This will eliminate
the possibility of audible distortion when the internal
device timing is resynchronized to the S Interface.
•
To make optimum use of the MAP digital signal processing chain, use digital gain (GX) for fine adjustment, and analog gain (GA) for coarse adjustment.
•
The user must program the Secondary Tone Ringer
Frequency Register (STFR) with a legal value before enabling the secondary tone ringer.
•
In order to exit Power-Down Mode due to LIU activation, both the F7 interrupt and the DSC/IDC circuit interrupt pin must be enabled. In order to exit
Power-Down Mode due to IOM-2 activation, both
the IOM-2 Timing Request interrupt and the
DSC/IDC circuit interrupt pin must be enabled.
•
The MAP auto-zero function must be enabled prior
to enabling the MAP. For all normal applications, the
auto-zero function should always be enabled.
•
To ensure proper operation of the filters (X and R)
and gains (GX, GR, GER, STGR, and ATGR), these
register blocks should not be accessed more frequently than 128-µs intervals. This allows the internal buffers to the map to operate properly, since
they are updated only once per frame.
Am79C30A/32A Data Sheet
97
APPENDIX C
PHYSICAL DIMENSIONS
PL 044
.685
.695
.062
.083
.650
.656
.042
.056
.685
.695
Pin 1 I.D.
.500
REF
.650
.656
.590
.630
.013
.021
.026
.032
.050
REF
.009
.015
TOP VIEW
SEATING PLANE
SIDE VIEW
Note:
Dimensions are measured in inches.
98
.090
.120
.165
.180
Am79C30A/32A Data Sheet
PHYSICAL DIMENSIONS
PQT 44
44
1
11.80
12.20
-A-
-B-
9.80
10.20
-D-
9.80
10.20
11.80
12.20
TOP VIEW
11° – 13°
0.95
1.05
1.00 REF.
1.20 MAX
0.30
0.45
0.80 BSC
11° – 13°
SIDE VIEW
Note:
Dimensions are measured in inches.
Am79C30A/32A Data Sheet
99
© 1998 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make
changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this
publication.
This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any warranty of merchantability
or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without
AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples)
of AMD products, except as provided in AMD’s Terms and Conditions of Sale for such products.
Trademarks
AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc.
AmMAP, Digital Subscriber Controller, DSC, and IDC are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
100
Am79C30A/32A Data Sheet
AMENDMENT
Am79C30A/32A
Digital Subscriber Controller™ (DSC™) Circuit
Table 23: Amplitude Gain Coefficients on page 27 of
the Am79C30A/32A final data sheet has the following
changes:
The tone gain block was intended to provide amplitude
steps of 2 dB with a tolerance of approximately 0.5 dB.
The following additional codes can also be used:
–17 dB = Hex 33
–11 dB = Hex 23
–5 dB = Hex 13
The updated Table 23 reads as follows:
Table 23. Amplitude Gain Coefficients
Gain (dB)
Hex Code
–18
37
–17
33
–16
32
–14
31
–12
27
–11
23
–10
22
–8
21
–6
20
–5
13
–4
12
–2
11
0
10
Publication# 09893 Rev: H Amendment/1
Issue Date: December 1998