Cherry CS2844 Current mode pwm control circuit with 50% max duty cycle Datasheet

Current Mode PWM Control Circuit
with 50% Max Duty Cycle
Description
Features
The CS3844/45 provides all the necessary features to implement off-line
fixed frequency current-mode control
with a minimum number of external
components.
before the output stage is enabled. In
the CS2844/CS3844 turn on occurs at
16V and turn off at 10V. In the
CS2845/CS3845 turn on is at 8.4V and
turn off at 7.6V.
The CS3844 family incorporates a new
precision temperature-controlled oscillator to minimize variations in frequency. An internal toggle flip-flop,
which blanks the output every other
clock cycle, limits the duty-cycle range
to less than 50%. An undervoltage
lockout ensures that VREF is stabilized
Other features include low start-up
current, pulse-by-pulse current limiting, and a high-current totem pole output for driving capacitive loads, such
as gate of a power MOSFET. The output is low in the off state, consistent
with N-channel devices.
Absolute Maximum Ratings
Supply Voltage (ICC<30mA).........................................................................Self Limiting
Supply Voltage (Low Impedance Source) .................................................................30V
Output Current..............................................................................................................±1A
Output Energy (Capacitive Load) ................................................................................5µJ
Analog Inputs (VFB, VSENSE) .........................................................................-0.3V to 5.5V
Error Amp Output Sink Current .............................................................................10mA
Lead Temperature Soldering
Wave Solder (through hole styles only) ...................10 sec. max, 260°C peak
Reflow (SMD styles only) ....................60 sec. max above 183°C, 230°C peak
■ Optimized for Offline
Control
■ Temp. Compensated
Oscillator
■ 50% Max Duty-cycle Clamp
■ VREF Stabilized before
Output Stage is Enabled
■ Low Start-up Current
■ Pulse-by-pulse Current
Limiting
■ Improved Undervoltage
Lockout
■ Double Pulse Suppression
■ 1% Trimmed Bandgap Ref.
■ High Current Totem Pole
Output
Package Options
8 Lead PDIP & SO Narrow
COMP
1
8
VREF
VFB
2
7
VCC
Sense
3
6
VOUT
OSC
4
5
Gnd
Block Diagram
14 Lead SO Narrow
V CC Undervoltage Lock-out
V CC
34V
V CC Pwr
Set/
5.0 Volt
Reset Reference
Gnd
V REF
16V/10V
(8.4V/7.6V)
V FB
Error
Amplifier
R
-
COMP
+
OSC
Internal
Bias
2.50V
Oscillator
V REF
Undervoltage
Lockout
Sense
VREF
13
NC
VFB 3
12
VCC
NC 4
11
VCC Pwr
Sense 5
10
VOUT
NC 6
9
Gnd
OSC 7
8
Pwr Gnd
16 Lead SO Wide
Toggle
Flip-Flop
NOR
V OUT
NC 1
16
NC
NC 2
15
VREF
COMP 3
14
VCC
VFB 4
13
VCCPwr
SENSE 5
12
VO
OSC 6
11
Gnd
NC 7
10
NC 8
9
Pwr Gnd
R
R
14
NC 2
R
S
2 R
COMP 1
1V
Current PWM
Sensing Latch
Comparator
Pwr Gnd
NC
( ) indicates CS-2845/3845
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 3/17/99
1
A
®
Company
CS2844/3845 SERIES
CS2844/CS3844
CS2845/CS3845
CS2844/3845 SERIES
Electrical Characteristics: -25 ≤ TA ≤ 85˚C for CS2844/2845, 0 ≤TA ≤ 70˚C for CS3844/3845. VCC = 15V (Note 1); RT = 10kΩ,
CT = 3.3nF for sawtooth mode., unless otherwise stated.
PARAMETER
TEST CONDITIONS
CS2844/CS2845
MIN TYP MAX
CS3844/CS3845
MIN TYP MAX UNITS
4.95
4.90
■ Reference Section
Output Voltage
TJ=25˚C, IREF=1mA
5.00
5.05
5.00
5.10 V
Line Regulation
12≤VCC≤25V
6
20
6
20
mV
Load Regulation
1≤IREF≤20mA
6
25
6
25
mV
Temperature Stability
(Note 2)
0.2
0.4
0.2
0.4
mV/˚C
Total Output Variation
Line, Load, Temp. (Note 2)
Output Noise Voltage
10Hz≤ f≤10kHz, TJ=25˚C (Note 2)
4.90
50
5.10
Long Term Stability
TA=125˚C, 1000 Hrs. (Note 2)
5
25
Output Short Circuit
TA=25˚C
-30
-100
-180
Initial Accuracy
Voltage Stability
Sawtooth Mode, TJ=25˚C
12≤VCC≤25V
47
52
0.2
57
1.0
Temperature Stability
Sawtooth Mode TMIN≤TA≤TMAX
(Note 2)
VOSC (peak to peak)
4.82
5.18 V
50
µV
5
25
mV
-30
-100
-180 mA
47
52
0.2
57
1.0
■ Oscillator Section
Amplitude
5
1.7
5
1.7
kHz
%
%
V
■ Error Amp Section
Input Voltage
VCOMP=2.5V
Input Bias Current
VFB=0V
2.45
2.50
2.55
-0.3
-1.0
2.42
2.50
2.58 V
-0.3
-2.0
µA
AVOL
2≤VOUT≤4V
65
90
65
90
dB
Unity Gain Bandwidth
(Note 2)
0.7
1.0
0.7
1.0
MHz
PSRR
12≤VCC≤25V
60
70
60
70
dB
Output Sink Current
VFB=2.7V, VCOMP=1.1V
2
6
2
6
mA
Output Source Current
VFB=2.3V, VCOMP=5V
-0.5
-0.8
-0.5
-0.8
mA
VOUT HIGH
VFB=2.3V, RL=15kΩ to Gnd
5
6
5
6
V
VOUT LOW
VFB=2.7V, RL=15kΩ to VREF
0.7
1.1
3.00
3.15
2.85
1.0
1.1
0.9
0.7
1.1
V
3.00
3.15 V/V
1.0
1.1
■ Current Sense Section
Gain
(Notes 3 & 4)
2.85
0.9
Maximum Input Signal
VCOMP=5V (Note 3)
PSRR
12≤VCC≤25V (Note 3)
70
Input Bias Current
VSense=0V
-2
-10
-2
-10
µA
Delay to Output
TJ=25˚C (Note 2)
150
300
150
300
ns
Output Low Level
ISINK=20mA
ISINK=200mA
0.1
1.5
0.4
2.2
0.1
1.5
0.4
2.2
V
V
Output High Level
ISOURCE=20mA
ISOURCE=200mA
Rise Time
TJ=25˚C, CL=1nF (Note 2)
50
150
50
150
ns
Fall Time
TJ=25˚C, CL=1nF (Note 2)
50
150
50
150
ns
70
V
dB
■ Output Section
13.0
12.0
2
13.5
13.5
13.0
12.0
13.5
13.5
V
V
PARAMETER
CS2844/CS2845
MIN TYP MAX
TEST CONDITIONS
CS3844/CS3845
MIN TYP MAX UNITS
■ Total Standby Current
Start-Up Current
0.5
1.0
0.5
1.0
mA
17
11
17
mA
Operating Supply Current
VFB=VSense=0V RT=10kΩ, CT=3.3nF
11
VCC Zener Voltage
ICC=25mA
34
34
V
■ PWM Section
Maximum Duty Cycle
46
48
50
Minimum Duty Cycle
PARAMETER
46
48
0
TEST CONDITIONS
MIN
CS2844
TYP MAX
MIN
CS3844
TYP MAX
50
%
0
%
CS2845/CS3845
MIN TYP MAX UNITS
■ Under-Voltage Lockout Section
Start Threshold
Min. Operating
Voltage
Notes:
After Turn On
15
16
17
14.5
16
17.5
7.8
8.4
9.0
V
9
10
11
8.5
10
11.5
7.0
7.6
8.2
V
1. Adjust Vcc above the start threshold before setting at 15V.
3. Parameter measured at trip point of latch with VFB=0.
2.These parameters, although guaranteed, are not 100% tested in production.
4. Gain defined as:
A=
∆VCOMP
∆VSense
; 0 ≤ VSense ≤ 0.8V.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Error amp output, used to compensate error amplifier.
8L
PDIP/SO
14L
SO Narrow
16L
SO Wide
1
1
3
COMP
2
3
4
VFB
3
5
5
Sense
Noninverting input to Current Sense Comparator.
4
7
6
OSC
Oscillator timing network with Capacitor to Ground, resistor to VREF.
5
9
11
Gnd
Ground.
8
10
Pwr Gnd
10
12
VOUT
11
13
VCCPwr
7
12
14
VCC
Positive power supply.
8
14
15
VREF
Output of 5V internal reference.
2,4,6,13
1,2,7,8,9,16
NC
No Connection.
6
Error amp inverting input.
Output driver Ground.
Output drive pin.
Output driver positive supply.
3
CS2844/3845 SERIES
Electrical Characteristics: -25≤TA≤85˚C for CS2844/2845, 0≤TA≤70˚C for CS3844/3845. VCC=15V (Note 1); RT=10kΩ,
CT=3.3nF for sawtooth mode., unless otherwise stated.
CS2844/3845 SERIES
Test Circuit Open Loop Laboratory Test Fixture
V REF
RT
2N2222
V CC
A
100kΩ
COMP
4.7kΩ
1kΩ
Error Amp
Adjust
V REF
V FB
V CC
0.1µF
5kΩ
4.7kΩ
0.1µF
V OUT
Sense
Sense
Adjust
OSC
1kΩ
1W
V OUT
Gnd
Gnd
CT
Circuit Description
V CC
Undervoltage Lockout
During Undervoltage Lockout (Figure 1), the output driver is biased to sink minor amounts of current. The output
should be shunted to ground with a resistor to prevent
activating the power switch with extraneous leakage currents.
ON/OFF Command
to reset of IC
V ON
V OFF
CSX844
CSX845
16V
10V
8.4V
7.6V
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure
2). An increase in VCC causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed-forward characteristic of current mode control, since
the control voltage does not have to change during
changes of input supply voltage.
When the power supply sees a sudden large output current increase, the control voltage will increase allowing
the duty cycle to momentarily increase. Since the duty
cycle tends to exceed the maximum allowed to prevent
transformer saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of OSC components.
I CC
<15mA
<1mA
V CC
V ON
V OFF
Figure 1: Startup voltage for CSX844 and CSX845.
4
Setting the Oscillator
The times Tc and Td can be determined as follows:
VOSC
OSC
RESET
t c = RTCT ln
Toggle
F/F Output
t d = RTCT ln
EA Output
Switch
Current
(
(
VREF - Vlower
VREF - Vupper
)
VREF - IdRT - Vlower
VREF - IdRT - Vupper
)
Substituting in typical values for the parameters in the
above formulas:
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA,
then
tc ≈ 0.5534RTCT
VCC
IO
VO
td = RTCT ln
Figure 2: Timing Diagram
(
2.3 - 0.0083 RT
4.0 - 0.0083 RT
)
For better accuracy RT should be ≥10kΩ.
Vupper
Grounding
Vlower
ton
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
toff
td
tC
ton = tC
toff = tC+2td
Figure 3: Duty Cycle parameters.
5
CS2844/3845 SERIES
Circuit Description: continued
CS2844/3845 SERIES
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Lead Count
Metric
Max
Min
10.16
9.02
5.00
4.80
8.75
8.55
10.50
10.10
8 Lead PDIP
8 Lead SO Narrow
14L SO Narrow
16L SO Wide
Thermal
Data
RΘJC
typ
RΘJA
typ
English
Max Min
.400 .355
.197 .189
.344 .337
.413 .398
Plastic DIP (N); 300 mil wide
8L
8L SO 14 L SO 16L SO
PDIP Narrow Narrow Wide
52
45
30
23
˚C/W
100
165
125
105
˚C/W
Surface Mount Narrow Body (D); 150 mil wide
7.11 (.280)
6.10 (.240)
8.26 (.325)
7.62 (.300)
1.77 (.070)
1.14 (.045)
4.00 (.157)
3.80 (.150)
6.20 (.244)
5.80 (.228)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
1.75 (.069) MAX
.356 (.014)
.203 (.008)
0.39 (.015)
MIN.
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
D
1.57 (.062)
1.37 (.054)
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
1.27 (.050)
0.40 (.016)
0.25 (.010)
0.19 (.008)
0.25 (0.10)
0.10 (.004)
D
REF: JEDEC MS-012
Ordering Information
Part Number 0˚C to -25˚C
70˚C to 85˚C
CS2844LN8
•
CS2844LD14
•
CS2844LDR14
•
CS2844LDW16
•
CS2844LDWR16
•
CS2845LN8
•
CS2845LDW16
•
CS2845LDWR16
•
CS3844GN8
•
CS3844GD8
•
CS3844GDR8
•
CS3844GD14
•
CS3844GDR14
•
CS3844GDW16
•
CS3844GDWR16 •
CS3845GN8
•
CS3845GD8
•
CS3845GDR8
•
CS3845GD14
•
CS3845GDR14
•
CS3845GDW16
•
CS3845GDWR16 •
Rev. 3/17/99
Surface Mount Wide Body (DW); 300 mil wide
Description
8L PDIP
14L SO
14L SO (Tape & Reel)
16L SO Wide
16L SO Wide (Tape & Reel)
8L PDIP
16L SO Wide
16L SO Wide (Tape & Reel)
8L PDIP
8L SO
8L SO (Tape & Reel)
14L SO
14L SO (Tape & Reel)
16L SO Wide
16L SO Wide (Tape & Reel)
8L PDIP
8L SO
8L SO (Tape & Reel)
14L SO
14L SO (Tape & Reel)
16L SO Wide
16L SO Wide (Tape & Reel)
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-013
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
D
0.30 (.012)
0.10 (.004)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
6
© 1999 Cherry Semiconductor Corporation
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