ESMT F25S004A Flash 2.5V Only 4 Mbit Serial Flash Memory FEATURES y Single supply voltage 2.3~3.3V y Speed - Read max frequency : 33MHz - Fast Read max frequency : 50MHz y y y Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte-Program operations Low power consumption - Active current：40mA - Standby current：75 μ A y SPI Serial Interface - SPI Compatible : Mode 0 and Mode3 y End of program or erase detection Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant y Program - Byte program time 7 μ s (typical) y Erase - Chip erase time 4sec(typical) - Block erase time 1sec (typical) - Sector erase time 90ms(typical) ORDERING INFORMATION PRODUCT ID SPEED PACKAGE COMMENTS F25S004A -50PG 50MHz 8 lead SOIC 150 mil Pb-free F25S004A -50PAG 50MHz 8 lead SOIC 200 mil Pb-free F25S004A –50DG 50MHz 8 lead PDIP 300 mil Pb-free GENERAL DESCRIPTION The F25S004A is a 4Megabit, 2.5V only CMOS Serial Flash memory device. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device features a sector erase architecture. The device memory array is divided into 128 uniform sectors with 4K byte each ; 8 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 1/33 ESMT F25S004A PIN CONFIGURATIONS 8-PIN SOIC CE 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI CE 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI 8-PIN PDIP Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 2/33 ESMT F25S004A PIN Description Symbol Pin Name Functions SCK Serial Clock To provide the timing for serial input and output operations SI Serial Data Input To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. CE Chip Enable To activate the device when CE is low. WP Write Protect The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. HOLD Hold VDD Power Supply VSS Ground To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 3/33 ESMT F25S004A SECTOR STRUCTURE Table1 : F25S004A Sector Address Table Block 7 6 5 4 3 2 1 0 Sector Sector Size (Kbytes) 127 4KB : : 112 4KB 070000H – 070FFFH 111 4KB 06F000H – 06FFFFH : : : 96 4KB 060000H – 060FFFH 95 4KB 05F000H – 05FFFFH : : : 80 4KB 050000H – 050FFFH 79 4KB 04F000H – 04FFFFH : : : 64 4KB 040000H – 040FFFH 63 4KB 03F000H – 03FFFFH : : 48 4KB 030000H – 030FFFH 47 4KB 02F000H – 02FFFFH Address range Block Address A18 A17 A16 07F000H – 07FFFFH : : : : : 32 4KB 020000H – 020FFFH 31 4KB 01F000H – 01FFFFH : : : 16 4KB 010000H – 010FFFH 15 4KB 00F000H – 00FFFFH : : : 0 4KB 000000H – 000FFFH Elite Semiconductor Memory Technology Inc. 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Publication Date: Jan. 2009 Revision: 1.1 4/33 ESMT F25S004A Table2 : F25S004A Block Protection Table Protection Level Status Register Bit Protected Memory Area BP2 BP1 BP0 Block Range 0 0 0 0 Upper 1/8 0 0 1 Block 7 70000H – 7FFFFH Upper 1/4 0 1 0 Block 6~7 60000H – 7FFFFH Upper 1/2 0 1 1 Block 4~7 40000H – 7FFFFH All Blocks 1 0 0 Block 0~7 00000H – 7FFFFH All Blocks 1 0 1 Block 0~7 00000H – 7FFFFH All Blocks 1 1 0 Block 0~7 00000H – 7FFFFH All Blocks 1 1 1 Block 0~7 00000H – 7FFFFH None Address Range None Block Protection (BP2, BP1, BP0) Block Protection Lock-Down (BPL) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the WP pin driven low (VIL), enables the Block-Protection -Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the BP2, BP1, BP0 bits as long as WP is high or the Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Elite Semiconductor Memory Technology Inc. WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Publication Date: Jan. 2009 Revision: 1.1 5/33 ESMT F25S004A FUNTIONAL BLOCK DIAGRAM Address Buffers and Latches Flash X-Decoder Y-Decoder I/O Butters and Data Latches Control Logic Serial Interface CE SCK Elite Semiconductor Memory Technology Inc. SI SO WP HOLD Publication Date: Jan. 2009 Revision: 1.1 6/33 ESMT F25S004A Hold Operation HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 21 for Hold timing. Similarly, if the rising edge of the HOLD signal does not S CK HO L D A ctive A ctive Ho ld Ho ld A ctive Figure 1 : HOLD CONDITION WAVEFORM Write Protection The device provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 2 for Block-Protection description. Write Protect Pin ( WP ) The Write Protect ( WP ) pin enables the lock-down function of TABLE3: CONDITIONS TO EXECUTE WRITE-STATUS- REGISTER (WRSR) INSTRUCTION WP BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP is high, the lock-down function of the BPL bit is disabled. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 7/33 ESMT F25S004A Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. TABLE 4: SOFTWARE STATUS REGISTER Bit Name 0 BUSY 1 WEL 2 3 4 5 BP0 BP1 BP2 RESERVED 6 AAI 7 BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 2) Indicate current level of block write protection (See Table 2) Indicate current level of block write protection (See Table 2) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP2,BP1,BP0 are read-only bits 0 = BP2,BP1,BP0 are read/writable Default at Power-up Read/Write 0 R 0 R 1 1 1 0 R/W R/W R/W N/A 0 R 0 R/W Note1 : Only BP0,BP1,BP2 and BPL are writable Note2 : All register bits are volatility Note3 : All area are protected at power-on (BP2=BP1=BP0=1) Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming reached its highest memory address • Sector-Erase instruction completion • Block-Erase instruction completion • Chip-Erase instruction completion • • • • • Write-Status-Register instructions Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 8/33 ESMT F25S004A Instructions Instructions are used to Read, Write (Erase and Program), and configure the device. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first transition of CE . Inputs will be accepted on the rising edge of TABLE 5: DEVICE OPERATION INSTRUCTIONS Cycle Type/ 1,2 Operation Max Freq 4 5 6 SIN SOUT SIN SOUT SIN SOUT A7-A0 Hi-Z X DOUT A7-A0 Hi-Z X X X DOUT A7-A0 Hi-Z A7-A0 Hi-Z - SIN A23-A16 A23-A16 A23-A16 A23-A16 SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - - Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z ADH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z 05H Hi-Z X DOUT - Note7 - Note7 - Note7 - - 50H Hi-Z - - - - - - - - - - 01H Hi-Z Data Hi-Z - - -. - - - - - 06H Hi-Z - - - - - - - - - - Write-Disable (WRDI) 04H Hi-Z - - - - - - - - - - Read-Electronic-Signature9 (RES) ABH Hi-Z X 12H - - - - - - - - Jedec-Read-ID (JEDEC-ID) 10 9FH Hi-Z X 8CH X 20H X 13H - - - - A7-A0 Hi-Z X 33 MHz 5 Byte-Program Auto-Address-Increment-word 6 programming (AAI) Read-Status-Register (RDSR) Enable-Write-Status-Register 8 (EWSR) Write-Status-Register (WRSR)8 Write-Enable (WREN) 11 Read-ID (RDID) Enable SO to output RY/BY# Status during AAI (EBSY) Disable SO to output RY/BY# Status during AAI (DBSY) 7. 8. Bus Cycle 3 SIN SOUT A15-A8 Hi-Z A15-A8 Hi-Z A15-A8 Hi-Z A15-A8 Hi-Z SOUT Hi-Z Hi-Z Hi-Z Hi-Z Chip-Erase5 6. 2 SIN 03H 0BH 20H D8H 60H C7H 02H Read High-Speed-Read Sector-Erase4,5 (4K Byte) Block-Erase5 (64K Byte) 1. 2. 3. 4. 5. 1 50MHz - 90H (A0=0) Hi-Z A23-A16 Hi-Z A15-A8 90H (A0=1) - Hi-Z - - - - - - DIN Hi-Z - - 8CH 12H 70H Hi-Z - - - - - - - - 80H Hi-Z - - - - - - - - X 12H 8CH Operation: SIN = Serial In, SOUT = Serial Out X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary) One bus cycle is eight clock periods. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be executed. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . 10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as memory Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 9/33 ESMT F25S004A capacity. 11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. Read (33 MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning 03H, followed by address bits [A23-A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. CE MODE3 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 SCK MODE1 03 SI MSB SO ADD. ADD. ADD. MSB HIGH IMPENANCE N N+1 N+2 N+3 N+4 DOUT DOUT DOUT DOUT D OUT MSB Figure 2 : READ SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 10/33 ESMT F25S004A Fast-Read (50 MHz) through all addresses until terminated by a low to high transition The High-Speed-Read instruction supporting up to 50 MHz is initiated by executing an 8-bit command, 0BH, followed by on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH has been read, the next output will be from address location 000000H. address bits [A23-A0] and a dummy byte. CE must remain active low for the duration of the High-Speed-Read cycle. See Figure 3 for the High-Speed-Read sequence. Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 0B SI MSB SO 15 16 ADD. 23 24 ADD. 31 32 ADD. 39 40 47 48 55 56 63 64 71 72 80 X MSB HIGH IMPENANCE N N+1 N+2 N+3 N+4 DOUT DOUT DOUT DOUT DOUT MSB Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3 : HIGH-SPEED-READ SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 11/33 ESMT F25S004A Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 4 for the Byte-Program sequence. instruction must be executed. CE must remain active low for the duration of the Byte-Program instruction. The Byte-Program CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 02 SI ADD. MSB SO 15 16 MSB 23 24 ADD. 31 32 ADD. 39 DIN MSB LSB HIGH IMPENANCE Figure 4 : BYTE-PROGRAM SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 12/33 ESMT F25S004A Auto Address Increment (AAI) WORD Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware detection by reading the SO; software detection by polling the BUSY in the software status register or wait TBP. Refer to End-of-Write Detection section for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data is input sequentially. The data is input sequentially from MSB (bit 7) to LSB (bit 0). The first byte of data(DO) will be programmed into the initial address [A23-A1] with A0 =0; The second byte of data(D1) will be programmed into the initial address [A23-A1] with A0 =1. CE must be driven high before the AAI WORD program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command. Please refer to Figures 7 and Figures 8. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0). End of Write Detection There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The hardware end of write detection method is described in the section below. Hardware End of Write Detection The hardware end of write detection method eliminates the overhead of polling the BUSY bit in the software status register during an AAI Word PROGRAM OPERATION. The 8bit command, 70H, configures the SO to indicate Flash Busy status during AAI WORD programming (refer to figure5). The 8bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A “0” Indicates the device is busy ; a “1” Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output software register data during AAI WORD programming (refer to figure6). FIGURE 5 : ENABLE SO AS HARDWARE RY / BY DURING AAI PROGRAMMING Elite Semiconductor Memory Technology Inc. FIGURE 6 : DISABLE SO AS HARDWARE RY / BY DURING AAI PROGRAMMING Publication Date: Jan. 2009 Revision: 1.1 13/33 ESMT F25S004A FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 14/33 ESMT F25S004A 64K-Byte Block-Erase The 64K Byte Block-Erase instruction clears all bits in the selected block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23-A0]. Address bits [AMS-A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence. FIGURE 9 : 64-KBYTE BLOCK-ERASE SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 15/33 ESMT F25S004A 4K-Byte-Sector-Erase The Sector-Erase instruction clears all bits in the selected sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 10 for the Sector-Erase sequence. Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits CE 15 16 0 1 2 3 4 5 6 7 8 MODE3 31 23 24 SCK MODE0 20 SI MSB SO ADD. ADD. ADD. MSB HIGH IMPENANCE FIGURE 10 : SECTOR-ERASE SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 16/33 ESMT F25S004A Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 11 for the Chip-Erase sequence. (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 60 or C7 SI MSB HIGH IMPENANCE SO FIGURE 11 : CHIP-ERASE SEQUENCE Read-Status-Register (RDSR) and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. until it is terminated by a low to high transition of the CE See Figure 12 for the RDSR instruction sequence. CE must be driven low before the RDSR instruction is entered CE 0 MODE3 1 2 3 4 5 6 7 8 9 Bit7 Bit6 10 11 12 13 14 Bit2 Bit1 SCK MODE1 05 SI MSB SO HIGH IMPENANCE MSB Bit5 Bit4 Bit3 Bit0 Status Register Out Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 17/33 ESMT F25S004A Write-Enable (WREN) The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. CE 0 1 2 3 4 5 6 7 MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE SO FIGURE 13 : WRITE ENABLE (WREN) SEQUENCE Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 04 SI MSB SO HIGH IMPENANCE Figure 14 : WRITE DISABLE (WRDI) SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 18/33 ESMT F25S004A Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 15 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lockdown the status register, but cannot be reset from “1” to “0”. When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions. CE MODE3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 1011 12 13 1415 SCK MODE0 50 or 06 SI MSB SO 01 STATUS REGISTER IN 7 6 5 4 3 2 1 0 MSB HIGH IMPENANCE Figure 15 : ENABLE-WRITE-STATUS-REGISTER (EWSR) or WRITE-ENABLE(WREN) and WRITE-STATUS-REGISTER (WRSR) Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 19/33 ESMT F25S004A Read-Electronic-Signature (RES) The RES instruction can be used to read the 8-bit Electronic Signature of the device on the SO pin. The RES instruction can provide access to the Electronic Signature of the device (except while an Erase, Program or WRSR cycle is in progress), Any ERS instruction executed while an Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress. CE 0 MODE3 1 2 3 4 5 6 7 8 9 Bit7 Bit6 10 11 12 13 14 Bit2 Bit1 SCK MODE1 AB SI MSB SO HIGH IMPENANCE MSB Bit5 Bit4 Bit3 Bit0 Status Register Out Figure 16 : Read-Electronic-Signature (RES) Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 20/33 ESMT F25S004A JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as F25S004A and the manufacturer as ESMT. The device information can be read from executing the 8-bit command,.9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 13H, identifies the device as F25S004A. The instruction sequence is shown in Figure17. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH). CE MODE3 SCK MODE0 SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 9F HIGH IMPENANCE 8C M SB 20 13 MSB Figure 17 : Jedec Read ID Sequence Table 9 : JEDEC READ-ID DATA Device ID Manufacturer’s ID Memory Type Memory Capacity Byte1 Byte 2 Byte 3 8CH 20H 13H Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 21/33 ESMT F25S004A Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25S004A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE . Figure 18 : Read-Electronic-Signature Table 10 : JEDEC READ-ID DATA Address Byte1 Byte2 Manufacturer’s ID 00000H 8CH 12H Device ID ESMT F25S004A 00001H 12H 8CH ELECTRICAL SPECIFICATIONS Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 22/33 ESMT F25S004A Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current (Note1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Note： 1. Output shorted for no more than one second. No more than one output shorted at a time. AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz See Figures 23 and 24 OPERATING RANGE Parameter Symbol Value Unit Operating Supply Voltage VDD 2.3~3.3 V Ambient Operating Temperature TA 0~70 °C TABLE 6: DC OPERATING CHARACTERISTICS Symbol IDDR Parameter Min Read Current Limits Max 15 Units mA Test Conditions CE =0.1 VDD/0.9 VDD@33 MHz, SO=open IDDW Program and Erase Current 40 mA ISB Standby Current 75 µA CE =VDD, VIN=VDD or VSS ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max 0.8 V VDD=VDD Min V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage 0.7 VDD 0.2 VDD-0.2 CE =VDD TABLE 7 : RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 VDD Min to Read Operation 10 µs TPU-WRITE1 VDD Min to Write Operation 10 µs 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum COUT1 Output Pin Capacitance VOUT = 0V 12 pF CIN1 Input Capacitance VIN = 0V 6 pF 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 23/33 ESMT F25S004A TABLE 11: RELIABILITY CHARACTERISTICS Symbol 1. Parameter NEND1 Endurance TDR1 Data Retention ILTH1 Latch Up Minimum Specification Units Test Method 100,000 Cycles JEDEC Standard A117 10 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12 : AC OPERATING CHARACTERISTICS Normal 33MHz Symbol Fast 50 MHz Parameter Units Min Max Min FCLK Serial Clock Frequency TSCKH Serial Clock High Time 13 9 ns TSCKL Serial Clock Low Time 13 9 ns CE Active Setup Time 5 5 ns TCEH1 CE Active Hold Time 5 5 ns TCHS1 CE Not Active Setup Time 5 5 ns TCHH1 CE Not Active Hold Time 5 5 ns TCPH CE High Time 100 100 ns TCHZ CE High to High-Z Output TCLZ SCK Low to Low-Z Output 0 0 ns TDS Data In Setup Time 3 3 ns TDH Data In Hold Time 3 3 ns THLS HOLD Low Setup Time 5 5 ns THHS HOLD High Setup Time 5 5 ns THLH HOLD Low Hold Time 5 5 ns THHH HOLD High Hold Time 5 5 ns THZ HOLD Low to High-Z Output 9 9 ns TLZ HOLD High to Low-Z Output 9 9 ns TOH Output Hold from SCK Change TV Output Valid from SCK TCES 1 33 Max 50 9 0 9 0 12 MHz ns ns 12 ns 1. Relative to SCK. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 24/33 ESMT F25S004A ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Symbol Typ.(2) Max.(3) Unit Sector Erase Time TSE 90 200 ms Block Erase Time TBE 1 2 s Chip Erase Time TCE 4 30 s Byte Programming Time TBP 7 300 us 12 100 s 100,000 - Cycles 20 - Years Chip Programming Time Erase/Program Cycles (1) Data Retention Notes: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 2.5V. 3.Maximum values measured at 85°C, 2.3V. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 25/33 ESMT F25S004A FIGURE 19: SERIAL INPUT TIMING DIAGRAM FIGURE 20: SERIAL OUTPUT TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 26/33 ESMT F25S004A CE# SCK SO SI HOLD# FIGURE 21: HOLD TIMING DIAGRAM FIGURE 22: POWER-UP TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 27/33 ESMT F25S004A Input timing reference level Output timing reference level 0.8VCC 0.7VCC 0.3VCC 0.2VCC AC Measurement Level 0.5VCC Note : Input pulse rise and fall time are <5ns FIGURE 23 : AC INPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 24: A TEST LOAD EXAMPLE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 28/33 ESMT F25S004A PACKAGING DIAGRAMS 8-LEAD SOP ( 150 mil ) 5 GAUGE PLANE 0 0.25 H E 8 L DETAIL "X" 1 4 e b L1 "X" A1 A2 A C D SEATING PLANE Dimension in mm Dimension in inch Dimension in mm Symbol Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A 1.35 1.60 1.75 0.053 0.063 0.069 D 4.80 4.90 5.00 0.189 0.193 0.197 A1 0.10 0.15 0.25 0.004 0.006 0.010 E 3.80 3.90 4.00 0.150 0.154 0.157 A2 1.25 1.45 1.55 0.049 0.057 0.061 L 0.40 0.66 1.27 0.016 0.026 0.050 b 0.33 0.406 0.51 0.013 0.016 0.020 e c 0.19 0.203 0.25 0.0075 0.008 0.010 L1 1.00 1.05 1.10 0.039 0.041 0.043 H 5.80 6.00 6.20 0.228 0.236 0.244 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 29/33 ESMT PACKING 8-LEAD F25S004A DIMENSIONS SOIC 200 mil (official name - 209 mil) 5 1 4 E1 8 E θ b e A A2 D L A1 L1 SEATING PLANE Dimension in mm Dimension in inch DETAIL "X" Dimension in mm Symbol Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A --- --- 2.16 --- --- 0.085 E 7.70 7.90 8.10 0.303 0.311 0.319 A1 0.05 0.15 0.25 0.002 0.006 0.010 E1 5.18 5.28 5.38 0.204 0.208 0.212 A2 1.70 1.80 1.91 0.067 0.071 0.075 L 0.50 0.65 0.80 0.020 0.026 0.032 b 0.36 0.41 0.51 0.014 0.016 0.020 e c 0.19 0.20 0.25 0.007 0.008 0.010 L1 1.27 1.37 1.47 0.050 0.054 0.058 D 5.13 5.23 5.33 0.202 0.206 0.210 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 30/33 ESMT F25S004A PACKAGING DIAGRAMS SOIC ( 150 mil ) 5 GAUGE PLANE 0 0.25 E 8 H 8-LEAD L DETAIL "X" 1 4 e b L1 "X" A1 A2 A C D SEATING PLANE Dimension in mm Dimension in inch Dimension in mm Symbol Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A 1.35 1.60 1.75 0.053 0.063 0.069 D 4.80 4.90 5.00 0.189 0.193 0.197 A1 0.10 0.15 0.25 0.004 0.006 0.010 E 3.80 3.90 4.00 0.150 0.154 0.157 A2 1.25 1.45 1.55 0.049 0.057 0.061 L 0.40 0.66 0.86 0.016 0.026 0.034 b 0.33 0.406 0.51 0.013 0.016 0.020 e c 0.19 0.203 0.25 0.0075 0.008 0.010 L1 1.00 1.05 1.10 0.039 0.041 0.043 H 5.80 6.00 6.20 0.228 0.236 0.244 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 31/33 ESMT F25S004A Revision History Revision Date 1.0 2008.09.24 Original 2009.01.12 1. Correct the size of "L" in the packaging diagram of SOIC 150mil 2.Add operating range table 3.Delete the rating of Temperature Under Bias 4.Add the symbol for erase and byte programming time 5.Correct typo error 6.Modify headline 1.1 Elite Semiconductor Memory Technology Inc. Description Publication Date: Jan. 2009 Revision: 1.1 32/33 ESMT F25S004A Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT 's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.1 33/33