DAIDM Series FAST / TTL Buffered 5-Tap Dual Edge Delay Modules Low Profile 14-Pin Package Two Surface Mount Versions Electrical Specifications at 25OC 8-Pin Versions: FAMDM Series SIP Versions: FSIDM Series Dual Edge 14-Pin DIP P/N 5 Equal Delay Taps Low Voltage CMOS Versions refer to LVMDM / LVIDM Series Operating Temperature Range 0OC to +70OC DAIDM 14-Pin Schematic Tap1 Tap3 Tap5 14 12 10 8 1 4 6 7 IN Tap2 Tap4 GND Tap 1 Tap 3 Tap 4 Tap-to-Tap (ns) Total - Tap 5 DImensions in Inches (mm) TEST CONDITIONS -- FAST / TTL VCC Supply Voltage ................................................ 5.00VDC Input Pulse Voltage ................................................... 3.20V Input Pulse Rise Time ....................................... 3.0 ns max. Input Pulse Width / Period ........................... 1000 / 2000 ns 1. Measurements made at 25OC 2. Delays measured at 1.50V level of leading & trailing edge. 3. Rise Times measured from 0.75V to 2.40V. 4. 10pf probe and fixture load on output under test. OPERATING SPECIFICATIONS VCC Supply Voltage ................................... 5.00 ± 0.25 VDC ICC Supply Current .................................... 48 mA Maximum Logic “1” Input: VIH ....................... 2.00 V min., 5.50 V max. IIH ............................... 20 µA max. @ 2.70V Logic “0” Input: VIL .......................................... 0.80 V max. IIL ............................................ -0.6 mA mA VOH Logic “1” Voltage Out .................................. 2.40 V min. VOL Logic “0” Voltage Out ............................... 0.50 V max. PWI Input Pulse Width ............................. 40% of Delay min. Operating Temperature Range ............................ 0O to 70OC Storage Temperature Range ...................... -65O to +150OC P/N Description Tap 2 DAIDM-7 3.0 4.0 5.0 6.0 7 ± 1.0 ∗∗ 1 ± 0.5 DAIDM-9 3.0 4.5 6.0 7.5 9 ± 1.0 ∗∗ 1.5 ± 0.5 DAIDM-11 3.0 5.0 7.0 9.0 11 ± 1.0 ∗∗ 2 ± 0.7 DAIDM-13 3.0 5.5 8.0 10.5 13 ± 1.5 ∗∗ 2.5 ± 1.0 DAIDM-15 3.0 6.0 9.0 12.0 15 ± 1.5 3 ± 1.0 DAIDM-20 4.0 8.0 12.0 16.0 20 ± 2.0 4 ± 1.5 DAIDM-25 5.0 10.0 15.0 20.0 25 ± 2.0 5 ± 2.0 DAIDM-30 6.0 12.0 18.0 24.0 30 ± 2.0 6 ± 2.0 DAIDM-35 7.0 14.0 21.0 28.0 35 ± 2.0 7 ± 2.0 DAIDM-40 8.0 16.0 24.0 32.0 40 ± 2.0 8 ± 2.0 DAIDM-50 10.0 20.0 30.0 40.0 50 ± 2.5 10 ± 2.0 DAIDM-60 12.0 24.0 36.0 48.0 60 ± 3.0 12 ± 2.0 DAIDM-75 15.0 30.0 45.0 60.0 75 ± 3.75 15 ± 2.5 DAIDM-100 20.0 40.0 60.0 80.0 100 ± 5.0 20 ± 3.0 ** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1. FAST/TTL Logic Buffered Vcc Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns) .250 .020 (6.35) (0.51) MAX. DIP .120 (3.05) MIN. .020 (0.51) TYP. .050 (1.27) TYP. .050 (1.27) TYP. .250 (6.35) MAX. .100 (2.54) TYP. .015 (0.38) TYP. .030 (0.76) TYP. G-SMD .008 R (0.20) .010 (0.25) TYP. .430 (10.92) .400 (10.16) .285 (7.24) MAX. .265 (6.73) MAX. J-SMD .050 (1.27) TYP. .010 (0.25) TYP. MAX. .785 (19.94) MAX. .020 (0.51) TYP. .300 (7.62) .008 R (0.20) .285 (7.24) G-SMD .020 (0.51) TYP. DIP .365 (9.27) MAX. .100 (2.54) TYP. .785 (19.94) MAX. DAIDM - XXX X Dual Edge Controlled Buffered 5 Tap Delay Molded Package Series: 14-pin DIP: DAIDM Total Delay in nanoseconds (ns) Lead Style: Blank = Thru-hole G = “Gull Wing” SMD J = “J” Bend SMD .285 (7.24) MAX. .785 (19.94) MAX. .100 (2.54) TYP. .030 (0.76) TYP. J-SMD .285 (7.24) .260 (6.60) .020 R (0.51) .330 (8.38) MAX. Examples: DAIDM-25G = 25ns (5ns per tap) 74F, 14-Pin G-SMD DAIDM-100 = 100ns (20ns per tap) 74F, 14-Pin DIP Specifications subject to change without notice. Rhombus Industries Inc. For other values & Custom Designs, contact factory. DAIDM 9901 15801 Chemical Lane, Huntington Beach, CA 92649-1595 Phone: (714) 898-0960 • FAX: (714) 896-0971 www.rhombus-ind.com • email: [email protected]