CAT34C02 2 kb I2C EEPROM for DDR2 DIMM Serial Presence Detect Description The CAT34C02 is a 2 kb Serial CMOS EEPROM, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each. It features a 16−byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory) or by setting an internal Write Protect flag via Software command (this protects the lower half of the memory). In addition to Permanent Software Write Protection, the CAT34C02 also features JEDEC compatible Reversible Software Write Protection for DDR2 Serial Presence Detect (SPD) applications operating over the 1.7 V to 3.6 V supply voltage range. The CAT34C02 is fully backwards compatible with earlier DDR1 SPD applications operating over the 1.7 V to 5.5 V supply voltage range. http://onsemi.com TSSOP−8 Y SUFFIX CASE 948AL TDFN−8 VP2 SUFFIX CASE 511AK UDFN−8 HU3 SUFFIX CASE 517AX UDFN−8 EP HU4 SUFFIX CASE 517AZ Features • • • • • • • • • • • Supports Standard and Fast I2C Protocol 1.7 V to 5.5 V Supply Voltage Range 16−Byte Page Write Buffer Hardware Write Protection for Entire Memory Software Write Protection for Lower 128 Bytes Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Range This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant* VCC PIN CONFIGURATION A0 WP A2 SCL VSS SDA TSSOP (Y), TDFN (VP2), UDFN (HU3), UDFN (HU4) For the location of Pin 1, please consult the corresponding package drawing. PIN FUNCTION Pin Name SCL CAT34C02 SDA WP VSS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. March, 2011 − Rev. 17 Function Device Address Input SDA Serial Data Input/Output SCL Serial Clock Input WP Write Protect Input VCC Power Supply VSS Ground ORDERING INFORMATION Figure 1. Functional Symbol © Semiconductor Components Industries, LLC, 2011 VCC A1 A0, A1, A2 A2, A1, A0 1 1 See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Publication Order Number: CAT34C02/D CAT34C02 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Voltage on Pin A0 with Respect to Ground −0.5 to +10.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Note 3) TDR Parameter Endurance Min Units 1,000,000 Program/ Erase Cycles 100 Years Data Retention 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.) Symbol Parameter ICC Supply Current ISB Standby Current Test Conditions Min VCC < 3.6 V, fSCL = 100 kHz VCC > 3.6 V, fSCL = 400 kHz IL All I/O Pins at GND or VCC I/O Pin Leakage VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage Max Units 1 mA 2 TA = −40°C to +85°C VCC ≤ 3.3 V 1 TA = −40°C to +85°C VCC > 3.3 V 3 Pin at GND or VCC mA 2 mA −0.5 0.3 x VCC V 0.7 x VCC VCC + 0.5 VCC > 2.5 V, IOL = 3 mA 0.4 VCC < 2.5 V, IOL = 1 mA 0.2 Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.) Symbol CIN (Note 4) Parameter SDA I/O Pin Capacitance Conditions Max Units VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 8 pF Other Input Pins IWP (Note 5) IA (Note 5) WP Input Current Address Input Current (A0, A1, A2) Product Rev H 6 VIN < VIH, VCC = 5.5 V 130 VIN < VIH, VCC = 3.6 V 120 VIN < VIH, VCC = 1.7 V 80 VIN > VIH 2 VIN < VIH, VCC = 5.5 V 50 VIN < VIH, VCC = 3.6 V 35 VIN < VIH, VCC = 1.7 V 25 VIN > VIH 2 mA mA 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. http://onsemi.com 2 CAT34C02 Table 5. A.C. CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C) (Note 6) Standard Min Parameter Symbol FSCL Max Clock Frequency tHD:STA Fast Min 100 START Condition Hold Time Max Units 400 kHz 4 0.6 ms tLOW Low Period of SCL Clock 4.7 1.3 ms tHIGH High Period of SCL Clock 4 0.6 ms tSU:STA START Condition Setup Time 4.7 0.6 ms tHD:DAT Data Hold Time 0 0 ms tSU:DAT Data Setup Time 250 100 ns tR (Note 7) SDA and SCL Rise Time 1000 300 ns tF (Note 7) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time 4 tBUF Bus Free Time Between STOP and START tAA SCL Low to SDA Data Out tDH Data Out Hold Time Ti (Note 7) 0.6 4.7 ms 1.3 ms 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs 0.9 100 ms ns 100 100 ns tSU:WP WP Setup Time 0 0 ms tHD:WP WP Hold Time 2.5 2.5 ms tWR tPU (Notes 7 & 8) Write Cycle Time 5 5 ms Power−up to Ready Mode 1 1 ms 6. Test conditions according to “A.C. Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. THERMAL CHARACTERISTICS (Air velocity = 0 m/s, 4 layers PCB) (Notes 9 and 10) Part Number CAT34C02Y Package qJA qJC Units TSSOP 64 37 °C/W CAT34C02VP2 TDFN 92 15 °C/W CAT34C02HU3 UDFN 101 18 °C/W CAT34C02HU4 UDFN 101 18 °C/W 9. TJ = TA + PD * qJA, where: TJ is the Junction Temperature, TA the Ambient Temperature, PD the Power dissipation. Example: CAT34C02VP2, VCC = 3.0 V, ICCmax = 1 mA, TA = 85°C: TJ = 85°C + 3 mW * 92°C/W = 85.276°C. 10. TJ = TC + PD * qJC, where: TC is the Case Temperature, etc. Table 7. A.C. TEST CONDITIONS Input Levels 0.2 VCC to 0.8 VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 VCC, 0.7 VCC Output Reference Levels 0.5 VCC Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF http://onsemi.com 3 CAT34C02 Power−On Reset (POR) The CAT34C02 incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The CAT34C02 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power. device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2). Start The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. These pins have on−chip pull−down resistors. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on−chip pull−down resistor. Stop The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command). Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. Functional Description The CAT34C02 supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT34C02 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 5. I2C Bus Protocol The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull−up resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting SDA SCL START BIT STOP BIT Figure 2. Start/Stop Timing http://onsemi.com 4 CAT34C02 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 4. Acknowledge Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 5. Bus Timing Write Operations The internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a ‘wrap−around’ fashion (within the selected page). The internal Write cycle starts immediately following the STOP. Byte Write In Byte Write mode the Master sends a START, followed by Slave address, byte address and data to be written (Figure 6). The Slave acknowledges all 3 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 7). During internal Write, the Slave will not acknowledge any Read or Write request from the Master. Acknowledge Polling Acknowledge polling can be used to determine if the CAT34C02 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a ‘Selective Read’ command (see READ OPERATIONS). The CAT34C02 will not acknowledge the Slave address, as long as internal Write is in progress. Page Write The CAT34C02 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. A page is selected by the 4 most significant bits of the address byte following the Slave address, while the 4 least significant bits point to the byte within the page. Up to 16 bytes can be written in one Write cycle (Figure 8). Delivery State The CAT34C02 is shipped ‘unprotected’, i.e. neither SWP flag is set. The entire 2 kb memory is erased, i.e. all bytes are FFh. http://onsemi.com 5 CAT34C02 BUS ACTIVITY: MASTER SDA LINE S T A R T BYTE ADDRESS SLAVE ADDRESS S T O P DATA S P A C K A C K A C K Figure 6. Byte Write Timing SCL 8th Bit SDA ACK Byte n tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) DATA n DATA n+1 S T O P DATA n+P S P A C K A C K A C K A C K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Figure 8. Page Write Timing BYTE ADDRESS DATA 1 8 9 A7 A0 1 8 D7 D0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing http://onsemi.com 6 A C K CAT34C02 Read Operations The address counter can be initialized by performing a ‘dummy’ Write operation (Figure 11). Here the START is followed by the Slave address (with the R/W bit set to ‘0’) and the desired byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier. Immediate Address Read In standby mode, the CAT34C02 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that ‘previous’ byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a START, the CAT34C02 is presented with a Slave address containing a ‘1’ in the R/W bit position (Figure 10), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition. Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT34C02, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 12). If the end of memory is reached during sequential Read, then the address counter will ‘wrap−around’ to the beginning of memory, etc. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. Selective Read The Read operation can also be started at an address different from the one stored in the internal address counter. BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS P S A C K DATA 8 SCL SDA N O A C K 9 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T A R T BYTE ADDRESS (n) SLAVE ADDRESS S T O P SLAVE ADDRESS P S S A C K A C K A C K Figure 11. Selective Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 DATA n N O A C K S T O P DATA n+x SDA LINE P A C K A C K A C K Figure 12. Sequential Read Timing http://onsemi.com 7 A C K N O A C K CAT34C02 Software Write Protection The lower half of memory (first 128 bytes) can be protected against Write requests by setting one of two Software Write Protection (SWP) flags. The Permanent Software Write Protection (PSWP) flag can be set or read while all address pins are at regular CMOS levels (GND or VCC), whereas the very high voltage VHV must be present on address pin A0 to set, clear or read the Reversible Software Write Protection (RSWP) flag. The D.C. OPERATING CONDITIONS for RSWP operations are shown in Table 8. The SWP commands are listed in Table 9. All commands are preceded by a START and terminated with a STOP, following the ACK or NoACK from the CAT34C02. All SWP related Slave addresses use the pre−amble: 0110 (6h), instead of the regular 1010 (Ah) used for memory access. For PSWP commands, the three address pins can be at any logic level, whereas for RSWP commands the address pins must be at pre−assigned logic levels. VHV is interpreted as logic ‘1’. The VHV condition must be established on pin A0 before the START and maintained just beyond the STOP. Otherwise an RSWP request could be interpreted by the CAT34C02 as a PSWP request. The SWP Slave addresses follow the standard I2C convention, i.e. to read the state of the SWP flag, the LSB of the Slave address must be ‘1’, and to set or clear a flag, it must be ‘0’. For Write commands a dummy byte address and dummy data byte must be provided (Figure 14). In contrast to a regular memory Read, a SWP Read does not return Data. Instead the CAT34C02 will respond with NoACK if the flag is set and with ACK if the flag is not set. Therefore, the Master can immediately follow up with a STOP, as there is no meaningful data following the ACK interval (Figure 15). Hardware Write Protection With the WP pin held HIGH, the entire memory, as well as the SWP flags are protected against Write operations, see Memory Protection Map below. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT34C02. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT34C02 will not acknowledge the data byte and the Write request will be rejected. FFH Hardware Write Protectable (by connecting WP pin to VCC) 7FH Software Write Protectable (by setting the write protect flags) 00H Figure 13. Memory Protection Map Table 8. RSWP D.C. OPERATING CONDITIONS (Note 11) Symbol Parameter DVHV A0 Overdrive (VHV − VCC) IHVD A0 High Voltage Detector Current VHV A0 Very High Voltage IHV A0 Input Current @ VHV Test Conditions Min 1.7 V < VCC < 3.6 V 4.8 7 Max Units 0.1 mA 10 V 1 mA V 11. To prevent damaging the CAT34C02 while applying VHV, it is strongly recommended to limit the power delivered to pin A0, by inserting a series resistor (> 1.5 kW) between the supply and the input pin. The resistance is only limited by the combination of VHV and maximum IHVD. While the resistor can be omitted if VHV is clamped well below 10 V, it nevertheless provides simple protection against EOS events. As an example: VCC = 1.7 V, VHV = 8 V, 1.5 kW < RS < 15 kW. http://onsemi.com 8 CAT34C02 Table 9. SWP COMMANDS Action Set PSWP Control Pin Levels (Note 12) Flag State (Note 13) Slave Address b3 b2 b1 b0 ACK ? X A2 A1 A0 X No 0 X A2 A1 A0 0 0 X A2 A1 A0 0 WP A2 A1 A0 PSWP X A2 A1 A0 1 GND A2 A1 A0 VCC A2 A1 A0 RSWP b7 to b4 Address Byte ACK ? Data Byte ACK ? Write Cycle Yes X Yes X Yes Yes Yes X Yes X No No X A2 A1 A0 0 X A2 A1 A0 1 Yes X GND GND VHV 1 X 0 0 1 X No GND GND VHV 0 1 GND GND VHV 0 0 X Set GND RSWP VCC X X Clear GND RSWP V CC X 0110 0 0 1 X No 0 0 1 0 Yes X Yes X Yes Yes X Yes X No No GND GND VHV 0 0 0 0 1 0 Yes GND GND VHV 0 0 0 0 1 1 Yes GND VCC VHV 1 X 0 1 1 X No GND VCC VHV 0 X 0 1 1 0 Yes X Yes X Yes Yes GND VCC VHV 0 X 0 1 1 0 Yes X Yes X No No GND VCC VHV 0 X 0 1 1 1 Yes 12. Here A2, A1 and A0 are either at VCC or GND. 13. 1 stands for ‘Set’, 0 stands for ‘Not Set’, X stands for ‘don’t care’. BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S DATA XXXXXXXX XXXXXXXX A C K A C K Figure 14. Software Write Protect (Write) SDA LINE S T A R T SLAVE ADDRESS S S T O P P N A C or O K A C K Figure 15. Software Write Protect (Read) http://onsemi.com 9 P N A C or O K A C K X = Don’t Care BUS ACTIVITY: MASTER S T O P BYTE ADDRESS CAT34C02 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.20 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 10 CAT34C02 PACKAGE DIMENSIONS TDFN8, 2x3 CASE 511AK−01 ISSUE A D A e b E2 E PIN#1 IDENTIFICATION A1 PIN#1 INDEX AREA D2 TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 0.45 0.55 0.65 A3 A2 A3 0.20 0.25 0.30 D 1.90 2.00 2.10 D2 1.30 1.40 1.50 E 2.90 3.00 3.10 E2 1.20 1.30 1.40 L BOTTOM VIEW 0.20 REF b e FRONT VIEW 0.50 TYP 0.20 0.30 L 0.40 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. http://onsemi.com 11 CAT34C02 PACKAGE DIMENSIONS UDFN8, 2x3 CASE 517AX−01 ISSUE O D A DETAIL A DAP SIZE 1.3 x 1.8 E PIN #1 IDENTIFICATION E2 A1 PIN #1 INDEX AREA D2 TOP VIEW SYMBOL MIN NOM MAX A 0.45 0.50 0.55 A1 0.00 0.02 0.05 A3 b L 0.127 REF K b 0.20 0.25 0.30 D 1.90 2.00 2.10 D2 1.50 1.60 1.70 E 2.90 3.00 3.10 E2 0.10 0.20 0.30 e 0.50 TYP K 0.10 REF L BOTTOM VIEW SIDE VIEW 0.30 0.35 e DETAIL A A3 A 0.40 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. A1 FRONT VIEW http://onsemi.com 12 CAT34C02 PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ−01 ISSUE O D b A e L DAP SIZE 1.8 x 1.8 E2 E PIN #1 IDENTIFICATION A1 PIN #1 INDEX AREA D2 TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.45 0.50 0.55 A1 0.00 0.02 0.05 A3 b 0.127 REF 0.20 0.25 0.30 D 1.95 2.00 2.05 D2 1.35 1.40 1.45 E 2.95 3.00 3.05 E2 1.25 1.30 1.35 e L BOTTOM VIEW DETAIL A 0.065 REF A3 A FRONT VIEW 0.50 REF 0.25 0.30 0.35 A3 Notes: (1) All dimensions are in millimeters. (2) Refer JEDEC MO-236/MO-252. 0.0 - 0.05 DETAIL A http://onsemi.com 13 0.065 REF Copper Exposed CAT34C02 Example of Ordering Information CAT34C02 (Note 16) Prefix Device # Suffix CAT 34C02 Y Company ID I −G T5 Temperature Range Lead Finish G: NiPdAu Lead Plating Tape & Reel (Note 22) T: Tape & Reel 4: 4000/Reel (Note 17) 5: 5000/Reel (Note 18) I = Industrial (−40°C to +85°C) Product Number 34C02 Package Y: TSSOP VP2: TDFN (Note 19) HU3: UDFN (Note 19) HU4: UDFN 14. All packages are RoHS−compliant (Lead−free, Halogen−free) 15. The standard lead finish is NiPdAu. 16. The device used in the above example is a CAT34C02YI−GT5 (TSSOP, Industrial Temperature, NiPdAu, 5000 pcs / Reel) 17. The TDFN and UDFN packages are available in 4000 pcs/Reel (i.e., CAT34C02VP2I−GT4, CAT34C02HU3I−GT4, CAT34C02HU4I−GT4). 18. The TSSOP (Y) package (i.e., CAT34C02YI−GT5) is available in 5000 pcs / Reel. 19. Not recommended for new designs. Please replace with UDFN 2 x 3 mm (HU4) package. 20. For Gresham ONLY die, please order the OPNs: CAT34C02YI-GT5A, CAT34C02VP2IGT4A, CAT34C02HU3IGT4A or CAT34C02HU4IGT4A. 21. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 22. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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