TI CD74HC03 High speed cmos logic quad 2-input nand gate with open drain Datasheet

[ /Title
(CD74H
C03,
CD74H
CT03)
/Subject
(High
Speed
CMOS
Logic
Quad 2Input
CD74HC03,
CD74HCT03
Data sheet acquired from Harris Semiconductor
SCHS126
High Speed CMOS Logic
Quad 2-Input NAND Gate with Open Drain
February 1998
Features
Description
• Buffered Inputs
The Harris CD74HC03 and CD74HCT03 logic gates utilize
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally as well as pin compatible with the standard 74LS
logic family.
• Typical Propagation Delay: 8ns at VCC = 5V,
CL = 15pF, TA = 25oC
• Output Pull-up to 10V
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
These open drain NAND gates can drive into resistive loads
to output voltages as high as 10V. Minimum values of RL
required verses load voltage are shown in Figure 2.
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
TEMP. RANGE
(oC)
PKG.
NO.
PACKAGE
CD74HC03E
-55 to 125
14 Ld PDIP
E14.3
CD74HCT03E
-55 to 125
14 Ld PDIP
E14.3
CD74HC03M
-55 to 125
14 Ld SOIC
M14.15
CD74HCT03M
-55 to 125
14 Ld SOIC
M14.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC03, CD74HCT03
(PDIP, SOIC)
TOP VIEW
1A 1
14 VCC
1B 2
13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number
1832.1
CD74HC03, CD74HCT03
Functional Diagram
1A
1B
2A
2B
3A
3B
4A
4B
1
3
2
4
5
6
9
8
1Y
2Y
3Y
10
12
11
13
4Y
GND = 7
VCC = 14
TRUTH TABLE
A
B
Y
L
L
Z (Note 4)
H (Note 3)
H
L
Z (Note 4)
H (Note 3)
L
H
Z (Note 4)
H (Note 3)
H
H
L
L
NOTES:
3. Requires pull-up (RL to VL)
4. Without pull-up (high impedance)
Logic Symbol
nA
nY
nB
2
CD74HC03, CD74HCT03
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC Drain Current, per Output, IO
For -0.5V < VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
Low Level Output
Voltage
CMOS Loads
VIL
VOL
-
VIH or
VIL
Low Level Output
Voltage
TTL Loads
-
-
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
2
-
20
-
40
µA
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
Input Leakage
Current
Quiescent Device
Current
HCT TYPES
3
CD74HC03, CD74HCT03
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
Low Level Output
Voltage CMOS Loads
VOL
VIH or
VIL
25oC
IO (mA) VCC (V)
0.02
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
II
VCC
and
GND
4
5.5
-
ICC
VCC or
GND
0
5.5
-
-
2
-
20
-
40
µA
∆ICC
(Note 6)
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
-40oC TO 85oC
NOTE:
6. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nA, nB
1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
100
-
125
-
150
ns
4.5
-
-
20
-
25
-
30
ns
6
-
-
17
-
21
-
26
ns
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
5
-
8
-
-
-
-
-
ns
Transition Times (Figure 1)
tTLH, tTHL
CL = 50pF
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 7, 8)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
6.4
-
-
-
-
-
pF
HCT TYPES
Propagation Delay,
Input to Output (Figure 1)
tPLH, tPHL
CL = 50pF
4.5
-
-
24
-
30
-
36
ns
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
5
-
9
-
-
-
-
-
ns
Transition Times (Figure 1)
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
-
-
-
10
-
10
-
10
pF
Input Capacitance
CI
-
4
CD74HC03, CD74HCT03
Switching Specifications Input tr, tf = 6ns
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
Power Dissipation Capacitance
(Notes 7, 8)
CPD
-
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
5
-
9
-
-
-
-
-
pF
NOTES:
7. CPD is used to determine the dynamic power consumption, per gate.
8. PD = CPD VCC2 fi + Σ (CL VCC2 fo) + Σ (VL2/RL) (Duty Factor “Low”)
where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage, Duty Factor “Low” = percent of
time output is “low”, VL = output voltage, RL = pull-up resistor.
Test Circuits and Waveforms
800
INPUT LEVEL
VS
RL MIN, PULLUP RESISTOR (Ω)
VS
tPZL
tPLZ
VOH
90%
nY
10%
VOL
tTHL
OUTPUT
LOW
OUTPUT
OFF
OUTPUT
LOW
1kΩ
nA(nB)
VCC
OPEN
DRAIN
NAND
GATE
nB(nA)
500
HCT
400
VCC = 5V
±10%
300
VL
HC
RL
200
HC/HCT03
100
0
FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY
TIMES, AND TEST CIRCUIT
tr = 6ns
VO
1
2
3
4
5
6
7
VL, LOAD VOLTAGE (V)
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
9
tf = 6ns
tr = 6ns
VCC
90%
50%
10%
8
10
FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE
tf = 6ns
tPHL
600
0.8V (HCT VIL MAX)
≤ 1.35V (HC VIL MAX)
RL
0.26V
MAX =
R
=
4mA
VO ON
o
65Ω AT 25 C
RON
50pF
VCC
INPUT
VL
700
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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