TI1 CD4021B-Q1 Cmos 8-stage static shift register Datasheet

CD4021B-Q1
www.ti.com
SCHS378 – MARCH 2010
CMOS 8-STAGE STATIC SHIFT REGISTER
Check for Samples: CD4021B-Q1
FEATURES
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Medium-Speed Operation: 12-MHz (Typ) Clock
Rate at VDD – VSS = 10 V
Fully Static Operation
Eight Master-Slave Flip-Flops Plus Output
Buffering and Control Gating
100% Tested for Quiescent Current at 20 V
Maximum Input Current of 1 µA at 18 V Over
Full Package-Temperature Range:
100 nA at 18 V and 25°C
Noise Margin (Full Package-Temperature
Range):
– 1 V at VDD = 5 V
– 2 V at VDD = 10 V
– 2.5 V at VDD = 15 V
Standardized Symmetrical Output
Characteristics
5-V, 10-V, and 15-V Parametric Ratings
•
•
Meets All Requirements of JEDEC Tentative
Standard No. 13B, "Standard Specifications for
Description of 'B' Series CMOS Devices"
Latch-Up Performance Meets 50 mA per JESD
78, Class I
APPLICATIONS
•
•
•
Parallel Input/Serial Output Data Queuing
Parallel-to-Serial Data Conversion
General-Purpose Register
D PACKAGE
(TOP VIEW)
DESCRIPTION
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each
register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q"
outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register
synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous
with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage
register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL
input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the
positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when
asynchronous parallel entry is made. Register expansion using multiple packages is permitted.
The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes),
16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
CD4010BQDRQ1
TOP-SIDE MARKING
CD4021BQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CD4021B-Q1
SCHS378 – MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Functional Diagram
Logic Diagram
2
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CD4021B-Q1
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SCHS378 – MARCH 2010
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VDD
DC supply voltage range (voltage referenced to VSS terminal)
Input voltage range, all inputs
DC input current, any one input
VALUE
UNIT
–0.5 to +20
V
–0.5 to VDD +0.5
V
±10
mA
TA = –40°C to +100°C
500
TA = +100°C to +125°C
Derate Linearity at
12mW/°C to 20 mW
mW
100
mW
–40 to +125
°C
PD
Power dissipation per package
PD
Device dissipation per output transistor
TA
Operating temperature range
Tstg
Storage temperature range
–65 to +150
°C
Human-body model (HBM)
ESD
Electrostatic discharge rating (2)
Machine model (MM)
200
Charged-Device Model (CDM)
1000
Latch-up performance per JESD 78, Class I
(1)
(2)
2000
50
V
mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Tested in accordance with AEC-Q100.
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CD4021B-Q1
SCHS378 – MARCH 2010
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RECOMMENDED OPERATING CONDITIONS
At TA = 25°C, unless other wise specified. For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges.
VDD
Supply voltage range
(TA = full package-temperature range)
tW
fCL
trCL,
tfCL
Clock pulse width
Clock frequency
Clock rise and fall time
MIN
MAX
3
18
5
180
10
80
15
50
Serial input (referred to CL)
Parallel inputs
CD4014B (referred to CL)
ts
Set-up time
Parallel inputs
CD4021B (referred to P/S)
Parallel/Serial Control
CD4014B (referred to CL)
tW
tREM
4
Parallel/serial pulse width
Parallel/serial removal time
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V
ns
5
3
10
6
15
8.5
5
15
10
15
15
UNIT
MHz
µs
15
5
120
10
80
15
60
5
80
10
50
15
40
5
50
10
30
15
20
5
180
10
80
15
60
5
160
10
80
15
50
5
280
10
140
15
100
ns
ns
ns
ns
ns
ns
Copyright © 2010, Texas Instruments Incorporated
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CD4021B-Q1
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SCHS378 – MARCH 2010
STATIC ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
PARAMETER
IDD Max
IOL Min
IOH Min
VOL Max
VOH Min
VIL Max
VIH Min
IIN Max
VD
(V)
VIN
(V)
Quiescent device current
Output low (sink) current
Output high (source) current
Input current
–40
+85
+125
+25
5
UNIT
150
150
0.5
5
10
300
300
0.04
5
0.10
10
20
600
600
0.04
10
0.15
15
100
3000
3000
0.04
20
0.08
100
0.20
20
0.61
0.42
0.36
0.5
5
1.5
1.1
0.9
0.51
1
0.5
0.10
10
4
2.8
2.4
1.3
2.6
1.5
0.15
15
–0.61
–0.42
–0.36
3.4
6.8
4.6
0.5
5
–1.8
–1.3
–1.15
–0.51
–1
2.5
0.5
5
–1.5
–1.1
–0.9
–1.6
–3.2
9.5
0.10
10
–4
–2.8
–2.4
–1.3
–2.6
13.5
0.15
15
–4.2
–3.4
–6.8
0.5
5
0.05
0
0.05
0.10
10
0.05
0
0.05
0.15
15
0.05
0
0.05
0.5
5
4.95
4.95
5
0.10
10
9.95
9.95
10
0.15
14.95
15
Output voltage: high level
Input high voltage
VDD
(V)
0.4
Output voltage: low level
Input low voltage
LIMITS AT INDICATED TEMPERATURES (°C)
15
14.95
0.5, 4.5
5
1.5
1, 9
10
3
1.5,
13.5
15
4
0.5, 4.5
5
3.5
1, 9
10
7
1.5,
13.5
15
11
0, 18
18
±0.1
±1
mA
Product Folder Link(s): CD4021B-Q1
V
1.5
3
4
V
3.5
7
11
±1
±10–5
±0.1
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µA
µA
5
CD4021B-Q1
SCHS378 – MARCH 2010
www.ti.com
DYNAMIC ELECTRICAL CHARACTERISTICS
TA = 25°C, Input tr/tf = 20 ns, CL = 50 pF, RL 200 kΩ
PARAMETER
tPLH,
tPHL
tTHL,
tTLH
TEST CONDITIONS
Propagation delay time
Transition time
Maximum clock input (1)
fCL
Minimum clock pulse width (1)
tW
trCL,
tfCL
Clock rise and fall time
(2) (1)
Serial input (referred to CL)
Parallel inputs (referred to CL)
Minimum setup time (1)
ts
Parallel inputs (referred to P/S)
Serial in, Parallel in, Parallel/Serial Control
Minimum hold time (1)
tH
VDD
TYP
MAX
5
MIN
160
320
10
80
160
15
30
120
5
100
200
10
50
100
15
40
80
5
3
6
10
6
12
15
8.5
17
Minimum P/S pulse width (1)
tWH
tREM
CI
(1)
(2)
6
Minimum P/S removal time (1)
Average input capacitance (1)
ns
ns
MHz
5
90
180
10
40
80
15
25
50
5
15
10
15
15
15
5
60
120
10
40
80
15
30
60
5
40
80
10
25
50
15
20
40
5
25
50
10
15
30
15
10
20
5
90
180
10
40
80
15
30
60
5
0
10
0
15
UNIT
ns
µs
ns
ns
0
5
80
160
10
40
80
15
25
50
5
140
280
10
70
140
15
50
100
5
7.5
ns
ns
pF
Not production tested
If more than one unit is cascaded, trCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
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SCHS378 – MARCH 2010
Typical Characteristics
Figure 1. Typical Output Low (Sink) Current Characteristics
Figure 2. Minimum Output Low (Sink) Current Characteristics
Figure 3. Typical Output High (Source) Current Characteristics
Figure 4. Minimum Output High (Source) Current
Characteristics
Figure 5. Typical Transition Time as a Function of Load
Capacitance
Figure 6. Typical Propagation Delay Times as a Function of
Load Capacitance
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Typical Characteristics (continued)
Figure 7. Typical Dynamic Power Dissipation as a Function of Clock Input Frequency
8
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PARAMETER MEASUREMENT INFORMATION
Figure 8. Dynamic Power Dissipation Test Circuit
Figure 9. Quiescent Device Current Test Circuit
Figure 10. Input Voltage Test Circuit
Figure 11. Input Current Test Circuit
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Note:
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Dimensions in parentheses are in millimeters and are dereived from the basic inch dimensions as indicated. Grid
graduation are in mils (10–3 inch).
Figure 12. Dimensions and Pad Layout
10
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PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
CD4021BQDRQ1
ACTIVE
SOIC
D
Pins Package Eco Plan (2)
Qty
16
2500 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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OTHER QUALIFIED VERSIONS OF CD4021B-Q1 :
CD4021B
• Catalog:
• Military: CD4021B-MIL
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
• Military - QML certified for Military and Defense Applications
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